diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 813640d..3ff1b44 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -1,7 +1,7 @@
 variables:
-  windows_vm: windows-2019
-  ubuntu_vm: ubuntu-22.04
-  macos_vm: macOS-12
+  windows_vm: windows-2022
+  ubuntu_vm: ubuntu-24.04
+  macos_vm: macOS-14
   ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
diff --git a/.mailmap b/.mailmap
index 952e1da..4d48349 100644
--- a/.mailmap
+++ b/.mailmap
@@ -38,7 +38,8 @@
 Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
 Dirk Behme <dirk.behme@googlemail.com>
 Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
-Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
+Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@microchip.com>
+Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@collabora.com>
 Fabio Estevam <fabio.estevam@nxp.com>
 Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
 Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 7c6c368..eef6353 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1754,6 +1754,15 @@
 F:	common/usb_storage.c
 F:	include/usb.h
 
+USB TCPM
+M:	Sebastian Reichel <sebastian.reichel@collabora.com>
+S:	Maintained
+F:	cmd/tcpm.c
+F:	doc/usage/cmd/tcpm.rst
+F:	drivers/usb/tcpm/
+F:	include/usb/pd.h
+F:	include/usb/tcpm.h
+
 USB xHCI
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
diff --git a/Makefile b/Makefile
index 2e0a2e9..6b9c00b 100644
--- a/Makefile
+++ b/Makefile
@@ -887,6 +887,7 @@
 libs-y += drivers/usb/musb-new/
 libs-y += drivers/usb/isp1760/
 libs-y += drivers/usb/phy/
+libs-y += drivers/usb/tcpm/
 libs-y += drivers/usb/ulpi/
 ifdef CONFIG_POST
 libs-y += post/
@@ -1429,18 +1430,12 @@
 # or a generator script
 # NOTE: Please do not use this. We are migrating away from Makefile rules to use
 # binman instead.
-ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
-U_BOOT_ITS := u-boot.its
-$(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
-	$(call if_changed,copy)
-else
 ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
 U_BOOT_ITS := u-boot.its
 $(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
 	$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
 	$(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
 endif
-endif
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index af5431c..8b9ced1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1140,7 +1140,6 @@
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 
 dtb-$(CONFIG_STM32MP13X) += \
-	stm32mp135f-dhcor-dhsbc.dtb \
 	stm32mp135f-dk.dtb
 
 dtb-$(CONFIG_STM32MP15X) += \
@@ -1156,13 +1155,7 @@
 	stm32mp157c-ed1-scmi.dtb \
 	stm32mp157c-ev1.dtb \
 	stm32mp157c-ev1-scmi.dtb \
-	stm32mp157c-odyssey.dtb \
-	stm32mp15xx-dhcom-drc02.dtb \
-	stm32mp15xx-dhcom-pdk2.dtb \
-	stm32mp15xx-dhcom-picoitx.dtb \
-	stm32mp15xx-dhcor-avenger96.dtb \
-	stm32mp15xx-dhcor-drc-compact.dtb \
-	stm32mp15xx-dhcor-testbench.dtb
+	stm32mp157c-odyssey.dtb
 
 dtb-$(CONFIG_STM32MP25X) += \
 	stm32mp257f-ev1.dtb
diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi
index 28087a3..6b52116 100644
--- a/arch/arm/dts/k3-j722s-binman.dtsi
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -8,6 +8,56 @@
 #if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM)
 
 &binman {
+	tiboot3-j722s-hs-evm.bin {
+		filename = "tiboot3-j722s-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				  <&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c7a800>;
+		};
+
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
 	tiboot3-j722s-hs-fs-evm.bin {
 		filename = "tiboot3-j722s-hs-fs-evm.bin";
 		symlink = "tiboot3.bin";
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 4dd17ff..b0ad115 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2023 Collabora Ltd.
  */
 
+#include <dt-bindings/usb/pd.h>
 #include "rk3588-u-boot.dtsi"
 
 &fspim2_pins {
@@ -10,6 +11,33 @@
 	bootph-some-ram;
 };
 
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4m1_xfer>;
+	status = "okay";
+
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "sink";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
+				<PDO_VAR(5000, 20000, 5000)>;
+		};
+	};
+};
+
 &sdhci {
 	cap-mmc-highspeed;
 	mmc-hs200-1_8v;
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
deleted file mode 100644
index fc1c48a..0000000
--- a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
+++ /dev/null
@@ -1,383 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2024 Marek Vasut <marex@denx.de>
- *
- * DHCOR STM32MP13 variant:
- * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
- * DHCOR PCB number: 718-100 or newer
- * DHSBC PCB number: 719-100 or newer
- */
-
-/dts-v1/;
-
-#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
-#include "stm32mp135.dtsi"
-#include "stm32mp13xf.dtsi"
-#include "stm32mp13xx-dhcor-som.dtsi"
-
-/ {
-	model = "DH electronics STM32MP135F DHCOR DHSBC";
-	compatible = "dh,stm32mp135f-dhcor-dhsbc",
-		     "dh,stm32mp135f-dhcor-som",
-		     "st,stm32mp135";
-
-	aliases {
-		ethernet0 = &eth1;
-		ethernet1 = &eth2;
-		serial2 = &usart1;
-		serial3 = &usart2;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&adc_1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>;
-	vdda-supply = <&vdd_adc>;
-	vref-supply = <&vdd_adc>;
-	status = "okay";
-
-	adc1: adc@0 {
-		status = "okay";
-
-		/*
-		 * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
-		 * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
-		 * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
-		 * Use arbitrary margin here (e.g. 5us).
-		 *
-		 * The pinmux pins must be set as ANALOG, use datasheet
-		 * DS13483 Table 7. STM32MP135C/F ball definitions to
-		 * find out which 'pin name' maps to which 'additional
-		 * functions', which lists the mapping between pin and
-		 * ADC channel. In this case, PA5 maps to ADC1_INP2 and
-		 * PF13 maps to ADC1_INP11 .
-		 */
-		channel@2 {
-			reg = <2>;
-			st,min-sample-time-ns = <5000>;
-		};
-
-		channel@11 {
-			reg = <11>;
-			st,min-sample-time-ns = <5000>;
-		};
-
-		/* Expansion connector: INP12:pin29 */
-		channel@12 {
-			reg = <12>;
-			st,min-sample-time-ns = <5000>;
-		};
-	};
-};
-
-&eth1 {
-	status = "okay";
-	pinctrl-0 = <&eth1_rgmii_pins_a>;
-	pinctrl-1 = <&eth1_rgmii_sleep_pins_a>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy1>;
-	st,ext-phyclk;
-	nvmem-cells = <&ethernet_mac1_address>;
-	nvmem-cell-names = "mac-address";
-
-	mdio1 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-
-		ethphy1: ethernet-phy@1 {
-			/* RTL8211F */
-			compatible = "ethernet-phy-id001c.c916",
-				     "ethernet-phy-ieee802.3-c22";
-			interrupt-parent = <&gpiog>;
-			interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
-			reg = <1>;
-			reset-assert-us = <15000>;
-			reset-deassert-us = <55000>;
-			reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&eth2 {
-	status = "okay";
-	pinctrl-0 = <&eth2_rgmii_pins_a>;
-	pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy2>;
-	st,ext-phyclk;
-	nvmem-cells = <&ethernet_mac2_address>;
-	nvmem-cell-names = "mac-address";
-
-	mdio1 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-
-		ethphy2: ethernet-phy@1 {
-			/* RTL8211F */
-			compatible = "ethernet-phy-id001c.c916",
-				     "ethernet-phy-ieee802.3-c22";
-			interrupt-parent = <&gpiog>;
-			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
-			reg = <1>;
-			reset-assert-us = <15000>;
-			reset-deassert-us = <55000>;
-			reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&gpioa {
-	gpio-line-names = "", "", "", "",
-			  "", "DHSBC_USB_PWR_CC1", "", "",
-			  "", "", "", "DHSBC_nETH1_RST",
-			  "", "DHCOR_HW-CODING_0", "", "";
-};
-
-&gpiob {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "DHCOR_BT_HOST_WAKE",
-			  "", "", "", "",
-			  "", "DHSBC_nTPM_CS", "", "";
-};
-
-&gpioc {
-	gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS",
-			  "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiod {
-	gpio-line-names = "", "", "", "",
-			  "", "DHCOR_RAM-CODING_0", "", "",
-			  "", "DHCOR_RAM-CODING_1", "", "",
-			  "", "", "", "";
-};
-
-&gpioe {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "", "DHSBC_nTPM_RST", "", "",
-			  "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", "";
-};
-
-&gpiof {
-	gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "",
-			  "", "", "", "",
-			  "", "", "", "",
-			  "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", "";
-};
-
-&gpiog {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "",
-			  "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB";
-};
-
-&gpioi {
-	gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1",
-			  "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT",
-			  "DHSBC_BOOT0", "DHSBC_BOOT1",
-			  "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS";
-};
-
-&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&i2c1_pins_a>;
-	pinctrl-1 = <&i2c1_sleep_pins_a>;
-	i2c-scl-rising-time-ns = <96>;
-	i2c-scl-falling-time-ns = <3>;
-	clock-frequency = <400000>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&i2c5_pins_b>;
-	pinctrl-1 = <&i2c5_sleep_pins_b>;
-	i2c-scl-rising-time-ns = <96>;
-	i2c-scl-falling-time-ns = <3>;
-	clock-frequency = <400000>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can1_pins_a>;
-	pinctrl-1 = <&m_can1_sleep_pins_a>;
-	status = "okay";
-};
-
-&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can2_pins_a>;
-	pinctrl-1 = <&m_can2_sleep_pins_a>;
-	status = "okay";
-};
-
-&pwr_regulators {
-	vdd-supply = <&vdd>;
-	vdd_3v3_usbfs-supply = <&vdd_usb>;
-	status = "okay";
-};
-
-&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */
-	clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
-	clock-names = "pclk", "x8k", "x11k";
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>;
-	pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>;
-};
-
-&scmi_voltd {
-	status = "disabled";
-};
-
-&spi2 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&spi2_pins_a>;
-	pinctrl-1 = <&spi2_sleep_pins_a>;
-	cs-gpios = <&gpiob 13 0>;
-	status = "okay";
-
-	st33htph: tpm@0 {
-		compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-	};
-};
-
-&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&spi3_pins_a>;
-	pinctrl-1 = <&spi3_sleep_pins_a>;
-	cs-gpios = <&gpiof 3 0>;
-	status = "disabled";
-};
-
-&timers5 { /* Expansion connector: CH3:pin31 */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-
-	pwm {
-		pinctrl-0 = <&pwm5_pins_a>;
-		pinctrl-1 = <&pwm5_sleep_pins_a>;
-		pinctrl-names = "default", "sleep";
-		status = "okay";
-	};
-	timer@4 {
-		status = "okay";
-	};
-};
-
-&timers13 { /* Expansion connector: CH1:pin32 */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-
-	pwm {
-		pinctrl-0 = <&pwm13_pins_a>;
-		pinctrl-1 = <&pwm13_sleep_pins_a>;
-		pinctrl-names = "default", "sleep";
-		status = "okay";
-	};
-	timer@12 {
-		status = "okay";
-	};
-};
-
-&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
-	pinctrl-names = "default", "sleep", "idle";
-	pinctrl-0 = <&usart1_pins_b>;
-	pinctrl-1 = <&usart1_sleep_pins_b>;
-	pinctrl-2 = <&usart1_idle_pins_b>;
-	status = "okay";
-};
-
-&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
-	pinctrl-names = "default", "sleep", "idle";
-	pinctrl-0 = <&usart2_pins_b>;
-	pinctrl-1 = <&usart2_sleep_pins_b>;
-	pinctrl-2 = <&usart2_idle_pins_b>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&usbh_ehci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbh_ohci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbotg_hs {
-	dr_mode = "peripheral";
-	phys = <&usbphyc_port1 0>;
-	phy-names = "usb2-phy";
-	usb33d-supply = <&usb33>;
-	status = "okay";
-};
-
-&usbphyc {
-	status = "okay";
-	vdda1v1-supply = <&reg11>;
-	vdda1v8-supply = <&reg18>;
-};
-
-&usbphyc_port0 {
-	phy-supply = <&vdd_usb>;
-	st,current-boost-microamp = <1000>;
-	st,decrease-hs-slew-rate;
-	st,tune-hs-dc-level = <2>;
-	st,enable-hs-rftime-reduction;
-	st,trim-hs-current = <11>;
-	st,trim-hs-impedance = <2>;
-	st,tune-squelch-level = <1>;
-	st,enable-hs-rx-gain-eq;
-	st,no-hs-ftime-ctrl;
-	st,no-lsfs-sc;
-	connector {
-		compatible = "usb-a-connector";
-		vbus-supply = <&vbus_sw>;
-	};
-};
-
-&usbphyc_port1 {
-	phy-supply = <&vdd_usb>;
-	st,current-boost-microamp = <1000>;
-	st,decrease-hs-slew-rate;
-	st,tune-hs-dc-level = <2>;
-	st,enable-hs-rftime-reduction;
-	st,trim-hs-current = <11>;
-	st,trim-hs-impedance = <2>;
-	st,tune-squelch-level = <1>;
-	st,enable-hs-rx-gain-eq;
-	st,no-hs-ftime-ctrl;
-	st,no-lsfs-sc;
-	connector {
-		compatible = "gpio-usb-b-connector", "usb-b-connector";
-		vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
-		label = "Type-C";
-		self-powered;
-		type = "micro";
-	};
-};
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index fe56f05..66d4c40 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -56,6 +56,24 @@
 			status = "okay";
 		};
 	};
+
+	cpu0_opp_table: cpu0-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		bootph-pre-ram;
+		opp-650000000 {
+			bootph-pre-ram;
+			opp-hz = /bits/ 64 <650000000>;
+			opp-microvolt = <1200000>;
+			opp-supported-hw = <0x1>;
+		};
+		opp-800000000 {
+			bootph-pre-ram;
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1350000>;
+			opp-supported-hw = <0x2>;
+		};
+	};
 };
 
 &bsec {
@@ -82,14 +100,10 @@
 	bootph-all;
 };
 
-&cpu0_opp_table {
-	bootph-pre-ram;
-	opp-650000000 {
-		bootph-pre-ram;
-	};
-	opp-800000000 {
-		bootph-pre-ram;
-	};
+&cpu0 {
+	nvmem-cells = <&part_number_otp>;
+	nvmem-cell-names = "part_number";
+	operating-points-v2 = <&cpu0_opp_table>;
 };
 
 &gpioa {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi b/arch/arm/dts/stm32mp151a-dhcor-testbench-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi
rename to arch/arm/dts/stm32mp151a-dhcor-testbench-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/stm32mp153c-dhcom-drc02-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
rename to arch/arm/dts/stm32mp153c-dhcom-drc02-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi b/arch/arm/dts/stm32mp153c-dhcor-drc-compact-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi
rename to arch/arm/dts/stm32mp153c-dhcor-drc-compact-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dhcor-avenger96-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
rename to arch/arm/dts/stm32mp157a-dhcor-avenger96-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dhcom-pdk2-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
rename to arch/arm/dts/stm32mp157c-dhcom-pdk2-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dhcom-picoitx-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi
rename to arch/arm/dts/stm32mp157c-dhcom-picoitx-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
deleted file mode 100644
index 90625bf..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcom-som.dtsi"
-#include "stm32mp15xx-dhcom-drc02.dtsi"
-
-/ {
-	model = "DH Electronics STM32MP15xx DHCOM DRC02";
-	compatible = "dh,stm32mp15xx-dhcom-drc02",
-		     "dh,stm32mp15xx-dhcom-som",
-		     "st,stm32mp1xx";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
deleted file mode 100644
index 35b1034..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&adc {
-	status = "disabled";
-};
-
-&dac {
-	status = "disabled";
-};
-
-&gpiob {
-	/*
-	 * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
-	 * GPIO line, however the STM32 UART driver assumes RX happens
-	 * during TX anyway and that it only controls drive enable DE
-	 * line. Hence, the RX is always enabled here.
-	 */
-	rs485-rx-en-hog {
-		gpio-hog;
-		gpios = <8 0>;
-		output-low;
-		line-name = "rs485-rx-en";
-	};
-};
-
-&gpiod {
-	gpio-line-names = "", "", "", "",
-			  "", "", "DHCOM-B", "",
-			  "", "", "", "DRC02-Out1",
-			  "DRC02-Out2", "", "", "";
-};
-
-&gpioi {
-	gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I",
-			  "DHCOM-R", "DHCOM-M", "", "",
-			  "DRC02-In2", "", "", "",
-			  "", "", "", "";
-
-	/*
-	 * NOTE: The USB Hub on the DRC02 needs a reset signal to be
-	 * pulled high in order to be detected by the USB Controller.
-	 * This signal should be handled by USB power sequencing in
-	 * order to reset the Hub when USB bus is powered down, but
-	 * so far there is no such functionality.
-	 */
-	usb-hub-hog {
-		gpio-hog;
-		gpios = <2 0>;
-		output-high;
-		line-name = "usb-hub-reset";
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-
-	eeprom@50 {
-		compatible = "atmel,24c04";
-		reg = <0x50>;
-		pagesize = <16>;
-	};
-};
-
-&i2c4 {
-	touchscreen@49 {
-		status = "disabled";
-	};
-};
-
-&i2c5 {	/* TP7/TP8 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&sdmmc3 {
-	/*
-	 * On DRC02, the SoM does not have SDIO WiFi. The pins
-	 * are used for on-board microSD slot instead.
-	 */
-	/delete-property/broken-cd;
-	cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
-	disable-wp;
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins_a>;
-	cs-gpios = <&gpioz 3 0>;
-	/* Use PIO for the display */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "disabled";	/* Enable once there is display driver */
-	/*
-	 * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
-	 * also connected to the display board connector.
-	 */
-};
-
-&usart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usart3_pins_a>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-/*
- * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
- *       however the STM32MP1 pinmux cannot map them to UART4 .
- */
-
-&uart8 {	/* RS485 */
-	linux,rs485-enabled-at-boot-time;
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart8_pins_a>;
-	rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&usbh_ehci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbphyc {
-	status = "okay";
-};
-
-&usbphyc_port0 {
-	phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
-	phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
deleted file mode 100644
index b2e450a..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcom-som.dtsi"
-#include "stm32mp15xx-dhcom-pdk2.dtsi"
-
-/ {
-	model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
-	compatible = "dh,stm32mp15xx-dhcom-pdk2",
-		     "dh,stm32mp15xx-dhcom-som",
-		     "st,stm32mp15x";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
deleted file mode 100644
index 5f586f0..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
+++ /dev/null
@@ -1,329 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	clk_ext_audio_codec: clock-codec {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-	};
-
-	display_bl: display-bl {
-		compatible = "pwm-backlight";
-		pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
-		brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
-		default-brightness-level = <8>;
-		enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
-		power-supply = <&reg_panel_bl>;
-		status = "okay";
-	};
-
-	gpio-keys-polled {
-		compatible = "gpio-keys-polled";
-		poll-interval = <20>;
-
-		/*
-		 * The EXTi IRQ line 3 is shared with ethernet,
-		 * so mark this as polled GPIO key.
-		 */
-		button-0 {
-			label = "TA1-GPIO-A";
-			linux,code = <KEY_A>;
-			gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
-		};
-
-		/*
-		 * The EXTi IRQ line 6 is shared with touchscreen,
-		 * so mark this as polled GPIO key.
-		 */
-		button-1 {
-			label = "TA2-GPIO-B";
-			linux,code = <KEY_B>;
-			gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
-		};
-
-		/*
-		 * The EXTi IRQ line 0 is shared with PMIC,
-		 * so mark this as polled GPIO key.
-		 */
-		button-2 {
-			label = "TA3-GPIO-C";
-			linux,code = <KEY_C>;
-			gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		button-3 {
-			label = "TA4-GPIO-D";
-			linux,code = <KEY_D>;
-			gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
-			wakeup-source;
-		};
-	};
-
-	led {
-		compatible = "gpio-leds";
-
-		led-0 {
-			label = "green:led5";
-			gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-			status = "disabled";
-		};
-
-		led-1 {
-			label = "green:led6";
-			gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-2 {
-			label = "green:led7";
-			gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-3 {
-			label = "green:led8";
-			gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	panel {
-		compatible = "edt,etm0700g0edh6";
-		backlight = <&display_bl>;
-		power-supply = <&reg_panel_bl>;
-
-		port {
-			lcd_panel_in: endpoint {
-				remote-endpoint = <&lcd_display_out>;
-			};
-		};
-	};
-
-	reg_panel_bl: regulator-panel-bl {
-		compatible = "regulator-fixed";
-		regulator-name = "panel_backlight";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&reg_panel_supply>;
-	};
-
-	reg_panel_supply: regulator-panel-supply {
-		compatible = "regulator-fixed";
-		regulator-name = "panel_supply";
-		regulator-min-microvolt = <24000000>;
-		regulator-max-microvolt = <24000000>;
-	};
-
-	sound {
-		compatible = "audio-graph-card";
-		routing =
-			"MIC_IN", "Capture",
-			"Capture", "Mic Bias",
-			"Playback", "HP_OUT";
-		dais = <&sai2a_port &sai2b_port>;
-		status = "okay";
-	};
-};
-
-&cec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&cec_pins_a>;
-	status = "okay";
-};
-
-&i2c2 {	/* Header X22 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&i2c5 {	/* Header X21 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-
-	sgtl5000: codec@a {
-		compatible = "fsl,sgtl5000";
-		reg = <0x0a>;
-		#sound-dai-cells = <0>;
-		clocks = <&clk_ext_audio_codec>;
-		VDDA-supply = <&v3v3>;
-		VDDIO-supply = <&vdd>;
-
-		sgtl5000_port: port {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			sgtl5000_tx_endpoint: endpoint@0 {
-				reg = <0>;
-				remote-endpoint = <&sai2a_endpoint>;
-				frame-master = <&sgtl5000_tx_endpoint>;
-				bitclock-master = <&sgtl5000_tx_endpoint>;
-			};
-
-			sgtl5000_rx_endpoint: endpoint@1 {
-				reg = <1>;
-				remote-endpoint = <&sai2b_endpoint>;
-				frame-master = <&sgtl5000_rx_endpoint>;
-				bitclock-master = <&sgtl5000_rx_endpoint>;
-			};
-		};
-
-	};
-
-	touchscreen@38 {
-		compatible = "edt,edt-ft5406";
-		reg = <0x38>;
-		interrupt-parent = <&gpioc>;
-		interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
-	};
-};
-
-&ltdc {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&ltdc_pins_b>;
-	pinctrl-1 = <&ltdc_sleep_pins_b>;
-	status = "okay";
-
-	port {
-		lcd_display_out: endpoint {
-			remote-endpoint = <&lcd_panel_in>;
-		};
-	};
-};
-
-&sai2 {
-	clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
-	clock-names = "pclk", "x8k", "x11k";
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>;
-	pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>;
-	status = "okay";
-
-	sai2a: audio-controller@4400b004 {
-		#clock-cells = <0>;
-		dma-names = "tx";
-		clocks = <&rcc SAI2_K>;
-		clock-names = "sai_ck";
-		status = "okay";
-
-		sai2a_port: port {
-			sai2a_endpoint: endpoint {
-				remote-endpoint = <&sgtl5000_tx_endpoint>;
-				format = "i2s";
-				mclk-fs = <512>;
-				dai-tdm-slot-num = <2>;
-				dai-tdm-slot-width = <16>;
-			};
-		};
-	};
-
-	sai2b: audio-controller@4400b024 {
-		dma-names = "rx";
-		st,sync = <&sai2a 2>;
-		clocks = <&rcc SAI2_K>, <&sai2a>;
-		clock-names = "sai_ck", "MCLK";
-		status = "okay";
-
-		sai2b_port: port {
-			sai2b_endpoint: endpoint {
-				remote-endpoint = <&sgtl5000_rx_endpoint>;
-				format = "i2s";
-				mclk-fs = <512>;
-				dai-tdm-slot-num = <2>;
-				dai-tdm-slot-width = <16>;
-			};
-		};
-	};
-};
-
-&timers2 {
-	/* spare dmas for other usage (un-delete to enable pwm capture) */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-	pwm2: pwm {
-		pinctrl-0 = <&pwm2_pins_a>;
-		pinctrl-names = "default";
-		status = "okay";
-	};
-	timer@1 {
-		status = "okay";
-	};
-};
-
-&usart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usart3_pins_a>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&uart8 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
-	uart-has-rtscts;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&usbh_ehci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbotg_hs {
-	dr_mode = "otg";
-	pinctrl-0 = <&usbotg_hs_pins_a>;
-	pinctrl-names = "default";
-	phy-names = "usb2-phy";
-	phys = <&usbphyc_port1 0>;
-	vbus-supply = <&vbus_otg>;
-	status = "okay";
-};
-
-&usbphyc {
-	status = "okay";
-};
-
-&usbphyc_port0 {
-	phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
-	phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
deleted file mode 100644
index 3e90810..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcom-som.dtsi"
-#include "stm32mp15xx-dhcom-picoitx.dtsi"
-
-/ {
-	model = "DH Electronics STM32MP15xx DHCOM PicoITX";
-	compatible = "dh,stm32mp15xx-dhcom-picoitx",
-		     "dh,stm32mp15xx-dhcom-som",
-		     "st,stm32mp1xx";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
deleted file mode 100644
index abc5953..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	led {
-		compatible = "gpio-leds";
-
-		led-0 {
-			label = "yellow:led";
-			gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-};
-
-&adc {
-	status = "disabled";
-};
-
-&dac {
-	status = "disabled";
-};
-
-&fmc {
-	status = "disabled";
-};
-
-&gpioa {
-	/*
-	 * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
-	 * port power. This signal should be handled by USB power sequencing
-	 * in order to turn on port power when USB bus is powered up, but so
-	 * far there is no such functionality.
-	 */
-	usb-port-power-hog {
-		gpio-hog;
-		gpios = <13 0>;
-		output-low;
-		line-name = "usb-port-power";
-	};
-};
-
-&gpioc {
-	gpio-line-names = "", "", "", "",
-			  "", "", "PicoITX-In1", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiod {
-	gpio-line-names = "", "", "", "",
-			  "", "", "DHCOM-B", "",
-			  "", "", "", "PicoITX-Out1",
-			  "PicoITX-Out2", "", "", "";
-};
-
-&gpiog {
-	gpio-line-names = "PicoITX-In2", "", "", "",
-			  "", "", "", "",
-			  "DHCOM-L", "", "", "",
-			  "", "", "", "";
-};
-
-&i2c2 {	/* On board-to-board connector (optional) */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&i2c5 {	/* On board-to-board connector */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&ksz8851 {
-	status = "disabled";
-};
-
-&usart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usart3_pins_a>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&uart8 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&usbh_ehci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbh_ohci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbotg_hs {
-	dr_mode = "otg";
-	pinctrl-0 = <&usbotg_hs_pins_a>;
-	pinctrl-names = "default";
-	phy-names = "usb2-phy";
-	phys = <&usbphyc_port1 0>;
-	vbus-supply = <&vbus_otg>;
-	status = "okay";
-};
-
-&usbphyc {
-	status = "okay";
-};
-
-&usbphyc_port0 {
-	phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
-	phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
deleted file mode 100644
index d3b85a8..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
+++ /dev/null
@@ -1,544 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
- */
-
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
-	aliases {
-		ethernet0 = &ethernet0;
-		ethernet1 = &ksz8851;
-		rtc0 = &hwrtc;
-		rtc1 = &rtc;
-	};
-
-	memory@c0000000 {
-		device_type = "memory";
-		reg = <0xC0000000 0x40000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		mcuram2: mcuram2@10000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10000000 0x40000>;
-			no-map;
-		};
-
-		vdev0vring0: vdev0vring0@10040000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10040000 0x1000>;
-			no-map;
-		};
-
-		vdev0vring1: vdev0vring1@10041000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10041000 0x1000>;
-			no-map;
-		};
-
-		vdev0buffer: vdev0buffer@10042000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10042000 0x4000>;
-			no-map;
-		};
-
-		mcuram: mcuram@30000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x30000000 0x40000>;
-			no-map;
-		};
-
-		retram: retram@38000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x38000000 0x10000>;
-			no-map;
-		};
-	};
-
-	ethernet_vio: vioregulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vio";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vdd>;
-	};
-};
-
-&adc {
-	vdd-supply = <&vdd>;
-	vdda-supply = <&vdda>;
-	vref-supply = <&vdda>;
-	status = "okay";
-
-	adc1: adc@0 {
-		st,min-sample-time-nsecs = <5000>;
-		st,adc-channels = <0>;
-		status = "okay";
-	};
-
-	adc2: adc@100 {
-		st,adc-channels = <1>;
-		st,min-sample-time-nsecs = <5000>;
-		status = "okay";
-	};
-};
-
-&crc1 {
-	status = "okay";
-};
-
-&dac {
-	pinctrl-names = "default";
-	pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
-	vref-supply = <&vdda>;
-	status = "okay";
-
-	dac1: dac@1 {
-		status = "okay";
-	};
-	dac2: dac@2 {
-		status = "okay";
-	};
-};
-
-&dts {
-	status = "okay";
-};
-
-&ethernet0 {
-	status = "okay";
-	pinctrl-0 = <&ethernet0_rmii_pins_c &mco2_pins_a>;
-	pinctrl-1 = <&ethernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rmii";
-	max-speed = <100>;
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-
-		phy0: ethernet-phy@1 {
-			reg = <1>;
-			/* LAN8710Ai */
-			compatible = "ethernet-phy-id0007.c0f0",
-				     "ethernet-phy-ieee802.3-c22";
-			clocks = <&rcc CK_MCO2>;
-			reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <500>;
-			reset-deassert-us = <500>;
-			smsc,disable-energy-detect;
-			interrupt-parent = <&gpioi>;
-			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-		};
-	};
-};
-
-&fmc {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&fmc_pins_b>;
-	pinctrl-1 = <&fmc_sleep_pins_b>;
-	status = "okay";
-
-	ksz8851: ethernet@1,0 {
-		compatible = "micrel,ks8851-mll";
-		reg = <1 0x0 0x2>, <1 0x2 0x20000>;
-		interrupt-parent = <&gpioc>;
-		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-		bank-width = <2>;
-
-		/* Timing values are in nS */
-		st,fmc2-ebi-cs-mux-enable;
-		st,fmc2-ebi-cs-transaction-type = <4>;
-		st,fmc2-ebi-cs-buswidth = <16>;
-		st,fmc2-ebi-cs-address-setup-ns = <5>;
-		st,fmc2-ebi-cs-address-hold-ns = <5>;
-		st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
-		st,fmc2-ebi-cs-data-setup-ns = <45>;
-		st,fmc2-ebi-cs-data-hold-ns = <1>;
-		st,fmc2-ebi-cs-write-address-setup-ns = <5>;
-		st,fmc2-ebi-cs-write-address-hold-ns = <5>;
-		st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
-		st,fmc2-ebi-cs-write-data-setup-ns = <45>;
-		st,fmc2-ebi-cs-write-data-hold-ns = <1>;
-	};
-};
-
-&gpioa {
-	gpio-line-names = "", "", "", "",
-			  "", "", "DHCOM-K", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiob {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "DHCOM-Q", "", "", "",
-			  "", "", "", "";
-};
-
-&gpioc {
-	gpio-line-names = "", "", "", "",
-			  "", "", "DHCOM-E", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiod {
-	gpio-line-names = "", "", "", "",
-			  "", "", "DHCOM-B", "",
-			  "", "", "", "DHCOM-F",
-			  "DHCOM-D", "", "", "";
-};
-
-&gpioe {
-	gpio-line-names = "", "", "", "",
-			  "", "", "DHCOM-P", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiof {
-	gpio-line-names = "", "", "", "DHCOM-A",
-			  "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiog {
-	gpio-line-names = "DHCOM-C", "", "", "",
-			  "", "", "", "",
-			  "DHCOM-L", "", "", "",
-			  "", "", "", "";
-};
-
-&gpioh {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "DHCOM-N",
-			  "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U",
-			  "DHCOM-T", "", "DHCOM-S", "";
-};
-
-&gpioi {
-	gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I",
-			  "DHCOM-R", "DHCOM-M", "", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&i2c4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c4_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-
-	hwrtc: rtc@32 {
-		compatible = "microcrystal,rv8803";
-		reg = <0x32>;
-	};
-
-	pmic: stpmic@33 {
-		compatible = "st,stpmic1";
-		reg = <0x33>;
-		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		status = "okay";
-
-		regulators {
-			compatible = "st,stpmic1-regulators";
-			ldo1-supply = <&v3v3>;
-			ldo2-supply = <&v3v3>;
-			ldo3-supply = <&vdd_ddr>;
-			ldo5-supply = <&v3v3>;
-			ldo6-supply = <&v3v3>;
-			pwr_sw1-supply = <&bst_out>;
-			pwr_sw2-supply = <&bst_out>;
-
-			vddcore: buck1 {
-				regulator-name = "vddcore";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd_ddr: buck2 {
-				regulator-name = "vdd_ddr";
-				regulator-min-microvolt = <1350000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd: buck3 {
-				regulator-name = "vdd";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				st,mask-reset;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			v3v3: buck4 {
-				regulator-name = "v3v3";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				regulator-over-current-protection;
-				regulator-initial-mode = <0>;
-			};
-
-			vdda: ldo1 {
-				regulator-name = "vdda";
-				regulator-always-on;
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <2900000>;
-				interrupts = <IT_CURLIM_LDO1 0>;
-			};
-
-			v2v8: ldo2 {
-				regulator-name = "v2v8";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				interrupts = <IT_CURLIM_LDO2 0>;
-			};
-
-			vtt_ddr: ldo3 {
-				regulator-name = "vtt_ddr";
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <750000>;
-				regulator-always-on;
-				regulator-over-current-protection;
-			};
-
-			vdd_usb: ldo4 {
-				regulator-name = "vdd_usb";
-				interrupts = <IT_CURLIM_LDO4 0>;
-			};
-
-			vdd_sd: ldo5 {
-				regulator-name = "vdd_sd";
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <2900000>;
-				interrupts = <IT_CURLIM_LDO5 0>;
-				regulator-boot-on;
-			};
-
-			v1v8: ldo6 {
-				regulator-name = "v1v8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO6 0>;
-			};
-
-			vref_ddr: vref_ddr {
-				regulator-name = "vref_ddr";
-				regulator-always-on;
-			};
-
-			bst_out: boost {
-				regulator-name = "bst_out";
-				interrupts = <IT_OCP_BOOST 0>;
-			};
-
-			vbus_otg: pwr_sw1 {
-				regulator-name = "vbus_otg";
-				interrupts = <IT_OCP_OTG 0>;
-			};
-
-			vbus_sw: pwr_sw2 {
-				regulator-name = "vbus_sw";
-				interrupts = <IT_OCP_SWOUT 0>;
-				regulator-active-discharge = <1>;
-			};
-		};
-
-		onkey {
-			compatible = "st,stpmic1-onkey";
-			interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
-			interrupt-names = "onkey-falling", "onkey-rising";
-			power-off-time-sec = <10>;
-			status = "okay";
-		};
-
-		watchdog {
-			compatible = "st,stpmic1-wdt";
-			status = "disabled";
-		};
-	};
-
-	touchscreen@49 {
-		compatible = "ti,tsc2004";
-		reg = <0x49>;
-		vio-supply = <&v3v3>;
-		interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>;
-	};
-
-	eeprom@50 {
-		compatible = "atmel,24c02";
-		reg = <0x50>;
-		pagesize = <16>;
-	};
-};
-
-&ipcc {
-	status = "okay";
-};
-
-&iwdg2 {
-	timeout-sec = <32>;
-	status = "okay";
-};
-
-&m4_rproc {
-	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
-			<&vdev0vring1>, <&vdev0buffer>;
-	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
-	mbox-names = "vq0", "vq1", "shutdown";
-	interrupt-parent = <&exti>;
-	interrupts = <68 1>;
-	status = "okay";
-};
-
-&pwr_regulators {
-	vdd-supply = <&vdd>;
-	vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&qspi {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&qspi_clk_pins_a
-		     &qspi_bk1_pins_a
-		     &qspi_cs1_pins_a>;
-	pinctrl-1 = <&qspi_clk_sleep_pins_a
-		     &qspi_bk1_sleep_pins_a
-		     &qspi_cs1_sleep_pins_a>;
-	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash0: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <108000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&rcc {
-	/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
-	clocks = <&rcc CK_MCO2>;
-	clock-names = "ETH_RX_CLK/ETH_REF_CLK";
-
-	/*
-	 * Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
-	 * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
-	 * so that MCO2 behaves as a divider for the ETHRX clock here.
-	 */
-	assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
-	assigned-clock-parents = <&rcc PLL4_P>;
-	assigned-clock-rates = <50000000>, <100000000>;
-};
-
-&rng1 {
-	status = "okay";
-};
-
-&rtc {
-	status = "okay";
-};
-
-&sdmmc1 {
-	pinctrl-names = "default", "opendrain", "sleep", "init";
-	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
-	pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>;
-	cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-	disable-wp;
-	st,sig-dir;
-	st,neg-edge;
-	st,use-ckin;
-	st,cmd-gpios = <&gpiod 2 0>;
-	st,ck-gpios = <&gpioc 12 0>;
-	st,ckin-gpios = <&gpioe 4 0>;
-	bus-width = <4>;
-	vmmc-supply = <&vdd_sd>;
-	status = "okay";
-};
-
-&sdmmc1_b4_pins_a {
-	/*
-	 * SD bus pull-up resistors:
-	 * - optional on SoMs with SD voltage translator
-	 * - mandatory on SoMs without SD voltage translator
-	 */
-	pins1 {
-		bias-pull-up;
-	};
-	pins2 {
-		bias-pull-up;
-	};
-};
-
-&sdmmc2 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
-	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
-	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	st,neg-edge;
-	bus-width = <8>;
-	vmmc-supply = <&v3v3>;
-	vqmmc-supply = <&v3v3>;
-	mmc-ddr-3_3v;
-	status = "okay";
-};
-
-&sdmmc3 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc3_b4_pins_a>;
-	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
-	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
-	broken-cd;
-	st,neg-edge;
-	bus-width = <4>;
-	vmmc-supply = <&v3v3>;
-	vqmmc-supply = <&v3v3>;
-	mmc-ddr-3_3v;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_a>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index d7b78cd..dd67e96 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -8,6 +8,7 @@
 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
+#include "stm32mp15xx-dhsom-u-boot.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
deleted file mode 100644
index dd8fcec..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-avenger96.dtsi"
-
-/ {
-	model = "Arrow Electronics STM32MP15xx Avenger96 board";
-	compatible = "arrow,stm32mp15xx-avenger96",
-		     "dh,stm32mp15xx-dhcor-som",
-		     "st,stm32mp15x";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
deleted file mode 100644
index 61e17f4..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
+++ /dev/null
@@ -1,437 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */
-#include "stm32mp15xx-dhcor-io1v8.dtsi"
-
-/ {
-	aliases {
-		ethernet0 = &ethernet0;
-		mmc0 = &sdmmc1;
-		serial0 = &uart4;
-		serial1 = &uart7;
-		serial2 = &usart2;
-		spi0 = &qspi;
-	};
-
-	/* XTal Q1 */
-	cec_clock: clk-cec-fixed {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	hdmi-out {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi_con: endpoint {
-				remote-endpoint = <&adv7513_out>;
-			};
-		};
-	};
-
-	led {
-		compatible = "gpio-leds";
-		led1 {
-			label = "green:user0";
-			gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-
-		led2 {
-			label = "green:user1";
-			gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc0";
-			default-state = "off";
-		};
-
-		led3 {
-			label = "green:user2";
-			gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc1";
-			default-state = "off";
-		};
-
-		led4 {
-			label = "green:user3";
-			gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "none";
-			default-state = "off";
-			panic-indicator;
-		};
-	};
-
-	sd_switch: regulator-sd_switch {
-		compatible = "regulator-gpio";
-		regulator-name = "sd_switch";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <2900000>;
-		regulator-type = "voltage";
-		regulator-always-on;
-
-		gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
-		gpios-states = <0>;
-		states = <1800000 0x1>,
-			 <2900000 0x0>;
-	};
-
-	sound {
-		compatible = "audio-graph-card";
-		label = "STM32MP1-AV96-HDMI";
-		dais = <&sai2a_port>;
-		status = "okay";
-	};
-
-	wlan_pwr: regulator-wlan {
-		compatible = "regulator-fixed";
-
-		regulator-name = "wl-reg";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-};
-
-&adc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&adc12_ain_pins_b>;
-	vdd-supply = <&vdd>;
-	vdda-supply = <&vdda>;
-	vref-supply = <&vdda>;
-	status = "okay";
-
-	adc1: adc@0 {
-		st,adc-channels = <0 1 6>;
-		st,min-sample-time-nsecs = <5000>;
-		status = "okay";
-	};
-
-	adc2: adc@100 {
-		st,adc-channels = <0 1 2>;
-		st,min-sample-time-nsecs = <5000>;
-		status = "okay";
-	};
-};
-
-&ethernet0 {
-	status = "okay";
-	pinctrl-0 = <&ethernet0_rgmii_pins_c>;
-	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rgmii";
-	max-speed = <1000>;
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <1000>;
-
-		phy0: ethernet-phy@7 {
-			reg = <7>;
-
-			rxc-skew-ps = <1500>;
-			rxdv-skew-ps = <540>;
-			rxd0-skew-ps = <420>;
-			rxd1-skew-ps = <420>;
-			rxd2-skew-ps = <420>;
-			rxd3-skew-ps = <420>;
-
-			txc-skew-ps = <1440>;
-			txen-skew-ps = <540>;
-			txd0-skew-ps = <420>;
-			txd1-skew-ps = <420>;
-			txd2-skew-ps = <420>;
-			txd3-skew-ps = <420>;
-		};
-	};
-};
-
-&gpioa {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "AV96-K",
-			  "AV96-I", "", "AV96-A", "";
-};
-
-&gpiob {
-	gpio-line-names = "", "", "", "",
-			  "", "AV96-J", "", "",
-			  "", "", "", "AV96-B",
-			  "", "AV96-L", "", "";
-};
-
-&gpioc {
-	gpio-line-names = "", "", "", "AV96-C",
-			  "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiod {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "AV96-D", "", "", "",
-			  "", "", "AV96-E", "AV96-F";
-};
-
-&gpiof {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "",
-			  "AV96-G", "AV96-H", "", "";
-};
-
-&i2c1 {	/* X6 I2C1 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_b>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&i2c2 {	/* X6 I2C2 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_c>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&i2c4 {
-	hdmi-transmitter@3d {
-		compatible = "adi,adv7513";
-		reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
-		reg-names = "main", "edid", "cec", "packet";
-		clocks = <&cec_clock>;
-		clock-names = "cec";
-
-		avdd-supply = <&v3v3>;
-		dvdd-supply = <&v3v3>;
-		pvdd-supply = <&v3v3>;
-		dvdd-3v-supply = <&v3v3>;
-		bgvdd-supply = <&v3v3>;
-
-		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-parent = <&gpiog>;
-
-		status = "okay";
-
-		adi,input-depth = <8>;
-		adi,input-colorspace = "rgb";
-		adi,input-clock = "1x";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				adv7513_in: endpoint {
-					remote-endpoint = <&ltdc_ep0_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				adv7513_out: endpoint {
-					remote-endpoint = <&hdmi_con>;
-				};
-			};
-
-			port@2 {
-				reg = <2>;
-				adv7513_i2s0: endpoint {
-					remote-endpoint = <&sai2a_endpoint>;
-				};
-			};
-		};
-	};
-};
-
-&ltdc {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&ltdc_pins_d>;
-	pinctrl-1 = <&ltdc_sleep_pins_d>;
-	status = "okay";
-
-	port {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ltdc_ep0_out: endpoint@0 {
-			reg = <0>;
-			remote-endpoint = <&adv7513_in>;
-		};
-	};
-};
-
-&sai2 {
-	clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&sai2a_pins_c>;
-	pinctrl-1 = <&sai2a_sleep_pins_c>;
-	clock-names = "pclk", "x8k", "x11k";
-	status = "okay";
-
-	sai2a: audio-controller@4400b004 {
-		#clock-cells = <0>;
-		dma-names = "tx";
-		clocks = <&rcc SAI2_K>;
-		clock-names = "sai_ck";
-		status = "okay";
-
-		sai2a_port: port {
-			sai2a_endpoint: endpoint {
-				remote-endpoint = <&adv7513_i2s0>;
-				format = "i2s";
-				mclk-fs = <256>;
-			};
-		};
-	};
-};
-
-&sdmmc1 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
-	cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-	disable-wp;
-	st,sig-dir;
-	st,neg-edge;
-	st,use-ckin;
-	bus-width = <4>;
-	vmmc-supply = <&vdd_sd>;
-	vqmmc-supply = <&sd_switch>;
-	status = "okay";
-};
-
-&sdmmc2 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
-	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
-	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	no-sd;
-	no-sdio;
-	non-removable;
-	st,neg-edge;
-	vmmc-supply = <&v3v3>;
-	vqmmc-supply = <&vdd_io>;
-	status = "okay";
-};
-
-&sdmmc3 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc3_b4_pins_b>;
-	pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
-	pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
-	broken-cd;
-	non-removable;
-	st,neg-edge;
-	bus-width = <4>;
-	vmmc-supply = <&wlan_pwr>;
-	status = "okay";
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	brcmf: bcrmf@1 {
-		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
-	};
-};
-
-&spi2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi2_pins_a>;
-	cs-gpios = <&gpioi 0 0>;
-	status = "disabled";
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&uart4 {
-	/* On Low speed expansion header */
-	label = "LS-UART1";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_b>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&uart7 {
-	/* On Low speed expansion header */
-	label = "LS-UART0";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
-	uart-has-rtscts;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-/* Bluetooth */
-&usart2 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&usart2_pins_a>;
-	pinctrl-1 = <&usart2_sleep_pins_a>;
-	st,hw-flow-ctrl;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-
-	bluetooth {
-		compatible = "brcm,bcm43438-bt";
-		max-speed = <3000000>;
-		shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
-	status = "okay";
-};
-
-&usbotg_hs {
-	pinctrl-0 = <&usbotg_hs_pins_a>;
-	pinctrl-names = "default";
-	phy-names = "usb2-phy";
-	phys = <&usbphyc_port1 0>;
-	status = "okay";
-	vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc {
-	status = "okay";
-};
-
-&usbphyc_port0 {
-	phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
-	phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
deleted file mode 100644
index c1f99c1..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- */
-
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-drc-compact.dtsi"
-
-/ {
-	model = "DH electronics STM32MP15xx DHCOR DRC Compact";
-	compatible = "dh,stm32mp15xx-dhcor-drc-compact",
-		     "dh,stm32mp15xx-dhcor-som",
-		     "st,stm32mp1xx";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi
deleted file mode 100644
index bedccf0..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi
+++ /dev/null
@@ -1,326 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- */
-
-/ {
-	aliases {
-		ethernet0 = &ethernet0;
-		ethernet1 = &ksz8851;
-		mmc0 = &sdmmc1;
-		rtc0 = &hwrtc;
-		rtc1 = &rtc;
-		serial0 = &uart4;
-		serial1 = &uart8;
-		serial2 = &usart3;
-		serial3 = &uart5;
-		spi0 = &qspi;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	led {
-		compatible = "gpio-leds";
-		led1 {
-			label = "yellow:user0";
-			gpios = <&gpioz 6 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-
-		led2 {
-			label = "red:user1";
-			gpios = <&gpioz 3 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-	};
-
-	ethernet_vio: vioregulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vio";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpioh 2 GPIO_ACTIVE_LOW>;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vdd>;
-	};
-};
-
-&adc {	/* X11 ADC inputs */
-	pinctrl-names = "default";
-	pinctrl-0 = <&adc12_ain_pins_b>;
-	vdd-supply = <&vdd>;
-	vdda-supply = <&vdda>;
-	vref-supply = <&vdda>;
-	status = "okay";
-
-	adc1: adc@0 {
-		st,adc-channels = <0 1 6>;
-		st,min-sample-time-nsecs = <5000>;
-		status = "okay";
-	};
-
-	adc2: adc@100 {
-		st,adc-channels = <0 1 2>;
-		st,min-sample-time-nsecs = <5000>;
-		status = "okay";
-	};
-};
-
-&ethernet0 {
-	status = "okay";
-	pinctrl-0 = <&ethernet0_rgmii_pins_c>;
-	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rgmii";
-	max-speed = <1000>;
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <1000>;
-		reset-post-delay-us = <1000>;
-
-		phy0: ethernet-phy@7 {
-			reg = <7>;
-
-			rxc-skew-ps = <1500>;
-			rxdv-skew-ps = <540>;
-			rxd0-skew-ps = <420>;
-			rxd1-skew-ps = <420>;
-			rxd2-skew-ps = <420>;
-			rxd3-skew-ps = <420>;
-
-			txc-skew-ps = <1440>;
-			txen-skew-ps = <540>;
-			txd0-skew-ps = <420>;
-			txd1-skew-ps = <420>;
-			txd2-skew-ps = <420>;
-			txd3-skew-ps = <420>;
-		};
-	};
-};
-
-&fmc {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&fmc_pins_b>;
-	pinctrl-1 = <&fmc_sleep_pins_b>;
-	status = "okay";
-
-	ksz8851: ethernet@1,0 {
-		compatible = "micrel,ks8851-mll";
-		reg = <1 0x0 0x2>, <1 0x2 0x20000>;
-		interrupt-parent = <&gpioc>;
-		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-		bank-width = <2>;
-
-		/* Timing values are in nS */
-		st,fmc2-ebi-cs-mux-enable;
-		st,fmc2-ebi-cs-transaction-type = <4>;
-		st,fmc2-ebi-cs-buswidth = <16>;
-		st,fmc2-ebi-cs-address-setup-ns = <5>;
-		st,fmc2-ebi-cs-address-hold-ns = <5>;
-		st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
-		st,fmc2-ebi-cs-data-setup-ns = <45>;
-		st,fmc2-ebi-cs-data-hold-ns = <1>;
-		st,fmc2-ebi-cs-write-address-setup-ns = <5>;
-		st,fmc2-ebi-cs-write-address-hold-ns = <5>;
-		st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
-		st,fmc2-ebi-cs-write-data-setup-ns = <45>;
-		st,fmc2-ebi-cs-write-data-hold-ns = <1>;
-	};
-};
-
-&gpioa {
-	gpio-line-names = "", "", "", "",
-			  "DRCC-VAR2", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpioe {
-	gpio-line-names = "", "", "", "",
-			  "", "DRCC-GPIO0", "", "",
-			  "", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiog {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "",
-			  "DRCC-GPIO5", "", "", "";
-};
-
-&gpioh {
-	gpio-line-names = "", "", "", "DRCC-HW2",
-			  "DRCC-GPIO4", "", "", "",
-			  "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1",
-			  "DRCC-VAR0", "", "", "DRCC-GPIO6";
-};
-
-&gpioi {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "DRCC-GPIO2",
-			  "", "DRCC-GPIO1", "", "",
-			  "", "", "", "";
-};
-
-&i2c1 {	/* X11 I2C1 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins_b>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&i2c4 {
-	hwrtc: rtc@32 {
-		compatible = "microcrystal,rv8803";
-		reg = <0x32>;
-	};
-
-	eeprom@50 {
-		compatible = "atmel,24c04";
-		reg = <0x50>;
-		pagesize = <16>;
-	};
-};
-
-&sdmmc1 {	/* MicroSD */
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc1_b4_pins_a>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
-	cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-	disable-wp;
-	st,neg-edge;
-	bus-width = <4>;
-	vmmc-supply = <&vdd>;
-	vqmmc-supply = <&vdd>;
-	status = "okay";
-};
-
-&sdmmc2 {	/* eMMC */
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
-	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
-	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
-	bus-width = <8>;
-	no-sd;
-	no-sdio;
-	non-removable;
-	st,neg-edge;
-	vmmc-supply = <&v3v3>;
-	vqmmc-supply = <&vdd>;
-	status = "okay";
-};
-
-&sdmmc3 {	/* SDIO Wi-Fi */
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc3_b4_pins_a>;
-	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
-	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
-	broken-cd;
-	bus-width = <4>;
-	mmc-ddr-3_3v;
-	st,neg-edge;
-	vmmc-supply = <&v3v3>;
-	vqmmc-supply = <&v3v3>;
-	status = "okay";
-};
-
-&spi2 {	/* X11 SPI */
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi2_pins_b>;
-	cs-gpios = <&gpioi 0 0>;
-	status = "disabled";
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&uart4 {
-	label = "UART0";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_d>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&uart5 {	/* X11 UART */
-	label = "X11-UART5";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart5_pins_a>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&uart8 {
-	label = "RS485-1";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
-	uart-has-rtscts;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&usart3 {	/* RS485 or RS232 */
-	label = "RS485-2";
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&usart3_pins_e>;
-	pinctrl-1 = <&usart3_sleep_pins_e>;
-	uart-has-rtscts;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&usbh_ehci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbh_ohci {
-	phys = <&usbphyc_port0>;
-	status = "okay";
-};
-
-&usbotg_hs {
-	dr_mode = "otg";
-	pinctrl-0 = <&usbotg_hs_pins_a>;
-	pinctrl-names = "default";
-	phy-names = "usb2-phy";
-	phys = <&usbphyc_port1 0>;
-	vbus-supply = <&vbus_otg>;
-	status = "okay";
-};
-
-&usbphyc {
-	status = "okay";
-};
-
-&usbphyc_port0 {
-	phy-supply = <&vdd_usb>;
-	vdda1v1-supply = <&reg11>;
-	vdda1v8-supply = <&reg18>;
-	connector {
-		compatible = "usb-a-connector";
-		vbus-supply = <&vbus_sw>;
-	};
-};
-
-&usbphyc_port1 {
-	phy-supply = <&vdd_usb>;
-	vdda1v1-supply = <&reg11>;
-	vdda1v8-supply = <&reg18>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
deleted file mode 100644
index e209178..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-/ {
-	/* Enpirion EP3A8LQI U2 on the DHCOR */
-	vdd_io: regulator-buck-io {
-		compatible = "regulator-fixed";
-		regulator-name = "buck-io";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vdd>;
-	};
-};
-
-&vdd {
-	regulator-min-microvolt = <1800000>;
-	regulator-max-microvolt = <2900000>;
-};
-
-&pwr_regulators {
-	vdd-supply = <&vdd_io>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi
deleted file mode 100644
index f36eec1..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxac-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
-	aliases {
-		spi0 = &qspi;
-	};
-
-	memory@c0000000 {
-		device_type = "memory";
-		reg = <0xc0000000 0x40000000>;
-	};
-};
-
-&crc1 {
-	status = "okay";
-};
-
-&dts {
-	status = "okay";
-};
-
-&i2c4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c4_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/delete-property/dmas;
-	/delete-property/dma-names;
-
-	pmic: stpmic@33 {
-		compatible = "st,stpmic1";
-		reg = <0x33>;
-		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		status = "okay";
-
-		regulators {
-			compatible = "st,stpmic1-regulators";
-
-			ldo1-supply = <&v3v3>;
-			ldo2-supply = <&v3v3>;
-			ldo3-supply = <&vdd_ddr>;
-			ldo5-supply = <&v3v3>;
-			ldo6-supply = <&v3v3>;
-			pwr_sw1-supply = <&bst_out>;
-			pwr_sw2-supply = <&bst_out>;
-
-			vddcore: buck1 {
-				regulator-name = "vddcore";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd_ddr: buck2 {
-				regulator-name = "vdd_ddr";
-				regulator-min-microvolt = <1350000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd: buck3 {
-				regulator-name = "vdd";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			v3v3: buck4 {
-				regulator-name = "v3v3";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				regulator-over-current-protection;
-				regulator-initial-mode = <0>;
-			};
-
-			vdda: ldo1 {
-				regulator-name = "vdda";
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <2900000>;
-				interrupts = <IT_CURLIM_LDO1 0>;
-			};
-
-			v2v8: ldo2 {
-				regulator-name = "v2v8";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				interrupts = <IT_CURLIM_LDO2 0>;
-			};
-
-			vtt_ddr: ldo3 {
-				regulator-name = "vtt_ddr";
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <750000>;
-				regulator-always-on;
-				regulator-over-current-protection;
-			};
-
-			vdd_usb: ldo4 {
-				regulator-name = "vdd_usb";
-				interrupts = <IT_CURLIM_LDO4 0>;
-			};
-
-			vdd_sd: ldo5 {
-				regulator-name = "vdd_sd";
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <2900000>;
-				interrupts = <IT_CURLIM_LDO5 0>;
-				regulator-boot-on;
-			};
-
-			v1v8: ldo6 {
-				regulator-name = "v1v8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO6 0>;
-				regulator-enable-ramp-delay = <300000>;
-			};
-
-			vref_ddr: vref_ddr {
-				regulator-name = "vref_ddr";
-				regulator-always-on;
-			};
-
-			bst_out: boost {
-				regulator-name = "bst_out";
-				interrupts = <IT_OCP_BOOST 0>;
-			};
-
-			vbus_otg: pwr_sw1 {
-				regulator-name = "vbus_otg";
-				interrupts = <IT_OCP_OTG 0>;
-				regulator-active-discharge = <1>;
-			};
-
-			vbus_sw: pwr_sw2 {
-				regulator-name = "vbus_sw";
-				interrupts = <IT_OCP_SWOUT 0>;
-				regulator-active-discharge = <1>;
-			};
-		};
-
-		onkey {
-			compatible = "st,stpmic1-onkey";
-			interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
-			interrupt-names = "onkey-falling", "onkey-rising";
-			status = "okay";
-		};
-
-		watchdog {
-			compatible = "st,stpmic1-wdt";
-			status = "disabled";
-		};
-	};
-
-	eeprom@53 {
-		compatible = "atmel,24c02";
-		reg = <0x53>;
-		pagesize = <16>;
-	};
-};
-
-&iwdg2 {
-	timeout-sec = <32>;
-	status = "okay";
-};
-
-&pwr_regulators {
-	vdd-supply = <&vdd>;
-	vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&qspi {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&qspi_clk_pins_a
-		     &qspi_bk1_pins_a
-		     &qspi_cs1_pins_a>;
-	pinctrl-1 = <&qspi_clk_sleep_pins_a
-		     &qspi_bk1_sleep_pins_a
-		     &qspi_cs1_sleep_pins_a>;
-	reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash0: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <50000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&rng1 {
-	status = "okay";
-};
-
-&rtc {
-	status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
deleted file mode 100644
index 5fdd762..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-
-/ {
-	model = "DH electronics STM32MP15xx DHCOR Testbench";
-	compatible = "dh,stm32mp15xx-dhcor-testbench",
-		     "dh,stm32mp15xx-dhcor-som",
-		     "st,stm32mp1xx";
-
-	aliases {
-		ethernet0 = &ethernet0;
-		mmc0 = &sdmmc1;
-		mmc1 = &sdmmc2;
-		serial0 = &uart4;
-		serial1 = &uart7;
-		spi0 = &qspi;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	sd_switch: regulator-sd_switch {
-		compatible = "regulator-gpio";
-		regulator-name = "sd_switch";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <2900000>;
-		regulator-type = "voltage";
-		regulator-always-on;
-
-		gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
-		gpios-states = <0>;
-		states = <1800000 0x1>,
-			 <2900000 0x0>;
-	};
-};
-
-&adc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&adc12_ain_pins_b>;
-	vdd-supply = <&vdd>;
-	vdda-supply = <&vdda>;
-	vref-supply = <&vdda>;
-	status = "okay";
-
-	adc1: adc@0 {
-		st,adc-channels = <0 1 6>;
-		st,min-sample-time-nsecs = <5000>;
-		status = "okay";
-	};
-
-	adc2: adc@100 {
-		st,adc-channels = <0 1 2>;
-		st,min-sample-time-nsecs = <5000>;
-		status = "okay";
-	};
-};
-
-&ethernet0 {
-	status = "okay";
-	pinctrl-0 = <&ethernet0_rgmii_pins_c>;
-	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rgmii";
-	max-speed = <1000>;
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <1000>;
-
-		phy0: ethernet-phy@7 {
-			reg = <7>;
-
-			rxc-skew-ps = <1500>;
-			rxdv-skew-ps = <540>;
-			rxd0-skew-ps = <420>;
-			rxd1-skew-ps = <420>;
-			rxd2-skew-ps = <420>;
-			rxd3-skew-ps = <420>;
-
-			txc-skew-ps = <1440>;
-			txen-skew-ps = <540>;
-			txd0-skew-ps = <420>;
-			txd1-skew-ps = <420>;
-			txd2-skew-ps = <420>;
-			txd3-skew-ps = <420>;
-		};
-	};
-};
-
-&sdmmc1 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
-	cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-	disable-wp;
-	st,sig-dir;
-	st,neg-edge;
-	st,use-ckin;
-	bus-width = <4>;
-	vmmc-supply = <&vdd_sd>;
-	vqmmc-supply = <&sd_switch>;
-	status = "okay";
-};
-
-&sdmmc2 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
-	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
-	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	no-sd;
-	no-sdio;
-	non-removable;
-	st,neg-edge;
-	vmmc-supply = <&v3v3>;
-	vqmmc-supply = <&v3v3>;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_b>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&uart7 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart7_pins_a>;
-	uart-has-rtscts;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-&usbh_ehci {
-	phys = <&usbphyc_port0>;
-	phy-names = "usb";
-	status = "okay";
-};
-
-&usbotg_hs {
-	pinctrl-0 = <&usbotg_hs_pins_a>;
-	pinctrl-names = "default";
-	phy-names = "usb2-phy";
-	phys = <&usbphyc_port1 0>;
-	status = "okay";
-	vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc {
-	status = "okay";
-};
-
-&usbphyc_port0 {
-	phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
-	phy-supply = <&vdd_usb>;
-};
-
-&vdd {
-	/delete-property/ regulator-always-on;
-	regulator-min-microvolt = <1200000>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index ba84db6..0843934 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -12,6 +12,7 @@
 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
+#include "stm32mp15xx-dhsom-u-boot.dtsi"
 
 / {
 	bootph-all;
diff --git a/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi
new file mode 100644
index 0000000..386c605
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+&binman {
+	 u-boot {
+		filename = "u-boot.itb";
+
+		fit {
+			description = "U-Boot mainline";
+			fit,fdt-list = "of-list";
+			#address-cells = <1>;
+
+			images {
+				uboot {
+					arch = "arm";
+					compression = "none";
+					description = "U-Boot (32-bit)";
+					entry = <CONFIG_TEXT_BASE>;
+					load = <CONFIG_TEXT_BASE>;
+					type = "standalone";
+
+					uboot-blob {
+						filename = "u-boot-nodtb.bin";
+						type = "blob-ext";
+					};
+				};
+
+				@fdt-SEQ {
+					compression = "none";
+					description = "NAME";
+					type = "flat_dt";
+
+					uboot-fdt-blob {
+						filename = "u-boot.dtb";
+						type = "blob-ext";
+					};
+				};
+			};
+
+			configurations {
+				default = "@config-DEFAULT-SEQ";
+
+				@config-SEQ {
+					description = "NAME";
+					fdt = "fdt-SEQ";
+					firmware = "uboot";
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index c1d9273..09b8f05 100644
--- a/arch/arm/mach-at91/include/mach/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
@@ -11,6 +11,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/global_data.h>
+#include <asm/io.h>
 
 #define GCK_CSS_SLOW_CLK	0
 #define GCK_CSS_MAIN_CLK	1
diff --git a/arch/arm/mach-k3/am62x/am625_fdt.c b/arch/arm/mach-k3/am62x/am625_fdt.c
index 8fe200a..ab9b573 100644
--- a/arch/arm/mach-k3/am62x/am625_fdt.c
+++ b/arch/arm/mach-k3/am62x/am625_fdt.c
@@ -5,6 +5,7 @@
 
 #include <asm/hardware.h>
 #include <fdt_support.h>
+#include <fdtdec.h>
 
 #include "../common_fdt.h"
 
@@ -75,12 +76,47 @@
 	}
 }
 
+static void fdt_fixup_thermal_cooling_device_cpus_am625(void *blob, int core_nr)
+{
+	static const char * const thermal_path[] = {
+		"/thermal-zones/main0-thermal/cooling-maps/map0",
+		"/thermal-zones/main1-thermal/cooling-maps/map0"
+	};
+
+	int node, cnt, i, ret;
+	u32 cooling_dev[12];
+
+	for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+		int new_count = core_nr * 3;  /* Each CPU has 3 entries */
+		int j;
+
+		node = fdt_path_offset(blob, thermal_path[i]);
+		if (node < 0)
+			continue; /* Not found, skip it */
+
+		cnt = fdtdec_get_int_array_count(blob, node, "cooling-device",
+						 cooling_dev, ARRAY_SIZE(cooling_dev));
+		if (cnt < 0)
+			continue;
+
+		for (j = 0; j < new_count; j++)
+			cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+		ret = fdt_setprop(blob, node, "cooling-device", cooling_dev,
+				  new_count * sizeof(u32));
+		if (ret < 0)
+			printf("Error %s, cooling-device setprop failed %d\n",
+			       thermal_path[i], ret);
+	}
+}
+
 int ft_system_setup(void *blob, struct bd_info *bd)
 {
 	fdt_fixup_cores_nodes_am625(blob, k3_get_core_nr());
 	fdt_fixup_gpu_nodes_am625(blob, k3_has_gpu());
 	fdt_fixup_pru_node_am625(blob, k3_has_pru());
 	fdt_fixup_thermal_zone_nodes_am625(blob, k3_get_max_temp());
+	fdt_fixup_thermal_cooling_device_cpus_am625(blob, k3_get_core_nr());
 	fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
 	fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
 
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index f2086cb..fa8cd93 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -28,6 +28,8 @@
 #include <env.h>
 #include <elf.h>
 #include <soc.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
 
 #include <asm/arch/k3-qos.h>
 
@@ -246,12 +248,32 @@
 #endif
 }
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+static __maybe_unused void k3_dma_remove(void)
+{
+	struct udevice *dev;
+	int rc;
+
+	rc = uclass_find_device(UCLASS_DMA, 0, &dev);
+	if (!rc && dev) {
+		rc = device_remove(dev, DM_REMOVE_NORMAL);
+		if (rc)
+			pr_warn("Cannot remove dma device '%s' (err=%d)\n",
+				dev->name, rc);
+	} else
+		pr_warn("DMA Device not found (err=%d)\n", rc);
+}
+
 void spl_board_prepare_for_boot(void)
 {
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	dcache_disable();
+#endif
+#if IS_ENABLED(CONFIG_SPL_DMA) && IS_ENABLED(CONFIG_SPL_DM_DEVICE_REMOVE)
+	k3_dma_remove();
+#endif
 }
 
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 void spl_board_prepare_for_linux(void)
 {
 	dcache_disable();
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index 793bcac..97d9692 100644
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -67,6 +67,16 @@
 	"gluelogic_hfosc0_clkout",
 };
 
+static const char * const wkup_usart_clksel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_usart_mcupll_bypass_out0_parents[] = {
+	"wkup_usart_clksel_out0",
+	"gluelogic_hfosc0_clkout",
+};
+
 static const char * const main_pll_hfosc_sel_out0_parents[] = {
 	"gluelogic_hfosc0_clkout",
 	"board_0_hfosc1_clk_out",
@@ -206,7 +216,7 @@
 	CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
 	CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
 	CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0, 96000000),
 	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
 	CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
 	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
@@ -216,6 +226,8 @@
 	CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
 	CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
 	CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
+	CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
+	CLK_MUX("wkup_usart_mcupll_bypass_out0", wkup_usart_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
 	CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
 	CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
 	CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
@@ -409,6 +421,10 @@
 	DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"),
 	DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(397, 0, "wkup_usart_mcupll_bypass_out0"),
+	DEV_CLK(397, 1, "wkup_usart_clksel_out0"),
+	DEV_CLK(397, 2, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(397, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 	DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"),
diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c
index d66ba8b..b32b4ba 100644
--- a/arch/arm/mach-k3/r5/j784s4/dev-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c
@@ -62,6 +62,7 @@
 	PSC_DEV(149, &soc_lpsc_list[0]),
 	PSC_DEV(167, &soc_lpsc_list[1]),
 	PSC_DEV(279, &soc_lpsc_list[1]),
+	PSC_DEV(397, &soc_lpsc_list[1]),
 	PSC_DEV(161, &soc_lpsc_list[2]),
 	PSC_DEV(162, &soc_lpsc_list[3]),
 	PSC_DEV(160, &soc_lpsc_list[4]),
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index d5934a9..25663a9 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -39,6 +39,7 @@
 
 config STM32MP13X
 	bool "Support STMicroelectronics STM32MP13x Soc"
+	select ARCH_EARLY_INIT_R
 	select ARM_SMCCC
 	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
@@ -57,6 +58,7 @@
 
 config STM32MP15X
 	bool "Support STMicroelectronics STM32MP15x Soc"
+	select ARCH_EARLY_INIT_R
 	select ARCH_SUPPORT_PSCI
 	select BINMAN
 	select CPU_V7A
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 3698fc4..b061057 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -25,8 +25,11 @@
 	ofnode node;
 
 	node = ofnode_path("/reserved-memory/optee");
-	if (!ofnode_valid(node))
-		return -ENOENT;
+	if (!ofnode_valid(node)) {
+		node = ofnode_path("/reserved-memory/optee_core");
+		if (!ofnode_valid(node))
+			return -ENOENT;
+	}
 
 	fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
 	*start = fdt_start;
@@ -62,7 +65,6 @@
 
 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
-	int ret;
 	phys_size_t size;
 	phys_addr_t reg;
 	u32 optee_start, optee_size;
@@ -75,10 +77,17 @@
 	 * if the effective available memory is bigger
 	 */
 	gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
+
+	/* add 8M for U-Boot reserved memory: display, fdt, gd,... */
 	size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
 
-	ret = optee_get_reserved_memory(&optee_start, &optee_size);
-	reg = (!ret ? optee_start : gd->ram_top) - size;
+	reg = gd->ram_top - size;
+
+	/* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */
+	if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) {
+		if (!optee_get_reserved_memory(&optee_start, &optee_size))
+			reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
+	}
 
 	/* before relocation, mark the U-Boot memory as cacheable by default */
 	if (!(gd->flags & GD_FLG_RELOC))
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 26c073f..62cc989 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -143,6 +143,11 @@
 {
 	/* I-cache is already enabled in start.S: icache_enable() not needed */
 
+	/* keep D-cache configuration done before relocation, wait arch_early_init_r*/
+}
+
+int arch_early_init_r(void)
+{
 	/* deactivate the data cache, early enabled in arch_cpu_init() */
 	dcache_disable();
 	/*
@@ -150,6 +155,8 @@
 	 * warning: the TLB location udpated in board_f.c::reserve_mmu
 	 */
 	dcache_enable();
+
+	return 0;
 }
 
 static void setup_boot_mode(void)
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
index 865588f..fdd5790 100644
--- a/board/dhelectronics/dh_stm32mp1/MAINTAINERS
+++ b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
@@ -2,8 +2,5 @@
 M:	Marek Vasut <marex@denx.de>
 L:	u-boot@dh-electronics.com
 S:	Maintained
-F:	arch/arm/dts/stm32mp15xx-dhcom*
-F:	board/dhelectronics/dh_stm32mp1/
-F:	configs/stm32mp15_dhcom_basic_defconfig
-F:	configs/stm32mp15_dhcor_basic_defconfig
-F:	include/configs/stm32mp15_dh_dhsom.h
+N:	stm32mp.*dh[cs]o
+N:	dh_stm32
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index a975fd2..d30171f 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -276,15 +276,26 @@
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
+	char *cdevice, *ndevice;
 	const char *compat;
-	char test[128];
 
 	compat = ofnode_get_property(ofnode_root(), "compatible", NULL);
+	if (!compat)
+		return -EINVAL;
 
-	snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
-		compat, somcode, brdcode);
+	cdevice = strchr(compat, ',');
+	if (!cdevice)
+		return -ENODEV;
+
+	cdevice++;	/* Move past the comma right after vendor prefix. */
+
+	ndevice = strchr(name, '/');
+	if (!ndevice)
+		return -ENODEV;
+
+	ndevice++;	/* Move past the last slash in DT path */
 
-	if (!strcmp(name, test))
+	if (!strcmp(cdevice, ndevice))
 		return 0;
 
 	return -EINVAL;
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
deleted file mode 100644
index 8eed9d0..0000000
--- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
+++ /dev/null
@@ -1,91 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "U-Boot mainline";
-	#address-cells = <1>;
-
-	images {
-		uboot {
-			description = "U-Boot (32-bit)";
-			data = /incbin/("u-boot-nodtb.bin");
-			type = "standalone";
-			os = "U-Boot";
-			arch = "arm";
-			compression = "none";
-			load = <0xc0100000>;
-			entry = <0xc0100000>;
-		};
-
-		fdt-1 {
-			description = ".dtb";
-			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-		};
-
-		fdt-2 {
-			description = ".dtb";
-			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-drc02.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-		};
-
-		fdt-3 {
-			description = ".dtb";
-			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-		};
-	};
-
-	configurations {
-		default = "config-1";
-
-		config-1 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcom-pdk2_somrev0_boardrev0";
-			firmware = "uboot";
-			fdt = "fdt-1";
-		};
-
-		config-2 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcom-pdk2_somrev1_boardrev0";
-			firmware = "uboot";
-			fdt = "fdt-1";
-		};
-
-		config-3 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcom-drc02_somrev0_boardrev0";
-			firmware = "uboot";
-			fdt = "fdt-2";
-		};
-
-		config-4 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcom-drc02_somrev1_boardrev0";
-			firmware = "uboot";
-			fdt = "fdt-2";
-		};
-
-		config-5 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcom-picoitx_somrev0_boardrev0";
-			loadables = "uboot";
-			fdt = "fdt-3";
-		};
-
-		config-6 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcom-picoitx_somrev1_boardrev0";
-			loadables = "uboot";
-			fdt = "fdt-3";
-		};
-
-		/* Add 587-100..587-400 with fdt-2..fdt-4 here */
-	};
-};
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
deleted file mode 100644
index f9c1075..0000000
--- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
+++ /dev/null
@@ -1,70 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "U-Boot mainline";
-	#address-cells = <1>;
-
-	images {
-		uboot {
-			description = "U-Boot (32-bit)";
-			data = /incbin/("u-boot-nodtb.bin");
-			type = "standalone";
-			os = "U-Boot";
-			arch = "arm";
-			compression = "none";
-			load = <0xc0100000>;
-			entry = <0xc0100000>;
-		};
-
-		fdt-1 {
-			description = ".dtb";
-			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-testbench.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-		};
-
-		fdt-2 {
-			description = ".dtb";
-			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-		};
-
-		fdt-3 {
-			description = ".dtb";
-			data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtb");
-			type = "flat_dt";
-			arch = "arm";
-			compression = "none";
-		};
-	};
-
-	configurations {
-		default = "config-1";
-
-		config-1 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcor-testbench_somrev0_boardrev1";
-			firmware = "uboot";
-			fdt = "fdt-1";
-		};
-
-		config-2 {
-			/* DT+SoM+board model */
-			description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1";
-			firmware = "uboot";
-			fdt = "fdt-2";
-		};
-
-		config-3 {
-			/* DT+SoM+board model */
-			description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0";
-			firmware = "uboot";
-			fdt = "fdt-3";
-		};
-
-		/* Add 586-200..586-400 with fdt-2..fdt-4 here */
-	};
-};
diff --git a/board/radxa/rock5b-rk3588/Makefile b/board/radxa/rock5b-rk3588/Makefile
new file mode 100644
index 0000000..95d8135
--- /dev/null
+++ b/board/radxa/rock5b-rk3588/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+# Copyright (c) 2022 Collabora Ltd.
+#
+
+obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
new file mode 100644
index 0000000..fc2f69d
--- /dev/null
+++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023-2024 Collabora Ltd.
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	if (IS_ENABLED(CONFIG_TYPEC_FUSB302))
+		fdt_status_okay_by_compatible(blob, "fcs,fusb302");
+	return 0;
+}
+#endif
diff --git a/boot/Kconfig b/boot/Kconfig
index 1d50a83..1ce1da6 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -282,14 +282,6 @@
 	  injected into the FIT creation (i.e. the blobs would have been pre-
 	  processed before being added to the FIT image).
 
-config SPL_FIT_SOURCE
-	string ".its source file for U-Boot FIT image"
-	depends on SPL_FIT
-	help
-	  Specifies a (platform specific) FIT source file to generate the
-	  U-Boot FIT image. This could specify further image to load and/or
-	  execute.
-
 config USE_SPL_FIT_GENERATOR
 	bool "Use a script to generate the .its script"
 	depends on SPL_FIT
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 8c677b1..bff22b94 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -221,6 +221,13 @@
 	help
 	  Register dump
 
+config CMD_TCPM
+	bool "tcpm"
+	depends on TYPEC_TCPM
+	help
+	  Show voltage and current negotiated via USB PD as well as the
+	  current state of the Type C Port Manager (TCPM) state machine.
+
 config CMD_TLV_EEPROM
 	bool "tlv_eeprom"
 	depends on I2C_EEPROM
diff --git a/cmd/Makefile b/cmd/Makefile
index f309140..3c5bd56 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -179,6 +179,7 @@
 obj-$(CONFIG_CMD_SMC) += smccc.o
 obj-$(CONFIG_CMD_SYSBOOT) += sysboot.o
 obj-$(CONFIG_CMD_STACKPROTECTOR_TEST) += stackprot_test.o
+obj-$(CONFIG_CMD_TCPM) += tcpm.o
 obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
 obj-$(CONFIG_CMD_TERMINAL) += terminal.o
 obj-$(CONFIG_CMD_TIME) += time.o
diff --git a/cmd/irq.c b/cmd/irq.c
index 655aba5..da223b4 100644
--- a/cmd/irq.c
+++ b/cmd/irq.c
@@ -29,9 +29,6 @@
 	"[on, off]"
 );
 
-/* Implemented in $(CPU)/interrupts.c */
-int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
-
 U_BOOT_CMD(
 	irqinfo,    1,    1,     do_irqinfo,
 	"print information about IRQs",
diff --git a/cmd/tcpm.c b/cmd/tcpm.c
new file mode 100644
index 0000000..39578f6
--- /dev/null
+++ b/cmd/tcpm.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Collabora
+ */
+
+#include <command.h>
+#include <errno.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <usb/tcpm.h>
+
+#define LIMIT_DEV	32
+#define LIMIT_PARENT	20
+
+static struct udevice *currdev;
+
+static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int devnum, ret;
+
+	switch (argc) {
+	case 2:
+		devnum = (int)dectoul(argv[1], NULL);
+		ret = tcpm_get(devnum, &currdev);
+		if (ret) {
+			log_err("Can't get TCPM %d: %d (%s)!\n", devnum, ret, errno_str(ret));
+			return CMD_RET_FAILURE;
+		}
+	case 1:
+		if (!currdev) {
+			log_err("TCPM device is not set!\n\n");
+			return CMD_RET_USAGE;
+		}
+
+		printf("dev: %d @ %s\n", dev_seq(currdev), currdev->name);
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_list(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	struct udevice *dev;
+	int ret, err = 0;
+
+	printf("| ID | %-*.*s| %-*.*s| %s @ %s\n",
+	       LIMIT_DEV, LIMIT_DEV, "Name",
+	       LIMIT_PARENT, LIMIT_PARENT, "Parent name",
+	       "Parent uclass", "seq");
+
+	for (ret = uclass_first_device_check(UCLASS_TCPM, &dev); dev;
+	     ret = uclass_next_device_check(&dev)) {
+		if (ret)
+			err = ret;
+
+		printf("| %2d | %-*.*s| %-*.*s| %s @ %d | status: %i\n",
+		       dev_seq(dev),
+		       LIMIT_DEV, LIMIT_DEV, dev->name,
+		       LIMIT_PARENT, LIMIT_PARENT, dev->parent->name,
+		       dev_get_uclass_name(dev->parent), dev_seq(dev->parent),
+		       ret);
+	}
+
+	if (err)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+int do_print_info(struct udevice *dev)
+{
+	enum typec_orientation orientation = tcpm_get_orientation(dev);
+	const char *state = tcpm_get_state(dev);
+	int pd_rev = tcpm_get_pd_rev(dev);
+	int mv = tcpm_get_voltage(dev);
+	int ma = tcpm_get_current(dev);
+	enum typec_role pwr_role = tcpm_get_pwr_role(dev);
+	enum typec_data_role data_role = tcpm_get_data_role(dev);
+	bool connected = tcpm_is_connected(dev);
+
+	if (!connected) {
+		printf("TCPM State: %s\n", state);
+		return 0;
+	}
+
+	printf("Orientation: %s\n", typec_orientation_name[orientation]);
+	printf("PD Revision: %s\n", typec_pd_rev_name[pd_rev]);
+	printf("Power Role:  %s\n", typec_role_name[pwr_role]);
+	printf("Data Role:   %s\n", typec_data_role_name[data_role]);
+	printf("Voltage:     %2d.%03d V\n", mv / 1000, mv % 1000);
+	printf("Current:     %2d.%03d A\n", ma / 1000, ma % 1000);
+
+	return 0;
+}
+
+static int do_info(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	if (!currdev) {
+		printf("First, set the TCPM device!\n");
+		return CMD_RET_USAGE;
+	}
+
+	return do_print_info(currdev);
+}
+
+static struct cmd_tbl subcmd[] = {
+	U_BOOT_CMD_MKENT(dev, 2, 1, do_dev, "", ""),
+	U_BOOT_CMD_MKENT(list, 1, 1, do_list, "", ""),
+	U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
+};
+
+static int do_tcpm(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	struct cmd_tbl *cmd;
+
+	argc--;
+	argv++;
+
+	cmd = find_cmd_tbl(argv[0], subcmd, ARRAY_SIZE(subcmd));
+	if (!cmd || argc > cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	return cmd->cmd(cmdtp, flag, argc, argv);
+}
+
+ /**************************************************/
+
+U_BOOT_CMD(tcpm, CONFIG_SYS_MAXARGS, 1, do_tcpm,
+	"TCPM sub-system",
+	"list          - list TCPM devices\n"
+	"tcpm dev [ID]      - show or [set] operating TCPM device\n"
+	"tcpm info          - dump information\n"
+);
diff --git a/common/Kconfig b/common/Kconfig
index 0339b9e..90cee19 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -850,6 +850,7 @@
 	depends on LIBAVB
 	depends on MMC
 	depends on PARTITION_UUIDS
+	depends on FASTBOOT
 	help
 	  This option enables compilation of bootloader-dependent operations,
 	  used by Android Verified Boot 2.0 library (libavb). Includes:
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 24be88b..c396171 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -45,6 +45,7 @@
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index f386875..2e758b4 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -68,6 +68,7 @@
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_NO_NET=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 0b7ee94..003fa4f 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -63,6 +63,7 @@
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 3019525..6ff0782 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -75,6 +75,7 @@
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 2fbfda5..ffa4a0e 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -91,6 +91,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index dcb7087..1db9251 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -76,6 +76,7 @@
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 640c1be..bd55634 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -97,6 +97,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 4c2d53b..ad6dbbc 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -85,6 +85,7 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 769c609..d619ac8 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -90,6 +90,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index eeb38af..a89e029 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -86,6 +86,7 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index f022017..c7fc6be 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -42,6 +42,7 @@
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
 CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_I2C=y
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 2281517..0b5441f 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -73,6 +73,7 @@
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index dd360d5..6bea782 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -24,6 +24,7 @@
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -103,3 +104,6 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_FUSB302=y
+CONFIG_CMD_TCPM=y
diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig
index ff9707d..1ca057c 100644
--- a/configs/stm32mp13_dhcor_defconfig
+++ b/configs/stm32mp13_dhcor_defconfig
@@ -6,7 +6,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x3E0000
 CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dhcor-dhsbc"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp135f-dhcor-dhsbc"
 CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_STM32MP13X=y
@@ -65,6 +65,7 @@
 CONFIG_CMD_UBI=y
 # CONFIG_ISO_PARTITION is not set
 CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_MAX_HZ=50000000
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 7426a78..a92c615d 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -7,7 +7,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-dhcom-pdk2"
 CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_MMC=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@@ -32,7 +32,6 @@
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
-CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
@@ -56,7 +55,6 @@
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_TARGET="u-boot.itb"
 CONFIG_SYS_PROMPT="STM32MP> "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_EXPORTENV is not set
@@ -92,7 +90,8 @@
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_OF_LIVE=y
-CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index b6d7f1e..4162eda 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -7,7 +7,7 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96"
 CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_MMC=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
@@ -30,7 +30,6 @@
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
-CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
@@ -54,7 +53,6 @@
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_TARGET="u-boot.itb"
 CONFIG_SYS_PROMPT="STM32MP> "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_EXPORTENV is not set
@@ -90,7 +88,8 @@
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_OF_LIVE=y
-CONFIG_OF_LIST="stm32mp15xx-dhcor-avenger96 stm32mp15xx-dhcor-testbench stm32mp15xx-dhcor-drc-compact"
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
index 63b4477..8cf7129 100644
--- a/doc/board/st/stm32mp1.rst
+++ b/doc/board/st/stm32mp1.rst
@@ -180,35 +180,54 @@
 
 STM32MP15x device Tree Selection
 ````````````````````````````````
-The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig) are:
+The supported device trees for STM32MP15x (**stm32mp15_defconfig** for TF-A_
+with FIP support) are:
 
 + ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
 
+   + **stm32mp157c-ev1-scmi**
    + stm32mp157c-ev1
 
 + ed1: daughter board with pmic stpmic1
 
+   + **stm32mp157c-ed1-scmi**
    + stm32mp157c-ed1
 
 + dk1: Discovery board
 
+   + **stm32mp157a-dk1-scmi**
    + stm32mp157a-dk1
 
 + dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel
 
+   + **stm32mp157c-dk2-scmi**
    + stm32mp157c-dk2
 
+The scmi variant of each device tree is only supported with OP-TEE as secure
+monitor and it is the configuration **recommended** by STMicroelectronics for
+product, with secured system resources (RCC_TZCR.TZEN=1).
+
+The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig
+TF-A without FIP support and stm32mp15_basic_defconfig with SPL) are:
+
++ the same STMicroelectronics boards with the no scmi device tree files:
+
+   + stm32mp157c-ev1
+   + stm32mp157c-ed1
+   + stm32mp157a-dk1
+   + stm32mp157c-dk2
+
 + avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM
 
    + stm32mp15xx-dhcor-avenger96
 
 STM32MP13x device Tree Selection
 ````````````````````````````````
-The supported device trees for STM32MP13x (stm32mp13_defconfig) are:
+The supported device trees for STM32MP13x (**stm32mp13_defconfig**) are:
 
 + dk: Discovery board
 
-   + stm32mp135f-dk
+   + **stm32mp135f-dk**
 
 
 Build Procedure
diff --git a/doc/git-mailrc b/doc/git-mailrc
index ca2f67a..1177e42 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -22,7 +22,7 @@
 alias bmeng          Bin Meng <bmeng.cn@gmail.com>
 alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 alias dinh           Dinh Nguyen <dinguyen@kernel.org>
-alias ehristev       Eugen Hristev <eugen.hristev@collabora.com>
+alias ehristev       Eugen Hristev <eugen.hristev@linaro.org>
 alias hs             Heiko Schocher <hs@denx.de>
 alias freenix        Peng Fan <peng.fan@nxp.com>
 alias iwamatsu       Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/doc/usage/cmd/tcpm.rst b/doc/usage/cmd/tcpm.rst
new file mode 100644
index 0000000..eb2c69d
--- /dev/null
+++ b/doc/usage/cmd/tcpm.rst
@@ -0,0 +1,66 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+.. index::
+   single: tcpm (command)
+
+tcpm command
+============
+
+Synopsis
+--------
+
+::
+
+    tcpm dev [devnum]
+    tcpm info
+    tcpm list
+
+Description
+-----------
+
+The tcpm command is used to control USB-PD controllers, also known as TypeC Port Manager (TCPM).
+
+The 'tcpm dev' command shows or set current TCPM device.
+
+    devnum
+        device number to change
+
+The 'tcpm info' command displays the current state of the device
+
+The 'tcpm list' command displays the list available devices.
+
+Examples
+--------
+
+The 'tcpm info' command displays device's status:
+::
+
+    => tcpm info
+    Orientation: normal
+    PD Revision: rev3
+    Power Role:  sink
+    Data Role:   device
+    Voltage:     20.000 V
+    Current:      2.250 A
+
+The current device can be shown or set via 'tcpm dev' command:
+::
+
+    => tcpm dev
+    TCPM device is not set!
+    => tcpm dev 0
+    dev: 0 @ usb-typec@22
+    => tcpm dev
+    dev: 0 @ usb-typec@22
+
+The list of available devices can be shown via 'tcpm list' command:
+::
+
+    => tcpm list
+    | ID | Name                            | Parent name         | Parent uclass @ seq
+    |  0 | usb-typec@22                    | i2c@feac0000        | i2c @ 4 | status: 0
+
+Configuration
+-------------
+
+The tcpm command is only available if CONFIG_CMD_TCPM=y.
diff --git a/doc/usage/fit/howto.rst b/doc/usage/fit/howto.rst
index b5097d4..280eff7 100644
--- a/doc/usage/fit/howto.rst
+++ b/doc/usage/fit/howto.rst
@@ -57,14 +57,9 @@
 multiple /configurations subnodes. The required images must be enumerated in
 the "loadables" property as a list of strings.
 
-If a platform specific image source file (.its) is shipped with the U-Boot
-source, it can be specified using the CONFIG_SPL_FIT_SOURCE Kconfig symbol.
-In this case it will be automatically used by U-Boot's Makefile to generate
-the image.
-If a static source file is not flexible enough, CONFIG_SPL_FIT_GENERATOR
-can point to a script which generates this image source file during
-the build process. It gets passed a list of device tree files (taken from the
-CONFIG_OF_LIST symbol).
+CONFIG_SPL_FIT_GENERATOR can point to a script which generates this image source
+file during the build process. It gets passed a list of device tree files (taken
+from the CONFIG_OF_LIST symbol).
 
 The SPL also records to a DT all additional images (called loadables) which are
 loaded. The information about loadables locations is passed via the DT node with
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 7056337..fcce125 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -112,6 +112,7 @@
    cmd/smbios
    cmd/sound
    cmd/source
+   cmd/tcpm
    cmd/temperature
    cmd/tftpput
    cmd/trace
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index e23d09e..dac4023 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1700,141 +1700,6 @@
 	return ch_count;
 }
 
-static int udma_probe(struct udevice *dev)
-{
-	struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-	struct udma_dev *ud = dev_get_priv(dev);
-	int i, ret;
-	struct udevice *tmp;
-	struct udevice *tisci_dev = NULL;
-	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
-	ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
-
-	ud->match_data = (void *)dev_get_driver_data(dev);
-	ret = udma_get_mmrs(dev);
-	if (ret)
-		return ret;
-
-	ud->psil_base = ud->match_data->psil_base;
-
-	ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
-					   "ti,sci", &tisci_dev);
-	if (ret) {
-		debug("Failed to get TISCI phandle (%d)\n", ret);
-		tisci_rm->tisci = NULL;
-		return -EINVAL;
-	}
-	tisci_rm->tisci = (struct ti_sci_handle *)
-			  (ti_sci_get_handle_from_sysfw(tisci_dev));
-
-	tisci_rm->tisci_dev_id = -1;
-	ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
-	if (ret) {
-		dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
-		return ret;
-	}
-
-	tisci_rm->tisci_navss_dev_id = -1;
-	ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
-			      &tisci_rm->tisci_navss_dev_id);
-	if (ret) {
-		dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
-		return ret;
-	}
-
-	tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
-	tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
-
-	if (ud->match_data->type == DMA_TYPE_UDMA) {
-		ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
-						   "ti,ringacc", &tmp);
-		ud->ringacc = dev_get_priv(tmp);
-	} else {
-		struct k3_ringacc_init_data ring_init_data;
-
-		ring_init_data.tisci = ud->tisci_rm.tisci;
-		ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
-		if (ud->match_data->type == DMA_TYPE_BCDMA) {
-			ring_init_data.num_rings = ud->bchan_cnt +
-						   ud->tchan_cnt +
-						   ud->rchan_cnt;
-		} else {
-			ring_init_data.num_rings = ud->rflow_cnt +
-						   ud->tflow_cnt;
-		}
-
-		ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
-	}
-	if (IS_ERR(ud->ringacc))
-		return PTR_ERR(ud->ringacc);
-
-	ud->dev = dev;
-	ret = setup_resources(ud);
-	if (ret < 0)
-		return ret;
-
-	ud->ch_count = ret;
-
-	for (i = 0; i < ud->bchan_cnt; i++) {
-		struct udma_bchan *bchan = &ud->bchans[i];
-
-		bchan->id = i;
-		bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
-	}
-
-	for (i = 0; i < ud->tchan_cnt; i++) {
-		struct udma_tchan *tchan = &ud->tchans[i];
-
-		tchan->id = i;
-		tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
-		tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
-	}
-
-	for (i = 0; i < ud->rchan_cnt; i++) {
-		struct udma_rchan *rchan = &ud->rchans[i];
-
-		rchan->id = i;
-		rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
-		rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
-	}
-
-	for (i = 0; i < ud->rflow_cnt; i++) {
-		struct udma_rflow *rflow = &ud->rflows[i];
-
-		rflow->id = i;
-		rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
-	}
-
-	for (i = 0; i < ud->ch_count; i++) {
-		struct udma_chan *uc = &ud->channels[i];
-
-		uc->ud = ud;
-		uc->id = i;
-		uc->config.remote_thread_id = -1;
-		uc->bchan = NULL;
-		uc->tchan = NULL;
-		uc->rchan = NULL;
-		uc->config.mapped_channel_id = -1;
-		uc->config.default_flow_id = -1;
-		uc->config.dir = DMA_MEM_TO_MEM;
-		sprintf(uc->name, "UDMA chan%d\n", i);
-		if (!i)
-			uc->in_use = true;
-	}
-
-	pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
-		 dev->name,
-		 udma_read(ud->mmrs[MMR_GCFG], 0),
-		 udma_read(ud->mmrs[MMR_GCFG], 0x20),
-		 udma_read(ud->mmrs[MMR_GCFG], 0x24),
-		 udma_read(ud->mmrs[MMR_GCFG], 0x28),
-		 udma_read(ud->mmrs[MMR_GCFG], 0x2c));
-
-	uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
-
-	return 0;
-}
-
 static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem)
 {
 	u64 addr = 0;
@@ -2325,37 +2190,12 @@
 	/* Channel0 is reserved for memcpy */
 	struct udma_chan *uc = &ud->channels[0];
 	dma_addr_t paddr = 0;
-	int ret;
-
-	switch (ud->match_data->type) {
-	case DMA_TYPE_UDMA:
-		ret = udma_alloc_chan_resources(uc);
-		break;
-	case DMA_TYPE_BCDMA:
-		ret = bcdma_alloc_chan_resources(uc);
-		break;
-	default:
-		return -EINVAL;
-	};
-	if (ret)
-		return ret;
 
 	udma_prep_dma_memcpy(uc, dst, src, len);
 	udma_start(uc);
 	udma_poll_completion(uc, &paddr);
 	udma_stop(uc);
 
-	switch (ud->match_data->type) {
-	case DMA_TYPE_UDMA:
-		udma_free_chan_resources(uc);
-		break;
-	case DMA_TYPE_BCDMA:
-		bcdma_free_bchan_resources(uc);
-		break;
-	default:
-		return -EINVAL;
-	};
-
 	return 0;
 }
 
@@ -2717,6 +2557,177 @@
 	return -EINVAL;
 }
 
+static int udma_probe(struct udevice *dev)
+{
+	struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct udma_dev *ud = dev_get_priv(dev);
+	int i, ret;
+	struct udevice *tmp;
+	struct udevice *tisci_dev = NULL;
+	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+	struct udma_chan *uc;
+	ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
+
+	ud->match_data = (void *)dev_get_driver_data(dev);
+	ret = udma_get_mmrs(dev);
+	if (ret)
+		return ret;
+
+	ud->psil_base = ud->match_data->psil_base;
+
+	ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
+					   "ti,sci", &tisci_dev);
+	if (ret) {
+		debug("Failed to get TISCI phandle (%d)\n", ret);
+		tisci_rm->tisci = NULL;
+		return -EINVAL;
+	}
+	tisci_rm->tisci = (struct ti_sci_handle *)
+			  (ti_sci_get_handle_from_sysfw(tisci_dev));
+
+	tisci_rm->tisci_dev_id = -1;
+	ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
+	if (ret) {
+		dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
+		return ret;
+	}
+
+	tisci_rm->tisci_navss_dev_id = -1;
+	ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
+			      &tisci_rm->tisci_navss_dev_id);
+	if (ret) {
+		dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
+		return ret;
+	}
+
+	tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
+	tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
+
+	if (ud->match_data->type == DMA_TYPE_UDMA) {
+		ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
+						   "ti,ringacc", &tmp);
+		ud->ringacc = dev_get_priv(tmp);
+	} else {
+		struct k3_ringacc_init_data ring_init_data;
+
+		ring_init_data.tisci = ud->tisci_rm.tisci;
+		ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
+		if (ud->match_data->type == DMA_TYPE_BCDMA) {
+			ring_init_data.num_rings = ud->bchan_cnt +
+						   ud->tchan_cnt +
+						   ud->rchan_cnt;
+		} else {
+			ring_init_data.num_rings = ud->rflow_cnt +
+						   ud->tflow_cnt;
+		}
+
+		ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
+	}
+	if (IS_ERR(ud->ringacc))
+		return PTR_ERR(ud->ringacc);
+
+	ud->dev = dev;
+	ret = setup_resources(ud);
+	if (ret < 0)
+		return ret;
+
+	ud->ch_count = ret;
+
+	for (i = 0; i < ud->bchan_cnt; i++) {
+		struct udma_bchan *bchan = &ud->bchans[i];
+
+		bchan->id = i;
+		bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
+	}
+
+	for (i = 0; i < ud->tchan_cnt; i++) {
+		struct udma_tchan *tchan = &ud->tchans[i];
+
+		tchan->id = i;
+		tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
+		tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
+	}
+
+	for (i = 0; i < ud->rchan_cnt; i++) {
+		struct udma_rchan *rchan = &ud->rchans[i];
+
+		rchan->id = i;
+		rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
+		rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
+	}
+
+	for (i = 0; i < ud->rflow_cnt; i++) {
+		struct udma_rflow *rflow = &ud->rflows[i];
+
+		rflow->id = i;
+		rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
+	}
+
+	for (i = 0; i < ud->ch_count; i++) {
+		struct udma_chan *uc = &ud->channels[i];
+
+		uc->ud = ud;
+		uc->id = i;
+		uc->config.remote_thread_id = -1;
+		uc->bchan = NULL;
+		uc->tchan = NULL;
+		uc->rchan = NULL;
+		uc->config.mapped_channel_id = -1;
+		uc->config.default_flow_id = -1;
+		uc->config.dir = DMA_MEM_TO_MEM;
+		sprintf(uc->name, "UDMA chan%d\n", i);
+		if (!i)
+			uc->in_use = true;
+	}
+
+	pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+		 dev->name,
+		 udma_read(ud->mmrs[MMR_GCFG], 0),
+		 udma_read(ud->mmrs[MMR_GCFG], 0x20),
+		 udma_read(ud->mmrs[MMR_GCFG], 0x24),
+		 udma_read(ud->mmrs[MMR_GCFG], 0x28),
+		 udma_read(ud->mmrs[MMR_GCFG], 0x2c));
+
+	uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
+
+	uc = &ud->channels[0];
+	ret = 0;
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		ret = udma_alloc_chan_resources(uc);
+		break;
+	case DMA_TYPE_BCDMA:
+		ret = bcdma_alloc_chan_resources(uc);
+		break;
+	default:
+		break; /* Do nothing in any other case */
+	};
+
+	if (ret)
+		dev_err(dev, " Channel 0 allocation failure %d\n", ret);
+
+	return ret;
+}
+
+static int udma_remove(struct udevice *dev)
+{
+	struct udma_dev *ud = dev_get_priv(dev);
+	struct udma_chan *uc = &ud->channels[0];
+
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		udma_free_chan_resources(uc);
+		break;
+	case DMA_TYPE_BCDMA:
+		bcdma_free_bchan_resources(uc);
+		break;
+	default:
+		break;
+	};
+
+	return 0;
+}
+
 static const struct dma_ops udma_ops = {
 	.transfer	= udma_transfer,
 	.of_xlate	= udma_of_xlate,
@@ -2855,5 +2866,7 @@
 	.of_match = udma_ids,
 	.ops	= &udma_ops,
 	.probe	= udma_probe,
+	.remove = udma_remove,
 	.priv_auto	= sizeof(struct udma_dev),
+	.flags  = DM_FLAG_OS_PREPARE,
 };
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 9feaa1e..a08678d 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -18,6 +18,7 @@
 #include <dm/lists.h>
 #include <dm/device-internal.h>
 #include <dm/of_access.h>
+#include <linux/build_bug.h>
 #include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -328,11 +329,15 @@
 static int _serial_tstc(struct udevice *dev)
 {
 	struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
+	uint wr, avail;
 
-	/* Read all available chars into the RX buffer */
-	while (__serial_tstc(dev)) {
-		upriv->buf[upriv->wr_ptr++] = __serial_getc(dev);
-		upriv->wr_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE;
+	BUILD_BUG_ON_NOT_POWER_OF_2(CONFIG_SERIAL_RX_BUFFER_SIZE);
+
+	/* Read all available chars into the RX buffer while there's room */
+	avail = CONFIG_SERIAL_RX_BUFFER_SIZE - (upriv->wr_ptr - upriv->rd_ptr);
+	while (avail-- && __serial_tstc(dev)) {
+		wr = upriv->wr_ptr++ % CONFIG_SERIAL_RX_BUFFER_SIZE;
+		upriv->buf[wr] = __serial_getc(dev);
 	}
 
 	return upriv->rd_ptr != upriv->wr_ptr ? 1 : 0;
@@ -342,12 +347,13 @@
 {
 	struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
 	char val;
+	uint rd;
 
 	if (upriv->rd_ptr == upriv->wr_ptr)
 		return __serial_getc(dev);
 
-	val = upriv->buf[upriv->rd_ptr++];
-	upriv->rd_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE;
+	rd = upriv->rd_ptr++ % CONFIG_SERIAL_RX_BUFFER_SIZE;
+	val = upriv->buf[rd];
 
 	return val;
 }
@@ -582,11 +588,6 @@
 	sdev.getc = serial_stub_getc;
 	sdev.tstc = serial_stub_tstc;
 
-#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER)
-	/* Allocate the RX buffer */
-	upriv->buf = malloc(CONFIG_SERIAL_RX_BUFFER_SIZE);
-#endif
-
 	stdio_register_dev(&sdev, &upriv->sdev);
 #endif
 	return 0;
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 311aaa7..960b6a9 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -85,6 +85,8 @@
 
 source "drivers/usb/phy/Kconfig"
 
+source "drivers/usb/tcpm/Kconfig"
+
 source "drivers/usb/ulpi/Kconfig"
 
 if USB_HOST
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index ac7e469..a30c40e 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -1637,6 +1637,14 @@
 	else
 		priv_ep->trb_burst_size = 16;
 
+	/*
+	 * The Endpoint is configured to handle a maximum packet size of
+	 * max_packet_size. Hence, set priv_ep->endpoint.maxpacket to
+	 * max_packet_size. This is necessary to ensure that the TD_SIZE
+	 * is calculated correctly in cdns3_ep_run_transfer().
+	 */
+	priv_ep->endpoint.maxpacket = max_packet_size;
+
 	ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
 					     !!priv_ep->dir);
 	if (ret) {
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7374ce9..b572ea3 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -670,6 +670,7 @@
  * @ep0_trb: dma address of ep0_trb
  * @ep0_usb_req: dummy req used while handling STD USB requests
  * @ep0_bounce_addr: dma address of ep0_bounce
+ * @setup_buf_addr: dma address of setup_buf
  * @scratch_addr: dma address of scratchbuf
  * @lock: for synchronizing
  * @dev: pointer to our struct device
@@ -757,6 +758,7 @@
 	dma_addr_t		ep0_trb_addr;
 	dma_addr_t		ep0_bounce_addr;
 	dma_addr_t		scratch_addr;
+	dma_addr_t		setup_buf_addr;
 	struct dwc3_request	ep0_usb_req;
 
 	/* device lock */
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 24f516a..531f0b5 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -380,7 +380,7 @@
 	dep = dwc->eps[0];
 	dwc->ep0_usb_req.dep = dep;
 	dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
-	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
+	dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr;
 	dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 
 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
@@ -662,7 +662,7 @@
 	dep = dwc->eps[0];
 	dwc->ep0_usb_req.dep = dep;
 	dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
-	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
+	dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr;
 	dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 
 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
@@ -742,6 +742,8 @@
 	if (!dwc->gadget_driver)
 		goto out;
 
+	dwc3_invalidate_cache((uintptr_t)ctrl, sizeof(*ctrl));
+
 	len = le16_to_cpu(ctrl->wLength);
 	if (!len) {
 		dwc->three_stage_setup = false;
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index fe33e30..e5a3834 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2534,6 +2534,8 @@
 	while (left > 0) {
 		union dwc3_event event;
 
+		dwc3_invalidate_cache((uintptr_t)evt->buf, evt->length);
+
 		event.raw = *(u32 *) (evt->buf + evt->lpos);
 
 		dwc3_process_event_entry(dwc, &event);
@@ -2653,8 +2655,8 @@
 		goto err1;
 	}
 
-	dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
-				  DWC3_EP0_BOUNCE_SIZE);
+	dwc->setup_buf = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
+					(unsigned long *)&dwc->setup_buf_addr);
 	if (!dwc->setup_buf) {
 		ret = -ENOMEM;
 		goto err2;
@@ -2701,7 +2703,7 @@
 	dma_free_coherent(dwc->ep0_bounce);
 
 err3:
-	kfree(dwc->setup_buf);
+	dma_free_coherent(dwc->setup_buf);
 
 err2:
 	dma_free_coherent(dwc->ep0_trb);
@@ -2723,7 +2725,7 @@
 
 	dma_free_coherent(dwc->ep0_bounce);
 
-	kfree(dwc->setup_buf);
+	dma_free_coherent(dwc->setup_buf);
 
 	dma_free_coherent(dwc->ep0_trb);
 
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
index 04791d4..c1ab028 100644
--- a/drivers/usb/dwc3/io.h
+++ b/drivers/usb/dwc3/io.h
@@ -50,6 +50,17 @@
 
 static inline void dwc3_flush_cache(uintptr_t addr, int length)
 {
-	flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
+	uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1);
+	uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE);
+
+	flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr);
+}
+
+static inline void dwc3_invalidate_cache(uintptr_t addr, int length)
+{
+	uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1);
+	uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE);
+
+	invalidate_dcache_range((unsigned long)start_addr, (unsigned long)end_addr);
 }
 #endif /* __DRIVERS_USB_DWC3_IO_H */
diff --git a/drivers/usb/tcpm/Kconfig b/drivers/usb/tcpm/Kconfig
new file mode 100644
index 0000000..9be4b49
--- /dev/null
+++ b/drivers/usb/tcpm/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config TYPEC_TCPM
+	tristate "USB Type-C Port Controller Manager"
+	depends on DM
+	help
+	  The Type-C Port Controller Manager provides a USB PD and USB Type-C
+	  state machine for use with Type-C Port Controllers.
+
+config TYPEC_FUSB302
+	tristate "Fairchild FUSB302 Type-C chip driver"
+	depends on DM && DM_I2C && TYPEC_TCPM
+	help
+	  The Fairchild FUSB302 Type-C chip driver that works with
+	  Type-C Port Controller Manager to provide USB PD and USB
+	  Type-C functionalities.
diff --git a/drivers/usb/tcpm/Makefile b/drivers/usb/tcpm/Makefile
new file mode 100644
index 0000000..668d331
--- /dev/null
+++ b/drivers/usb/tcpm/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_TYPEC_TCPM) += tcpm.o tcpm-uclass.o
+obj-$(CONFIG_TYPEC_FUSB302) += fusb302.o
diff --git a/drivers/usb/tcpm/fusb302.c b/drivers/usb/tcpm/fusb302.c
new file mode 100644
index 0000000..fe93ff3
--- /dev/null
+++ b/drivers/usb/tcpm/fusb302.c
@@ -0,0 +1,1323 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016-2017 Google, Inc
+ *
+ * Fairchild FUSB302 Type-C Chip Driver
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <dm/device_compat.h>
+#include <usb/tcpm.h>
+#include "fusb302_reg.h"
+
+#define FUSB302_MAX_MSG_LEN 0x1F
+
+enum toggling_mode {
+	TOGGLING_MODE_OFF,
+	TOGGLING_MODE_DRP,
+	TOGGLING_MODE_SNK,
+	TOGGLING_MODE_SRC,
+};
+
+enum src_current_status {
+	SRC_CURRENT_DEFAULT,
+	SRC_CURRENT_MEDIUM,
+	SRC_CURRENT_HIGH,
+};
+
+static const u8 ra_mda_value[] = {
+	[SRC_CURRENT_DEFAULT] = 4,	/* 210mV */
+	[SRC_CURRENT_MEDIUM] = 9,	/* 420mV */
+	[SRC_CURRENT_HIGH] = 18,	/* 798mV */
+};
+
+static const u8 rd_mda_value[] = {
+	[SRC_CURRENT_DEFAULT] = 38,	/* 1638mV */
+	[SRC_CURRENT_MEDIUM] = 38,	/* 1638mV */
+	[SRC_CURRENT_HIGH] = 61,	/* 2604mV */
+};
+
+struct fusb302_chip {
+	enum toggling_mode toggling_mode;
+	enum src_current_status src_current_status;
+	bool intr_togdone;
+	bool intr_bc_lvl;
+	bool intr_comp_chng;
+
+	/* port status */
+	bool vconn_on;
+	bool vbus_present;
+	enum typec_cc_polarity cc_polarity;
+	enum typec_cc_status cc1;
+	enum typec_cc_status cc2;
+};
+
+static int fusb302_i2c_write(struct udevice *dev, u8 address, u8 data)
+{
+	int ret;
+
+	ret = dm_i2c_write(dev, address, &data, 1);
+	if (ret)
+		dev_err(dev, "cannot write 0x%02x to 0x%02x, ret=%d\n",
+			data, address, ret);
+
+	return ret;
+}
+
+static int fusb302_i2c_block_write(struct udevice *dev, u8 address,
+				   u8 length, const u8 *data)
+{
+	int ret;
+
+	if (!length)
+		return 0;
+
+	ret = dm_i2c_write(dev, address, data, length);
+	if (ret)
+		dev_err(dev, "cannot block write 0x%02x, len=%d, ret=%d\n",
+			address, length, ret);
+
+	return ret;
+}
+
+static int fusb302_i2c_read(struct udevice *dev, u8 address, u8 *data)
+{
+	int ret, retries;
+
+	for (retries = 0; retries < 3; retries++) {
+		ret = dm_i2c_read(dev, address, data, 1);
+		if (ret == 0)
+			return ret;
+		dev_err(dev, "cannot read %02x, ret=%d\n", address, ret);
+	}
+
+	return ret;
+}
+
+static int fusb302_i2c_block_read(struct udevice *dev, u8 address,
+				  u8 length, u8 *data)
+{
+	int ret;
+
+	if (!length)
+		return 0;
+
+	ret = dm_i2c_read(dev, address, data, length);
+	if (ret)
+		dev_err(dev, "cannot block read 0x%02x, len=%d, ret=%d\n",
+			address, length, ret);
+	return ret;
+}
+
+static int fusb302_i2c_mask_write(struct udevice *dev, u8 address,
+				  u8 mask, u8 value)
+{
+	int ret;
+	u8 data;
+
+	ret = fusb302_i2c_read(dev, address, &data);
+	if (ret)
+		return ret;
+	data &= ~mask;
+	data |= value;
+	ret = fusb302_i2c_write(dev, address, data);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static int fusb302_i2c_set_bits(struct udevice *dev, u8 address, u8 set_bits)
+{
+	return fusb302_i2c_mask_write(dev, address, 0x00, set_bits);
+}
+
+static int fusb302_i2c_clear_bits(struct udevice *dev, u8 address, u8 clear_bits)
+{
+	return fusb302_i2c_mask_write(dev, address, clear_bits, 0x00);
+}
+
+static int fusb302_sw_reset(struct udevice *dev)
+{
+	int ret = fusb302_i2c_write(dev, FUSB_REG_RESET, FUSB_REG_RESET_SW_RESET);
+
+	if (ret)
+		dev_err(dev, "cannot sw reset the fusb302: %d\n", ret);
+
+	return ret;
+}
+
+static int fusb302_enable_tx_auto_retries(struct udevice *dev, u8 retry_count)
+{
+	int ret;
+
+	ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL3, retry_count |
+				   FUSB_REG_CONTROL3_AUTO_RETRY);
+
+	return ret;
+}
+
+/*
+ * mask all interrupt on the chip
+ */
+static int fusb302_mask_interrupt(struct udevice *dev)
+{
+	int ret;
+
+	ret = fusb302_i2c_write(dev, FUSB_REG_MASK, 0xFF);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_write(dev, FUSB_REG_MASKA, 0xFF);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_write(dev, FUSB_REG_MASKB, 0xFF);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL0,
+				   FUSB_REG_CONTROL0_INT_MASK);
+		return ret;
+}
+
+/*
+ * initialize interrupt on the chip
+ * - unmasked interrupt: VBUS_OK
+ */
+static int fusb302_init_interrupt(struct udevice *dev)
+{
+	int ret;
+
+	ret = fusb302_i2c_write(dev, FUSB_REG_MASK,
+				0xFF & ~FUSB_REG_MASK_VBUSOK);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_write(dev, FUSB_REG_MASKA, 0xFF);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_write(dev, FUSB_REG_MASKB, 0xFF);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_clear_bits(dev, FUSB_REG_CONTROL0,
+				     FUSB_REG_CONTROL0_INT_MASK);
+	return ret;
+}
+
+static int fusb302_set_power_mode(struct udevice *dev, u8 power_mode)
+{
+	int ret;
+
+	ret = fusb302_i2c_write(dev, FUSB_REG_POWER, power_mode);
+
+	return ret;
+}
+
+static int fusb302_init(struct udevice *dev)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	int ret;
+	u8 data;
+
+	ret = fusb302_sw_reset(dev);
+	if (ret)
+		return ret;
+	ret = fusb302_enable_tx_auto_retries(dev, FUSB_REG_CONTROL3_N_RETRIES_3);
+	if (ret)
+		return ret;
+	ret = fusb302_init_interrupt(dev);
+	if (ret)
+		return ret;
+	ret = fusb302_set_power_mode(dev, FUSB_REG_POWER_PWR_ALL);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &data);
+	if (ret)
+		return ret;
+	chip->vbus_present = !!(data & FUSB_REG_STATUS0_VBUSOK);
+	ret = fusb302_i2c_read(dev, FUSB_REG_DEVICE_ID, &data);
+	if (ret)
+		return ret;
+	dev_info(dev, "fusb302 device ID: 0x%02x\n", data);
+
+	return ret;
+}
+
+static int fusb302_get_vbus(struct udevice *dev)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+
+	return chip->vbus_present ? 1 : 0;
+}
+
+static int fusb302_set_src_current(struct udevice *dev,
+				   enum src_current_status status)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	int ret;
+
+	chip->src_current_status = status;
+	switch (status) {
+	case SRC_CURRENT_DEFAULT:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0,
+					     FUSB_REG_CONTROL0_HOST_CUR_MASK,
+					     FUSB_REG_CONTROL0_HOST_CUR_DEF);
+		break;
+	case SRC_CURRENT_MEDIUM:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0,
+					     FUSB_REG_CONTROL0_HOST_CUR_MASK,
+					     FUSB_REG_CONTROL0_HOST_CUR_MED);
+		break;
+	case SRC_CURRENT_HIGH:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0,
+					     FUSB_REG_CONTROL0_HOST_CUR_MASK,
+					     FUSB_REG_CONTROL0_HOST_CUR_HIGH);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int fusb302_set_toggling(struct udevice *dev,
+				enum toggling_mode mode)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	int ret;
+
+	/* first disable toggling */
+	ret = fusb302_i2c_clear_bits(dev, FUSB_REG_CONTROL2,
+				     FUSB_REG_CONTROL2_TOGGLE);
+	if (ret)
+		return ret;
+	/* mask interrupts for SRC or SNK */
+	ret = fusb302_i2c_set_bits(dev, FUSB_REG_MASK,
+				   FUSB_REG_MASK_BC_LVL |
+				   FUSB_REG_MASK_COMP_CHNG);
+	if (ret)
+		return ret;
+	chip->intr_bc_lvl = false;
+	chip->intr_comp_chng = false;
+	/* configure toggling mode: none/snk/src/drp */
+	switch (mode) {
+	case TOGGLING_MODE_OFF:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+					     FUSB_REG_CONTROL2_MODE_MASK,
+					     FUSB_REG_CONTROL2_MODE_NONE);
+		break;
+	case TOGGLING_MODE_SNK:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+					     FUSB_REG_CONTROL2_MODE_MASK,
+					     FUSB_REG_CONTROL2_MODE_UFP);
+		break;
+	case TOGGLING_MODE_SRC:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+					     FUSB_REG_CONTROL2_MODE_MASK,
+					     FUSB_REG_CONTROL2_MODE_DFP);
+		break;
+	case TOGGLING_MODE_DRP:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+					     FUSB_REG_CONTROL2_MODE_MASK,
+					     FUSB_REG_CONTROL2_MODE_DRP);
+		break;
+	default:
+		break;
+	}
+
+	if (ret)
+		return ret;
+
+	if (mode == TOGGLING_MODE_OFF) {
+		/* mask TOGDONE interrupt */
+		ret = fusb302_i2c_set_bits(dev, FUSB_REG_MASKA,
+					   FUSB_REG_MASKA_TOGDONE);
+		if (ret)
+			return ret;
+		chip->intr_togdone = false;
+	} else {
+		/* Datasheet says vconn MUST be off when toggling */
+		if (chip->vconn_on)
+			dev_warn(dev, "Vconn is on during toggle start\n");
+		/* unmask TOGDONE interrupt */
+		ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASKA,
+					     FUSB_REG_MASKA_TOGDONE);
+		if (ret)
+			return ret;
+		chip->intr_togdone = true;
+		/* start toggling */
+		ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL2,
+					   FUSB_REG_CONTROL2_TOGGLE);
+		if (ret)
+			return ret;
+		/* during toggling, consider cc as Open */
+		chip->cc1 = TYPEC_CC_OPEN;
+		chip->cc2 = TYPEC_CC_OPEN;
+	}
+	chip->toggling_mode = mode;
+
+	return ret;
+}
+
+static const enum src_current_status cc_src_current[] = {
+	[TYPEC_CC_OPEN]		= SRC_CURRENT_DEFAULT,
+	[TYPEC_CC_RA]		= SRC_CURRENT_DEFAULT,
+	[TYPEC_CC_RD]		= SRC_CURRENT_DEFAULT,
+	[TYPEC_CC_RP_DEF]	= SRC_CURRENT_DEFAULT,
+	[TYPEC_CC_RP_1_5]	= SRC_CURRENT_MEDIUM,
+	[TYPEC_CC_RP_3_0]	= SRC_CURRENT_HIGH,
+};
+
+static int fusb302_set_cc(struct udevice *dev, enum typec_cc_status cc)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	const u8 switches0_mask = FUSB_REG_SWITCHES0_CC1_PU_EN |
+				  FUSB_REG_SWITCHES0_CC2_PU_EN |
+				  FUSB_REG_SWITCHES0_CC1_PD_EN |
+				  FUSB_REG_SWITCHES0_CC2_PD_EN;
+	u8 rd_mda, switches0_data = 0x00;
+	int ret;
+
+	switch (cc) {
+	case TYPEC_CC_OPEN:
+		break;
+	case TYPEC_CC_RD:
+		switches0_data |= FUSB_REG_SWITCHES0_CC1_PD_EN |
+				  FUSB_REG_SWITCHES0_CC2_PD_EN;
+		break;
+	case TYPEC_CC_RP_DEF:
+	case TYPEC_CC_RP_1_5:
+	case TYPEC_CC_RP_3_0:
+		switches0_data |= (chip->cc_polarity == TYPEC_POLARITY_CC1) ?
+				  FUSB_REG_SWITCHES0_CC1_PU_EN :
+				  FUSB_REG_SWITCHES0_CC2_PU_EN;
+		break;
+	default:
+		dev_err(dev, "unsupported CC value: %s\n",
+			typec_cc_status_name[cc]);
+		ret = -EINVAL;
+		goto done;
+	}
+
+	ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF);
+	if (ret) {
+		dev_err(dev, "cannot set toggling mode: %d\n", ret);
+		goto done;
+	}
+
+	ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES0,
+				     switches0_mask, switches0_data);
+	if (ret) {
+		dev_err(dev, "cannot set pull-up/-down: %d\n", ret);
+		goto done;
+	}
+	/* reset the cc status */
+	chip->cc1 = TYPEC_CC_OPEN;
+	chip->cc2 = TYPEC_CC_OPEN;
+
+	/* adjust current for SRC */
+	ret = fusb302_set_src_current(dev, cc_src_current[cc]);
+	if (ret) {
+		dev_err(dev, "cannot set src current %s: %d\n",
+			typec_cc_status_name[cc], ret);
+		goto done;
+	}
+
+	/* enable/disable interrupts, BC_LVL for SNK and COMP_CHNG for SRC */
+	switch (cc) {
+	case TYPEC_CC_RP_DEF:
+	case TYPEC_CC_RP_1_5:
+	case TYPEC_CC_RP_3_0:
+		rd_mda = rd_mda_value[cc_src_current[cc]];
+		ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda);
+		if (ret) {
+			dev_err(dev, "cannot set SRC measure value: %d\n", ret);
+			goto done;
+		}
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_MASK,
+					     FUSB_REG_MASK_BC_LVL |
+					     FUSB_REG_MASK_COMP_CHNG,
+					     FUSB_REG_MASK_BC_LVL);
+		if (ret) {
+			dev_err(dev, "cannot set SRC irq: %d\n", ret);
+			goto done;
+		}
+		chip->intr_comp_chng = true;
+		break;
+	case TYPEC_CC_RD:
+		ret = fusb302_i2c_mask_write(dev, FUSB_REG_MASK,
+					     FUSB_REG_MASK_BC_LVL |
+					     FUSB_REG_MASK_COMP_CHNG,
+					     FUSB_REG_MASK_COMP_CHNG);
+		if (ret) {
+			dev_err(dev, "cannot set SRC irq: %d\n", ret);
+			goto done;
+		}
+		chip->intr_bc_lvl = true;
+		break;
+	default:
+		break;
+	}
+done:
+	return ret;
+}
+
+static int fusb302_get_cc(struct udevice *dev, enum typec_cc_status *cc1,
+			  enum typec_cc_status *cc2)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+
+	*cc1 = chip->cc1;
+	*cc2 = chip->cc2;
+	dev_dbg(dev, "get cc1 = %s, cc2 = %s\n", typec_cc_status_name[*cc1],
+		typec_cc_status_name[*cc2]);
+
+	return 0;
+}
+
+static int fusb302_set_vconn(struct udevice *dev, bool on)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	int ret;
+	u8 switches0_data = 0x00;
+	u8 switches0_mask = FUSB_REG_SWITCHES0_VCONN_CC1 |
+			    FUSB_REG_SWITCHES0_VCONN_CC2;
+
+	if (chip->vconn_on == on) {
+		ret = 0;
+		dev_dbg(dev, "vconn is already %s\n", on ? "on" : "off");
+		goto done;
+	}
+	if (on) {
+		switches0_data = (chip->cc_polarity == TYPEC_POLARITY_CC1) ?
+				 FUSB_REG_SWITCHES0_VCONN_CC2 :
+				 FUSB_REG_SWITCHES0_VCONN_CC1;
+	}
+	ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES0,
+				     switches0_mask, switches0_data);
+	if (ret)
+		goto done;
+	dev_dbg(dev, "set vconn = %s\n", on ? "on" : "off");
+done:
+	return ret;
+}
+
+static int fusb302_set_vbus(struct udevice *dev, bool on, bool charge)
+{
+	return 0;
+}
+
+static int fusb302_pd_tx_flush(struct udevice *dev)
+{
+	return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL0,
+				    FUSB_REG_CONTROL0_TX_FLUSH);
+}
+
+static int fusb302_pd_rx_flush(struct udevice *dev)
+{
+	return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL1,
+				    FUSB_REG_CONTROL1_RX_FLUSH);
+}
+
+static int fusb302_pd_set_auto_goodcrc(struct udevice *dev, bool on)
+{
+	if (on)
+		return fusb302_i2c_set_bits(dev, FUSB_REG_SWITCHES1,
+					    FUSB_REG_SWITCHES1_AUTO_GCRC);
+	return fusb302_i2c_clear_bits(dev, FUSB_REG_SWITCHES1,
+				      FUSB_REG_SWITCHES1_AUTO_GCRC);
+}
+
+static int fusb302_pd_set_interrupts(struct udevice *dev, bool on)
+{
+	int ret;
+	u8 mask_interrupts = FUSB_REG_MASK_COLLISION;
+	u8 maska_interrupts = FUSB_REG_MASKA_RETRYFAIL |
+			      FUSB_REG_MASKA_HARDSENT |
+			      FUSB_REG_MASKA_TX_SUCCESS |
+			      FUSB_REG_MASKA_HARDRESET;
+	u8 maskb_interrupts = FUSB_REG_MASKB_GCRCSENT;
+
+	ret = on ?
+		fusb302_i2c_clear_bits(dev, FUSB_REG_MASK, mask_interrupts) :
+		fusb302_i2c_set_bits(dev, FUSB_REG_MASK, mask_interrupts);
+	if (ret)
+		return ret;
+	ret = on ?
+		fusb302_i2c_clear_bits(dev, FUSB_REG_MASKA, maska_interrupts) :
+		fusb302_i2c_set_bits(dev, FUSB_REG_MASKA, maska_interrupts);
+	if (ret)
+		return ret;
+	ret = on ?
+		fusb302_i2c_clear_bits(dev, FUSB_REG_MASKB, maskb_interrupts) :
+		fusb302_i2c_set_bits(dev, FUSB_REG_MASKB, maskb_interrupts);
+	return ret;
+}
+
+static int fusb302_set_pd_rx(struct udevice *dev, bool on)
+{
+	int ret;
+
+	ret = fusb302_pd_rx_flush(dev);
+	if (ret) {
+		dev_err(dev, "cannot flush pd rx buffer: %d\n", ret);
+		goto done;
+	}
+	ret = fusb302_pd_tx_flush(dev);
+	if (ret) {
+		dev_err(dev, "cannot flush pd tx buffer: %d\n", ret);
+		goto done;
+	}
+	ret = fusb302_pd_set_auto_goodcrc(dev, on);
+	if (ret) {
+		dev_err(dev, "cannot turn %s auto GoodCRC: %d\n",
+			on ? "on" : "off", ret);
+		goto done;
+	}
+	ret = fusb302_pd_set_interrupts(dev, on);
+	if (ret) {
+		dev_err(dev, "cannot turn %s pd interrupts: %d\n",
+			on ? "on" : "off", ret);
+		goto done;
+	}
+	dev_dbg(dev, "set pd RX %s\n", on ? "on" : "off");
+done:
+	return ret;
+}
+
+static int fusb302_set_roles(struct udevice *dev, bool attached,
+			     enum typec_role pwr, enum typec_data_role data)
+{
+	int ret;
+	u8 switches1_mask = FUSB_REG_SWITCHES1_POWERROLE |
+			    FUSB_REG_SWITCHES1_DATAROLE;
+	u8 switches1_data = 0x00;
+
+	if (pwr == TYPEC_SOURCE)
+		switches1_data |= FUSB_REG_SWITCHES1_POWERROLE;
+	if (data == TYPEC_HOST)
+		switches1_data |= FUSB_REG_SWITCHES1_DATAROLE;
+	ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES1,
+				     switches1_mask, switches1_data);
+	if (ret) {
+		dev_err(dev, "unable to set pd header %s, %s, ret=%d\n",
+			typec_role_name[pwr], typec_data_role_name[data], ret);
+		goto done;
+	}
+	dev_dbg(dev, "pd header : %s, %s\n", typec_role_name[pwr],
+		typec_data_role_name[data]);
+done:
+
+	return ret;
+}
+
+static int fusb302_start_toggling(struct udevice *dev,
+				  enum typec_port_type port_type,
+				  enum typec_cc_status cc)
+{
+	enum toggling_mode mode = TOGGLING_MODE_OFF;
+	int ret;
+
+	switch (port_type) {
+	case TYPEC_PORT_SRC:
+		mode = TOGGLING_MODE_SRC;
+		break;
+	case TYPEC_PORT_SNK:
+		mode = TOGGLING_MODE_SNK;
+		break;
+	case TYPEC_PORT_DRP:
+		mode = TOGGLING_MODE_DRP;
+		break;
+	}
+
+	ret = fusb302_set_src_current(dev, cc_src_current[cc]);
+	if (ret) {
+		dev_err(dev, "unable to set src current %s, ret=%d",
+			typec_cc_status_name[cc], ret);
+		goto done;
+	}
+	ret = fusb302_set_toggling(dev, mode);
+	if (ret) {
+		dev_err(dev, "unable to start drp toggling: %d\n", ret);
+		goto done;
+	}
+	dev_info(dev, "fusb302 start drp toggling\n");
+done:
+
+	return ret;
+}
+
+static int fusb302_pd_send_message(struct udevice *dev,
+				   const struct pd_message *msg)
+{
+	int ret;
+	/* SOP tokens */
+	u8 buf[40] = {FUSB302_TKN_SYNC1, FUSB302_TKN_SYNC1, FUSB302_TKN_SYNC1,
+		      FUSB302_TKN_SYNC2};
+	u8 pos = 4;
+	int len;
+
+	len = pd_header_cnt_le(msg->header) * 4;
+	/* plug 2 for header */
+	len += 2;
+	if (len > FUSB302_MAX_MSG_LEN) {
+		dev_err(dev, "PD message too long %d (incl. header)", len);
+		return -EINVAL;
+	}
+	/* packsym tells the FUSB302 chip that the next X bytes are payload */
+	buf[pos++] = FUSB302_TKN_PACKSYM | (len & FUSB302_MAX_MSG_LEN);
+	memcpy(&buf[pos], &msg->header, sizeof(msg->header));
+	pos += sizeof(msg->header);
+
+	len -= 2;
+	memcpy(&buf[pos], msg->payload, len);
+	pos += len;
+
+	/* CRC */
+	buf[pos++] = FUSB302_TKN_JAMCRC;
+	/* EOP */
+	buf[pos++] = FUSB302_TKN_EOP;
+	/* turn tx off after sending message */
+	buf[pos++] = FUSB302_TKN_TXOFF;
+	/* start transmission */
+	buf[pos++] = FUSB302_TKN_TXON;
+
+	ret = fusb302_i2c_block_write(dev, FUSB_REG_FIFOS, pos, buf);
+	if (ret)
+		return ret;
+	dev_dbg(dev, "Send PD message (header=0x%x len=%d)\n", msg->header, len);
+
+	return ret;
+}
+
+static int fusb302_pd_send_hardreset(struct udevice *dev)
+{
+	return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL3,
+				    FUSB_REG_CONTROL3_SEND_HARDRESET);
+}
+
+static const char * const transmit_type_name[] = {
+	[TCPC_TX_SOP]			= "SOP",
+	[TCPC_TX_SOP_PRIME]		= "SOP'",
+	[TCPC_TX_SOP_PRIME_PRIME]	= "SOP''",
+	[TCPC_TX_SOP_DEBUG_PRIME]	= "DEBUG'",
+	[TCPC_TX_SOP_DEBUG_PRIME_PRIME]	= "DEBUG''",
+	[TCPC_TX_HARD_RESET]		= "HARD_RESET",
+	[TCPC_TX_CABLE_RESET]		= "CABLE_RESET",
+	[TCPC_TX_BIST_MODE_2]		= "BIST_MODE_2",
+};
+
+static int fusb302_pd_transmit(struct udevice *dev, enum tcpm_transmit_type type,
+			       const struct pd_message *msg, unsigned int negotiated_rev)
+{
+	int ret;
+
+	switch (type) {
+	case TCPC_TX_SOP:
+		/* nRetryCount 3 in P2.0 spec, whereas 2 in PD3.0 spec */
+		ret = fusb302_enable_tx_auto_retries(dev, negotiated_rev > PD_REV20 ?
+						     FUSB_REG_CONTROL3_N_RETRIES_2 :
+						     FUSB_REG_CONTROL3_N_RETRIES_3);
+		if (ret)
+			dev_err(dev, "cannot update retry count: %d\n", ret);
+
+		ret = fusb302_pd_send_message(dev, msg);
+		if (ret)
+			dev_err(dev, "cannot send PD message: %d\n", ret);
+		break;
+	case TCPC_TX_HARD_RESET:
+		ret = fusb302_pd_send_hardreset(dev);
+		if (ret)
+			dev_err(dev, "cannot send hardreset: %d\n", ret);
+		break;
+	default:
+		dev_err(dev, "type %s not supported", transmit_type_name[type]);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static enum typec_cc_status fusb302_bc_lvl_to_cc(u8 bc_lvl)
+{
+	if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_1230_MAX)
+		return TYPEC_CC_RP_3_0;
+	if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_600_1230)
+		return TYPEC_CC_RP_1_5;
+	if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_200_600)
+		return TYPEC_CC_RP_DEF;
+	return TYPEC_CC_OPEN;
+}
+
+static void fusb302_bc_lvl_handler(struct udevice *dev)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	enum typec_cc_status cc_status;
+	u8 status0, bc_lvl;
+	int ret;
+
+	if (!chip->intr_bc_lvl) {
+		dev_err(dev, "BC_LVL interrupt is turned off, abort\n");
+		goto done;
+	}
+	ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+	if (ret)
+		goto done;
+
+	dev_dbg(dev, "BC_LVL handler, status0 = 0x%02x\n", status0);
+	if (status0 & FUSB_REG_STATUS0_ACTIVITY)
+		dev_info(dev, "CC activities detected, delay handling\n");
+	bc_lvl = status0 & FUSB_REG_STATUS0_BC_LVL_MASK;
+	cc_status = fusb302_bc_lvl_to_cc(bc_lvl);
+	if (chip->cc_polarity == TYPEC_POLARITY_CC1) {
+		if (chip->cc1 != cc_status) {
+			dev_dbg(dev, "cc1: %s -> %s\n",
+				typec_cc_status_name[chip->cc1],
+				typec_cc_status_name[cc_status]);
+			chip->cc1 = cc_status;
+			tcpm_cc_change(dev);
+		}
+	} else {
+		if (chip->cc2 != cc_status) {
+			dev_dbg(dev, "cc2: %s -> %s\n",
+				typec_cc_status_name[chip->cc2],
+				typec_cc_status_name[cc_status]);
+			chip->cc2 = cc_status;
+			tcpm_cc_change(dev);
+		}
+	}
+
+done:
+	return;
+}
+
+static int fusb302_enter_low_power_mode(struct udevice *dev,
+					bool attached, bool pd_capable)
+{
+	unsigned int reg;
+	int ret;
+
+	ret = fusb302_mask_interrupt(dev);
+	if (ret)
+		return ret;
+	if (attached && pd_capable)
+		reg = FUSB_REG_POWER_PWR_MEDIUM;
+	else if (attached)
+		reg = FUSB_REG_POWER_PWR_LOW;
+	else
+		reg = 0;
+
+	return fusb302_set_power_mode(dev, reg);
+}
+
+static const char * const cc_polarity_name[] = {
+	[TYPEC_POLARITY_CC1]	= "Polarity_CC1",
+	[TYPEC_POLARITY_CC2]	= "Polarity_CC2",
+};
+
+static int fusb302_set_cc_polarity_and_pull(struct udevice *dev,
+					    enum typec_cc_polarity cc_polarity,
+					    bool pull_up, bool pull_down)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	int ret;
+	u8 switches0_data = 0x00;
+	u8 switches1_mask = FUSB_REG_SWITCHES1_TXCC1_EN |
+			    FUSB_REG_SWITCHES1_TXCC2_EN;
+	u8 switches1_data = 0x00;
+
+	if (pull_down)
+		switches0_data |= FUSB_REG_SWITCHES0_CC1_PD_EN |
+				  FUSB_REG_SWITCHES0_CC2_PD_EN;
+
+	if (cc_polarity == TYPEC_POLARITY_CC1) {
+		switches0_data |= FUSB_REG_SWITCHES0_MEAS_CC1;
+		if (chip->vconn_on)
+			switches0_data |= FUSB_REG_SWITCHES0_VCONN_CC2;
+		if (pull_up)
+			switches0_data |= FUSB_REG_SWITCHES0_CC1_PU_EN;
+		switches1_data = FUSB_REG_SWITCHES1_TXCC1_EN;
+	} else {
+		switches0_data |= FUSB_REG_SWITCHES0_MEAS_CC2;
+		if (chip->vconn_on)
+			switches0_data |= FUSB_REG_SWITCHES0_VCONN_CC1;
+		if (pull_up)
+			switches0_data |= FUSB_REG_SWITCHES0_CC2_PU_EN;
+		switches1_data = FUSB_REG_SWITCHES1_TXCC2_EN;
+	}
+	ret = fusb302_i2c_write(dev, FUSB_REG_SWITCHES0, switches0_data);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES1,
+				     switches1_mask, switches1_data);
+	if (ret)
+		return ret;
+	chip->cc_polarity = cc_polarity;
+
+	return ret;
+}
+
+static int fusb302_handle_togdone_snk(struct udevice *dev,
+				      u8 togdone_result)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	int ret;
+	u8 status0;
+	u8 bc_lvl;
+	enum typec_cc_polarity cc_polarity;
+	enum typec_cc_status cc_status_active, cc1, cc2;
+
+	/* set polarity and pull_up, pull_down */
+	cc_polarity = (togdone_result == FUSB_REG_STATUS1A_TOGSS_SNK1) ?
+		      TYPEC_POLARITY_CC1 : TYPEC_POLARITY_CC2;
+	ret = fusb302_set_cc_polarity_and_pull(dev, cc_polarity, false, true);
+	if (ret) {
+		dev_err(dev, "cannot set cc polarity %s, ret = %d\n",
+			cc_polarity_name[cc_polarity], ret);
+		return ret;
+	}
+	/* fusb302_set_cc_polarity() has set the correct measure block */
+	ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+	if (ret < 0)
+		return ret;
+	bc_lvl = status0 & FUSB_REG_STATUS0_BC_LVL_MASK;
+	cc_status_active = fusb302_bc_lvl_to_cc(bc_lvl);
+	/* restart toggling if the cc status on the active line is OPEN */
+	if (cc_status_active == TYPEC_CC_OPEN) {
+		dev_info(dev, "restart toggling as CC_OPEN detected\n");
+		ret = fusb302_set_toggling(dev, chip->toggling_mode);
+		return ret;
+	}
+	/* update tcpm with the new cc value */
+	cc1 = (cc_polarity == TYPEC_POLARITY_CC1) ?
+	      cc_status_active : TYPEC_CC_OPEN;
+	cc2 = (cc_polarity == TYPEC_POLARITY_CC2) ?
+	      cc_status_active : TYPEC_CC_OPEN;
+	if (chip->cc1 != cc1 || chip->cc2 != cc2) {
+		chip->cc1 = cc1;
+		chip->cc2 = cc2;
+		tcpm_cc_change(dev);
+	}
+	/* turn off toggling */
+	ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF);
+	if (ret) {
+		dev_err(dev, "cannot set toggling mode off, ret=%d\n", ret);
+		return ret;
+	}
+	/* unmask bc_lvl interrupt */
+	ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASK, FUSB_REG_MASK_BC_LVL);
+	if (ret) {
+		dev_err(dev, "cannot unmask bc_lcl irq, ret=%d\n", ret);
+		return ret;
+	}
+	chip->intr_bc_lvl = true;
+	dev_dbg(dev, "detected cc1=%s, cc2=%s\n",
+		typec_cc_status_name[cc1],
+		typec_cc_status_name[cc2]);
+
+	return ret;
+}
+
+/* On error returns < 0, otherwise a typec_cc_status value */
+static int fusb302_get_src_cc_status(struct udevice *dev,
+				     enum typec_cc_polarity cc_polarity,
+				     enum typec_cc_status *cc)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	u8 ra_mda = ra_mda_value[chip->src_current_status];
+	u8 rd_mda = rd_mda_value[chip->src_current_status];
+	u8 switches0_data, status0;
+	int ret;
+
+	/* Step 1: Set switches so that we measure the right CC pin */
+	switches0_data = (cc_polarity == TYPEC_POLARITY_CC1) ?
+		FUSB_REG_SWITCHES0_CC1_PU_EN | FUSB_REG_SWITCHES0_MEAS_CC1 :
+		FUSB_REG_SWITCHES0_CC2_PU_EN | FUSB_REG_SWITCHES0_MEAS_CC2;
+	ret = fusb302_i2c_write(dev, FUSB_REG_SWITCHES0, switches0_data);
+	if (ret < 0)
+		return ret;
+
+	fusb302_i2c_read(dev, FUSB_REG_SWITCHES0, &status0);
+	dev_dbg(dev, "get_src_cc_status switches: 0x%0x", status0);
+
+	/* Step 2: Set compararator volt to differentiate between Open and Rd */
+	ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda);
+	if (ret)
+		return ret;
+
+	udelay(100);
+	ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+	if (ret)
+		return ret;
+
+	dev_dbg(dev, "get_src_cc_status rd_mda status0: 0x%0x", status0);
+	if (status0 & FUSB_REG_STATUS0_COMP) {
+		*cc = TYPEC_CC_OPEN;
+		return 0;
+	}
+
+	/* Step 3: Set compararator input to differentiate between Rd and Ra. */
+	ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, ra_mda);
+	if (ret)
+		return ret;
+
+	udelay(100);
+	ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+	if (ret)
+		return ret;
+
+	dev_dbg(dev, "get_src_cc_status ra_mda status0: 0x%0x", status0);
+	if (status0 & FUSB_REG_STATUS0_COMP)
+		*cc = TYPEC_CC_RD;
+	else
+		*cc = TYPEC_CC_RA;
+
+	return 0;
+}
+
+static int fusb302_handle_togdone_src(struct udevice *dev,
+				      u8 togdone_result)
+{
+	/*
+	 * - set polarity (measure cc, vconn, tx)
+	 * - set pull_up, pull_down
+	 * - set cc1, cc2, and update to tcpm state machine
+	 * - set I_COMP interrupt on
+	 */
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	u8 rd_mda = rd_mda_value[chip->src_current_status];
+	enum toggling_mode toggling_mode = chip->toggling_mode;
+	enum typec_cc_polarity cc_polarity;
+	enum typec_cc_status cc1, cc2;
+	int ret;
+
+	/*
+	 * The toggle-engine will stop in a src state if it sees either Ra or
+	 * Rd. Determine the status for both CC pins, starting with the one
+	 * where toggling stopped, as that is where the switches point now.
+	 */
+	if (togdone_result == FUSB_REG_STATUS1A_TOGSS_SRC1)
+		ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC1, &cc1);
+	else
+		ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC2, &cc2);
+	if (ret)
+		return ret;
+	/* we must turn off toggling before we can measure the other pin */
+	ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF);
+	if (ret) {
+		dev_err(dev, "cannot set toggling mode off, ret=%d\n", ret);
+		return ret;
+	}
+	/* get the status of the other pin */
+	if (togdone_result == FUSB_REG_STATUS1A_TOGSS_SRC1)
+		ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC2, &cc2);
+	else
+		ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC1, &cc1);
+	if (ret)
+		return ret;
+
+	/* determine polarity based on the status of both pins */
+	if (cc1 == TYPEC_CC_RD && (cc2 == TYPEC_CC_OPEN || cc2 == TYPEC_CC_RA)) {
+		cc_polarity = TYPEC_POLARITY_CC1;
+	} else if (cc2 == TYPEC_CC_RD &&
+		    (cc1 == TYPEC_CC_OPEN || cc1 == TYPEC_CC_RA)) {
+		cc_polarity = TYPEC_POLARITY_CC2;
+	} else {
+		dev_err(dev, "unexpected CC status cc1=%s, cc2=%s, restarting toggling\n",
+			typec_cc_status_name[cc1],
+			typec_cc_status_name[cc2]);
+		return fusb302_set_toggling(dev, toggling_mode);
+	}
+	/* set polarity and pull_up, pull_down */
+	ret = fusb302_set_cc_polarity_and_pull(dev, cc_polarity, true, false);
+	if (ret < 0) {
+		dev_err(dev, "cannot set cc polarity %s, ret=%d\n",
+			cc_polarity_name[cc_polarity], ret);
+		return ret;
+	}
+	/* update tcpm with the new cc value */
+	if (chip->cc1 != cc1 || chip->cc2 != cc2) {
+		chip->cc1 = cc1;
+		chip->cc2 = cc2;
+		tcpm_cc_change(dev);
+	}
+	/* set MDAC to Rd threshold, and unmask I_COMP for unplug detection */
+	ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda);
+	if (ret)
+		return ret;
+	/* unmask comp_chng interrupt */
+	ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASK,
+				     FUSB_REG_MASK_COMP_CHNG);
+	if (ret) {
+		dev_err(dev, "cannot unmask comp_chng irq, ret=%d\n", ret);
+		return ret;
+	}
+	chip->intr_comp_chng = true;
+	dev_dbg(dev, "detected cc1=%s, cc2=%s\n",
+		typec_cc_status_name[cc1],
+		typec_cc_status_name[cc2]);
+
+	return ret;
+}
+
+static int fusb302_handle_togdone(struct udevice *dev)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	u8 togdone_result, status1a;
+	int ret;
+
+	ret = fusb302_i2c_read(dev, FUSB_REG_STATUS1A, &status1a);
+	if (ret < 0)
+		return ret;
+	togdone_result = (status1a >> FUSB_REG_STATUS1A_TOGSS_POS) &
+			 FUSB_REG_STATUS1A_TOGSS_MASK;
+	switch (togdone_result) {
+	case FUSB_REG_STATUS1A_TOGSS_SNK1:
+	case FUSB_REG_STATUS1A_TOGSS_SNK2:
+		return fusb302_handle_togdone_snk(dev, togdone_result);
+	case FUSB_REG_STATUS1A_TOGSS_SRC1:
+	case FUSB_REG_STATUS1A_TOGSS_SRC2:
+		return fusb302_handle_togdone_src(dev, togdone_result);
+	case FUSB_REG_STATUS1A_TOGSS_AA:
+		/* doesn't support */
+		dev_err(dev, "AudioAccessory not supported\n");
+		fusb302_set_toggling(dev, chip->toggling_mode);
+		break;
+	default:
+		dev_err(dev, "TOGDONE with an invalid state: %d\n",
+			togdone_result);
+		fusb302_set_toggling(dev, chip->toggling_mode);
+		break;
+	}
+	return ret;
+}
+
+static int fusb302_pd_reset(struct udevice *dev)
+{
+	return fusb302_i2c_set_bits(dev, FUSB_REG_RESET,
+				    FUSB_REG_RESET_PD_RESET);
+}
+
+static int fusb302_pd_read_message(struct udevice *dev,
+				   struct pd_message *msg)
+{
+	int len, ret;
+	u8 crc[4];
+	u8 token;
+
+	/* first SOP token */
+	ret = fusb302_i2c_read(dev, FUSB_REG_FIFOS, &token);
+	if (ret)
+		return ret;
+	ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, 2,
+				     (u8 *)&msg->header);
+	if (ret)
+		return ret;
+	len = pd_header_cnt_le(msg->header) * 4;
+	/* add 4 to length to include the CRC */
+	if (len > PD_MAX_PAYLOAD * 4) {
+		dev_err(dev, "PD message too long %d\n", len);
+		return -EINVAL;
+	}
+	if (len > 0) {
+		ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, len,
+					     (u8 *)msg->payload);
+		if (ret)
+			return ret;
+	}
+	/* another 4 bytes to read CRC out */
+	ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, 4, crc);
+	if (ret)
+		return ret;
+	dev_dbg(dev, "Received PD message (header=0x%x len=%d)\n", msg->header, len);
+
+	/*
+	 * Check if we've read off a GoodCRC message. If so then indicate to
+	 * TCPM that the previous transmission has completed. Otherwise we pass
+	 * the received message over to TCPM for processing.
+	 *
+	 * We make this check here instead of basing the reporting decision on
+	 * the IRQ event type, as it's possible for the chip to report the
+	 * TX_SUCCESS and GCRCSENT events out of order on occasion, so we need
+	 * to check the message type to ensure correct reporting to TCPM.
+	 */
+	if (!len && (pd_header_type_le(msg->header) == PD_CTRL_GOOD_CRC))
+		tcpm_pd_transmit_complete(dev, TCPC_TX_SUCCESS);
+	else
+		tcpm_pd_receive(dev, msg);
+
+	return ret;
+}
+
+static void fusb302_interrupt_handle(struct udevice *dev)
+{
+	struct fusb302_chip *chip = dev_get_priv(dev);
+	u8 interrupt;
+	u8 interrupta;
+	u8 interruptb;
+	u8 status0;
+	bool vbus_present;
+	bool comp_result;
+	bool intr_togdone;
+	bool intr_bc_lvl;
+	bool intr_comp_chng;
+	struct pd_message pd_msg;
+	int ret;
+
+	/* grab a snapshot of intr flags */
+	intr_togdone = chip->intr_togdone;
+	intr_bc_lvl = chip->intr_bc_lvl;
+	intr_comp_chng = chip->intr_comp_chng;
+
+	ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPT, &interrupt);
+	if (ret)
+		return;
+	ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPTA, &interrupta);
+	if (ret)
+		return;
+	ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPTB, &interruptb);
+	if (ret)
+		return;
+	ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+	if (ret)
+		return;
+
+	/*
+	 * Since we are polling the IRQs, avoid printing messages when there
+	 * no interrupts at all to avoid spamming the log.
+	 */
+	if (interrupt != 0 || interrupta != 0 || interruptb != 0)
+		dev_dbg(dev, "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x, status0: 0x%02x\n",
+			interrupt, interrupta, interruptb, status0);
+
+	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
+		dev_dbg(dev, "IRQ: VBUS_OK, vbus=%s\n",
+			vbus_present ? "On" : "Off");
+		if (vbus_present != chip->vbus_present) {
+			chip->vbus_present = vbus_present;
+			tcpm_vbus_change(dev);
+		}
+	}
+
+	if ((interrupta & FUSB_REG_INTERRUPTA_TOGDONE) && intr_togdone) {
+		dev_dbg(dev, "IRQ: TOGDONE\n");
+		ret = fusb302_handle_togdone(dev);
+		if (ret) {
+			dev_err(dev, "handle togdone error: %d\n", ret);
+			return;
+		}
+	}
+
+	if ((interrupt & FUSB_REG_INTERRUPT_BC_LVL) && intr_bc_lvl) {
+		dev_dbg(dev, "IRQ: BC_LVL, handler pending\n");
+		fusb302_bc_lvl_handler(dev);
+	}
+
+	if ((interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) && intr_comp_chng) {
+		comp_result = !!(status0 & FUSB_REG_STATUS0_COMP);
+		dev_dbg(dev, "IRQ: COMP_CHNG, comp=%s\n",
+			comp_result ? "true" : "false");
+		if (comp_result) {
+			/* cc level > Rd_threshold, detach */
+			chip->cc1 = TYPEC_CC_OPEN;
+			chip->cc2 = TYPEC_CC_OPEN;
+			tcpm_cc_change(dev);
+		}
+	}
+
+	if (interrupt & FUSB_REG_INTERRUPT_COLLISION) {
+		dev_dbg(dev, "IRQ: PD collision\n");
+		tcpm_pd_transmit_complete(dev, TCPC_TX_FAILED);
+	}
+
+	if (interrupta & FUSB_REG_INTERRUPTA_RETRYFAIL) {
+		dev_dbg(dev, "IRQ: PD retry failed\n");
+		tcpm_pd_transmit_complete(dev, TCPC_TX_FAILED);
+	}
+
+	if (interrupta & FUSB_REG_INTERRUPTA_HARDSENT) {
+		dev_dbg(dev, "IRQ: PD hardreset sent\n");
+		ret = fusb302_pd_reset(dev);
+		if (ret) {
+			dev_err(dev, "cannot PD reset, ret=%d\n", ret);
+			return;
+		}
+		tcpm_pd_transmit_complete(dev, TCPC_TX_SUCCESS);
+	}
+
+	if (interrupta & FUSB_REG_INTERRUPTA_TX_SUCCESS) {
+		dev_dbg(dev, "IRQ: PD tx success\n");
+		ret = fusb302_pd_read_message(dev, &pd_msg);
+		if (ret) {
+			dev_err(dev, "cannot read in PD message, ret=%d\n", ret);
+			return;
+		}
+	}
+
+	if (interrupta & FUSB_REG_INTERRUPTA_HARDRESET) {
+		dev_dbg(dev, "IRQ: PD received hardreset\n");
+		ret = fusb302_pd_reset(dev);
+		if (ret) {
+			dev_err(dev, "cannot PD reset, ret=%d\n", ret);
+			return;
+		}
+		tcpm_pd_hard_reset(dev);
+	}
+
+	if (interruptb & FUSB_REG_INTERRUPTB_GCRCSENT) {
+		dev_dbg(dev, "IRQ: PD sent good CRC\n");
+		ret = fusb302_pd_read_message(dev, &pd_msg);
+		if (ret) {
+			dev_err(dev, "cannot read in PD message, ret=%d\n", ret);
+			return;
+		}
+	}
+}
+
+static void fusb302_poll_event(struct udevice *dev)
+{
+	fusb302_interrupt_handle(dev);
+}
+
+static int fusb302_get_connector_node(struct udevice *dev, ofnode *connector_node)
+{
+	*connector_node = dev_read_subnode(dev, "connector");
+	if (!ofnode_valid(*connector_node)) {
+		dev_err(dev, "'connector' node is not found\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static struct dm_tcpm_ops fusb302_ops = {
+	.get_connector_node = fusb302_get_connector_node,
+	.init = fusb302_init,
+	.get_vbus = fusb302_get_vbus,
+	.set_cc = fusb302_set_cc,
+	.get_cc = fusb302_get_cc,
+	.set_vconn = fusb302_set_vconn,
+	.set_vbus = fusb302_set_vbus,
+	.set_pd_rx = fusb302_set_pd_rx,
+	.set_roles = fusb302_set_roles,
+	.start_toggling = fusb302_start_toggling,
+	.pd_transmit = fusb302_pd_transmit,
+	.poll_event = fusb302_poll_event,
+	.enter_low_power_mode = fusb302_enter_low_power_mode,
+};
+
+static const struct udevice_id fusb302_ids[] = {
+	{ .compatible = "fcs,fusb302" },
+	{ }
+};
+
+U_BOOT_DRIVER(fusb302) = {
+	.name = "fusb302",
+	.id = UCLASS_TCPM,
+	.of_match = fusb302_ids,
+	.ops = &fusb302_ops,
+	.priv_auto = sizeof(struct fusb302_chip),
+};
diff --git a/drivers/usb/tcpm/fusb302_reg.h b/drivers/usb/tcpm/fusb302_reg.h
new file mode 100644
index 0000000..edc0e4b0
--- /dev/null
+++ b/drivers/usb/tcpm/fusb302_reg.h
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016-2017 Google, Inc
+ *
+ * Fairchild FUSB302 Type-C Chip Driver
+ */
+
+#ifndef FUSB302_REG_H
+#define FUSB302_REG_H
+
+#define FUSB_REG_DEVICE_ID			0x01
+#define FUSB_REG_SWITCHES0			0x02
+#define FUSB_REG_SWITCHES0_CC2_PU_EN		BIT(7)
+#define FUSB_REG_SWITCHES0_CC1_PU_EN		BIT(6)
+#define FUSB_REG_SWITCHES0_VCONN_CC2		BIT(5)
+#define FUSB_REG_SWITCHES0_VCONN_CC1		BIT(4)
+#define FUSB_REG_SWITCHES0_MEAS_CC2		BIT(3)
+#define FUSB_REG_SWITCHES0_MEAS_CC1		BIT(2)
+#define FUSB_REG_SWITCHES0_CC2_PD_EN		BIT(1)
+#define FUSB_REG_SWITCHES0_CC1_PD_EN		BIT(0)
+#define FUSB_REG_SWITCHES1			0x03
+#define FUSB_REG_SWITCHES1_POWERROLE		BIT(7)
+#define FUSB_REG_SWITCHES1_SPECREV1		BIT(6)
+#define FUSB_REG_SWITCHES1_SPECREV0		BIT(5)
+#define FUSB_REG_SWITCHES1_DATAROLE		BIT(4)
+#define FUSB_REG_SWITCHES1_AUTO_GCRC		BIT(2)
+#define FUSB_REG_SWITCHES1_TXCC2_EN		BIT(1)
+#define FUSB_REG_SWITCHES1_TXCC1_EN		BIT(0)
+#define FUSB_REG_MEASURE			0x04
+#define FUSB_REG_MEASURE_MDAC5			BIT(7)
+#define FUSB_REG_MEASURE_MDAC4			BIT(6)
+#define FUSB_REG_MEASURE_MDAC3			BIT(5)
+#define FUSB_REG_MEASURE_MDAC2			BIT(4)
+#define FUSB_REG_MEASURE_MDAC1			BIT(3)
+#define FUSB_REG_MEASURE_MDAC0			BIT(2)
+#define FUSB_REG_MEASURE_VBUS			BIT(1)
+#define FUSB_REG_MEASURE_XXXX5			BIT(0)
+#define FUSB_REG_CONTROL0			0x06
+#define FUSB_REG_CONTROL0_TX_FLUSH		BIT(6)
+#define FUSB_REG_CONTROL0_INT_MASK		BIT(5)
+#define FUSB_REG_CONTROL0_HOST_CUR_MASK		(0xC)
+#define FUSB_REG_CONTROL0_HOST_CUR_HIGH		(0xC)
+#define FUSB_REG_CONTROL0_HOST_CUR_MED		(0x8)
+#define FUSB_REG_CONTROL0_HOST_CUR_DEF		(0x4)
+#define FUSB_REG_CONTROL0_TX_START		BIT(0)
+#define FUSB_REG_CONTROL1			0x07
+#define FUSB_REG_CONTROL1_ENSOP2DB		BIT(6)
+#define FUSB_REG_CONTROL1_ENSOP1DB		BIT(5)
+#define FUSB_REG_CONTROL1_BIST_MODE2		BIT(4)
+#define FUSB_REG_CONTROL1_RX_FLUSH		BIT(2)
+#define FUSB_REG_CONTROL1_ENSOP2		BIT(1)
+#define FUSB_REG_CONTROL1_ENSOP1		BIT(0)
+#define FUSB_REG_CONTROL2			0x08
+#define FUSB_REG_CONTROL2_MODE			BIT(1)
+#define FUSB_REG_CONTROL2_MODE_MASK		(0x6)
+#define FUSB_REG_CONTROL2_MODE_DFP		(0x6)
+#define FUSB_REG_CONTROL2_MODE_UFP		(0x4)
+#define FUSB_REG_CONTROL2_MODE_DRP		(0x2)
+#define FUSB_REG_CONTROL2_MODE_NONE		(0x0)
+#define FUSB_REG_CONTROL2_TOGGLE		BIT(0)
+#define FUSB_REG_CONTROL3			0x09
+#define FUSB_REG_CONTROL3_SEND_HARDRESET	BIT(6)
+#define FUSB_REG_CONTROL3_BIST_TMODE		BIT(5)	/* 302B Only */
+#define FUSB_REG_CONTROL3_AUTO_HARDRESET	BIT(4)
+#define FUSB_REG_CONTROL3_AUTO_SOFTRESET	BIT(3)
+#define FUSB_REG_CONTROL3_N_RETRIES		BIT(1)
+#define FUSB_REG_CONTROL3_N_RETRIES_MASK	(0x6)
+#define FUSB_REG_CONTROL3_N_RETRIES_3		(0x6)
+#define FUSB_REG_CONTROL3_N_RETRIES_2		(0x4)
+#define FUSB_REG_CONTROL3_N_RETRIES_1		(0x2)
+#define FUSB_REG_CONTROL3_AUTO_RETRY		BIT(0)
+#define FUSB_REG_MASK				0x0A
+#define FUSB_REG_MASK_VBUSOK			BIT(7)
+#define FUSB_REG_MASK_ACTIVITY			BIT(6)
+#define FUSB_REG_MASK_COMP_CHNG			BIT(5)
+#define FUSB_REG_MASK_CRC_CHK			BIT(4)
+#define FUSB_REG_MASK_ALERT			BIT(3)
+#define FUSB_REG_MASK_WAKE			BIT(2)
+#define FUSB_REG_MASK_COLLISION			BIT(1)
+#define FUSB_REG_MASK_BC_LVL			BIT(0)
+#define FUSB_REG_POWER				0x0B
+#define FUSB_REG_POWER_PWR			BIT(0)
+#define FUSB_REG_POWER_PWR_LOW			0x1
+#define FUSB_REG_POWER_PWR_MEDIUM		0x3
+#define FUSB_REG_POWER_PWR_HIGH			0x7
+#define FUSB_REG_POWER_PWR_ALL			0xF
+#define FUSB_REG_RESET				0x0C
+#define FUSB_REG_RESET_PD_RESET			BIT(1)
+#define FUSB_REG_RESET_SW_RESET			BIT(0)
+#define FUSB_REG_MASKA				0x0E
+#define FUSB_REG_MASKA_OCP_TEMP			BIT(7)
+#define FUSB_REG_MASKA_TOGDONE			BIT(6)
+#define FUSB_REG_MASKA_SOFTFAIL			BIT(5)
+#define FUSB_REG_MASKA_RETRYFAIL		BIT(4)
+#define FUSB_REG_MASKA_HARDSENT			BIT(3)
+#define FUSB_REG_MASKA_TX_SUCCESS		BIT(2)
+#define FUSB_REG_MASKA_SOFTRESET		BIT(1)
+#define FUSB_REG_MASKA_HARDRESET		BIT(0)
+#define FUSB_REG_MASKB				0x0F
+#define FUSB_REG_MASKB_GCRCSENT			BIT(0)
+#define FUSB_REG_STATUS0A			0x3C
+#define FUSB_REG_STATUS0A_SOFTFAIL		BIT(5)
+#define FUSB_REG_STATUS0A_RETRYFAIL		BIT(4)
+#define FUSB_REG_STATUS0A_POWER			BIT(2)
+#define FUSB_REG_STATUS0A_RX_SOFT_RESET		BIT(1)
+#define FUSB_REG_STATUS0A_RX_HARD_RESET		BIT(0)
+#define FUSB_REG_STATUS1A			0x3D
+#define FUSB_REG_STATUS1A_TOGSS			BIT(3)
+#define FUSB_REG_STATUS1A_TOGSS_RUNNING		0x0
+#define FUSB_REG_STATUS1A_TOGSS_SRC1		0x1
+#define FUSB_REG_STATUS1A_TOGSS_SRC2		0x2
+#define FUSB_REG_STATUS1A_TOGSS_SNK1		0x5
+#define FUSB_REG_STATUS1A_TOGSS_SNK2		0x6
+#define FUSB_REG_STATUS1A_TOGSS_AA		0x7
+#define FUSB_REG_STATUS1A_TOGSS_POS		(3)
+#define FUSB_REG_STATUS1A_TOGSS_MASK		(0x7)
+#define FUSB_REG_STATUS1A_RXSOP2DB		BIT(2)
+#define FUSB_REG_STATUS1A_RXSOP1DB		BIT(1)
+#define FUSB_REG_STATUS1A_RXSOP			BIT(0)
+#define FUSB_REG_INTERRUPTA			0x3E
+#define FUSB_REG_INTERRUPTA_OCP_TEMP		BIT(7)
+#define FUSB_REG_INTERRUPTA_TOGDONE		BIT(6)
+#define FUSB_REG_INTERRUPTA_SOFTFAIL		BIT(5)
+#define FUSB_REG_INTERRUPTA_RETRYFAIL		BIT(4)
+#define FUSB_REG_INTERRUPTA_HARDSENT		BIT(3)
+#define FUSB_REG_INTERRUPTA_TX_SUCCESS		BIT(2)
+#define FUSB_REG_INTERRUPTA_SOFTRESET		BIT(1)
+#define FUSB_REG_INTERRUPTA_HARDRESET		BIT(0)
+#define FUSB_REG_INTERRUPTB			0x3F
+#define FUSB_REG_INTERRUPTB_GCRCSENT		BIT(0)
+#define FUSB_REG_STATUS0			0x40
+#define FUSB_REG_STATUS0_VBUSOK			BIT(7)
+#define FUSB_REG_STATUS0_ACTIVITY		BIT(6)
+#define FUSB_REG_STATUS0_COMP			BIT(5)
+#define FUSB_REG_STATUS0_CRC_CHK		BIT(4)
+#define FUSB_REG_STATUS0_ALERT			BIT(3)
+#define FUSB_REG_STATUS0_WAKE			BIT(2)
+#define FUSB_REG_STATUS0_BC_LVL_MASK		0x03
+#define FUSB_REG_STATUS0_BC_LVL_0_200		0x0
+#define FUSB_REG_STATUS0_BC_LVL_200_600		0x1
+#define FUSB_REG_STATUS0_BC_LVL_600_1230	0x2
+#define FUSB_REG_STATUS0_BC_LVL_1230_MAX	0x3
+#define FUSB_REG_STATUS0_BC_LVL1		BIT(1)
+#define FUSB_REG_STATUS0_BC_LVL0		BIT(0)
+#define FUSB_REG_STATUS1			0x41
+#define FUSB_REG_STATUS1_RXSOP2			BIT(7)
+#define FUSB_REG_STATUS1_RXSOP1			BIT(6)
+#define FUSB_REG_STATUS1_RX_EMPTY		BIT(5)
+#define FUSB_REG_STATUS1_RX_FULL		BIT(4)
+#define FUSB_REG_STATUS1_TX_EMPTY		BIT(3)
+#define FUSB_REG_STATUS1_TX_FULL		BIT(2)
+#define FUSB_REG_INTERRUPT			0x42
+#define FUSB_REG_INTERRUPT_VBUSOK		BIT(7)
+#define FUSB_REG_INTERRUPT_ACTIVITY		BIT(6)
+#define FUSB_REG_INTERRUPT_COMP_CHNG		BIT(5)
+#define FUSB_REG_INTERRUPT_CRC_CHK		BIT(4)
+#define FUSB_REG_INTERRUPT_ALERT		BIT(3)
+#define FUSB_REG_INTERRUPT_WAKE			BIT(2)
+#define FUSB_REG_INTERRUPT_COLLISION		BIT(1)
+#define FUSB_REG_INTERRUPT_BC_LVL		BIT(0)
+#define FUSB_REG_FIFOS				0x43
+
+/* Tokens defined for the FUSB302 TX FIFO */
+enum fusb302_txfifo_tokens {
+	FUSB302_TKN_TXON = 0xA1,
+	FUSB302_TKN_SYNC1 = 0x12,
+	FUSB302_TKN_SYNC2 = 0x13,
+	FUSB302_TKN_SYNC3 = 0x1B,
+	FUSB302_TKN_RST1 = 0x15,
+	FUSB302_TKN_RST2 = 0x16,
+	FUSB302_TKN_PACKSYM = 0x80,
+	FUSB302_TKN_JAMCRC = 0xFF,
+	FUSB302_TKN_EOP = 0x14,
+	FUSB302_TKN_TXOFF = 0xFE,
+};
+
+#endif
diff --git a/drivers/usb/tcpm/tcpm-internal.h b/drivers/usb/tcpm/tcpm-internal.h
new file mode 100644
index 0000000..5614420
--- /dev/null
+++ b/drivers/usb/tcpm/tcpm-internal.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ * Copyright 2024 Collabora
+ */
+
+#ifndef __LINUX_USB_TCPM_INTERNAL_H
+#define __LINUX_USB_TCPM_INTERNAL_H
+
+#define FOREACH_TCPM_STATE(S)			\
+	S(INVALID_STATE),			\
+	S(TOGGLING),			\
+	S(SRC_UNATTACHED),			\
+	S(SRC_ATTACH_WAIT),			\
+	S(SRC_ATTACHED),			\
+	S(SRC_STARTUP),				\
+	S(SRC_SEND_CAPABILITIES),		\
+	S(SRC_SEND_CAPABILITIES_TIMEOUT),	\
+	S(SRC_NEGOTIATE_CAPABILITIES),		\
+	S(SRC_TRANSITION_SUPPLY),		\
+	S(SRC_READY),				\
+	S(SRC_WAIT_NEW_CAPABILITIES),		\
+						\
+	S(SNK_UNATTACHED),			\
+	S(SNK_ATTACH_WAIT),			\
+	S(SNK_DEBOUNCED),			\
+	S(SNK_ATTACHED),			\
+	S(SNK_STARTUP),				\
+	S(SNK_DISCOVERY),			\
+	S(SNK_DISCOVERY_DEBOUNCE),		\
+	S(SNK_DISCOVERY_DEBOUNCE_DONE),		\
+	S(SNK_WAIT_CAPABILITIES),		\
+	S(SNK_NEGOTIATE_CAPABILITIES),		\
+	S(SNK_TRANSITION_SINK),			\
+	S(SNK_TRANSITION_SINK_VBUS),		\
+	S(SNK_READY),				\
+						\
+	S(HARD_RESET_SEND),			\
+	S(HARD_RESET_START),			\
+	S(SRC_HARD_RESET_VBUS_OFF),		\
+	S(SRC_HARD_RESET_VBUS_ON),		\
+	S(SNK_HARD_RESET_SINK_OFF),		\
+	S(SNK_HARD_RESET_WAIT_VBUS),		\
+	S(SNK_HARD_RESET_SINK_ON),		\
+						\
+	S(SOFT_RESET),				\
+	S(SOFT_RESET_SEND),			\
+						\
+	S(DR_SWAP_ACCEPT),			\
+	S(DR_SWAP_CHANGE_DR),			\
+						\
+	S(ERROR_RECOVERY),			\
+	S(PORT_RESET),				\
+	S(PORT_RESET_WAIT_OFF)
+
+#define GENERATE_TCPM_ENUM(e)		e
+#define GENERATE_TCPM_STRING(s)		#s
+#define TCPM_POLL_EVENT_TIME_OUT	2000
+
+enum tcpm_state {
+	FOREACH_TCPM_STATE(GENERATE_TCPM_ENUM)
+};
+
+enum pd_msg_request {
+	PD_MSG_NONE = 0,
+	PD_MSG_CTRL_REJECT,
+	PD_MSG_CTRL_WAIT,
+	PD_MSG_CTRL_NOT_SUPP,
+	PD_MSG_DATA_SINK_CAP,
+	PD_MSG_DATA_SOURCE_CAP,
+};
+
+struct tcpm_port {
+	enum typec_port_type typec_type;
+	int typec_prefer_role;
+
+	enum typec_role vconn_role;
+	enum typec_role pwr_role;
+	enum typec_data_role data_role;
+
+	struct typec_partner *partner;
+
+	enum typec_cc_status cc_req;
+	enum typec_cc_status cc1;
+	enum typec_cc_status cc2;
+	enum typec_cc_polarity polarity;
+
+	bool attached;
+	bool connected;
+	int poll_event_cnt;
+	enum typec_port_type port_type;
+
+	/*
+	 * Set to true when vbus is greater than VSAFE5V min.
+	 * Set to false when vbus falls below vSinkDisconnect max threshold.
+	 */
+	bool vbus_present;
+
+	/*
+	 * Set to true when vbus is less than VSAFE0V max.
+	 * Set to false when vbus is greater than VSAFE0V max.
+	 */
+	bool vbus_vsafe0v;
+
+	bool vbus_never_low;
+	bool vbus_source;
+	bool vbus_charge;
+
+	int try_role;
+
+	enum pd_msg_request queued_message;
+
+	enum tcpm_state enter_state;
+	enum tcpm_state prev_state;
+	enum tcpm_state state;
+	enum tcpm_state delayed_state;
+	unsigned long delay_ms;
+
+	bool state_machine_running;
+
+	bool tx_complete;
+	enum tcpm_transmit_status tx_status;
+
+	unsigned int negotiated_rev;
+	unsigned int message_id;
+	unsigned int caps_count;
+	unsigned int hard_reset_count;
+	bool pd_capable;
+	bool explicit_contract;
+	unsigned int rx_msgid;
+
+	/* Partner capabilities/requests */
+	u32 sink_request;
+	u32 source_caps[PDO_MAX_OBJECTS];
+	unsigned int nr_source_caps;
+	u32 sink_caps[PDO_MAX_OBJECTS];
+	unsigned int nr_sink_caps;
+
+	/*
+	 * whether to wait for the Type-C device to send the DR_SWAP Message flag
+	 * For Type-C device with Dual-Role Power and Dual-Role Data, the port side
+	 * is used as sink + ufp, then the tcpm framework needs to wait for Type-C
+	 * device to initiate DR_swap Message.
+	 */
+	bool wait_dr_swap_message;
+
+	/* Local capabilities */
+	u32 src_pdo[PDO_MAX_OBJECTS];
+	unsigned int nr_src_pdo;
+	u32 snk_pdo[PDO_MAX_OBJECTS];
+	unsigned int nr_snk_pdo;
+
+	unsigned int operating_snk_mw;
+	bool update_sink_caps;
+
+	/* Requested current / voltage to the port partner */
+	u32 req_current_limit;
+	u32 req_supply_voltage;
+	/* Actual current / voltage limit of the local port */
+	u32 current_limit;
+	u32 supply_voltage;
+
+	/* port belongs to a self powered device */
+	bool self_powered;
+
+	unsigned long delay_target;
+};
+
+extern const char * const tcpm_states[];
+
+int tcpm_post_probe(struct udevice *dev);
+
+#endif
diff --git a/drivers/usb/tcpm/tcpm-uclass.c b/drivers/usb/tcpm/tcpm-uclass.c
new file mode 100644
index 0000000..d4fe260
--- /dev/null
+++ b/drivers/usb/tcpm/tcpm-uclass.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Collabora Ltd.
+ *
+ * USB Power Delivery protocol stack.
+ */
+
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <usb/tcpm.h>
+#include "tcpm-internal.h"
+
+int tcpm_get_voltage(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return port->supply_voltage;
+}
+
+int tcpm_get_current(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return port->current_limit;
+}
+
+enum typec_orientation tcpm_get_orientation(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	switch (port->polarity) {
+	case TYPEC_POLARITY_CC1:
+		return TYPEC_ORIENTATION_NORMAL;
+	case TYPEC_POLARITY_CC2:
+		return TYPEC_ORIENTATION_REVERSE;
+	default:
+		return TYPEC_ORIENTATION_NONE;
+	}
+}
+
+const char *tcpm_get_state(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return tcpm_states[port->state];
+}
+
+int tcpm_get_pd_rev(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return port->negotiated_rev;
+}
+
+enum typec_role tcpm_get_pwr_role(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return port->pwr_role;
+}
+
+enum typec_data_role tcpm_get_data_role(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return port->data_role;
+}
+
+bool tcpm_is_connected(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return port->connected;
+}
+
+int tcpm_get(int index, struct udevice **devp)
+{
+	return uclass_get_device(UCLASS_TCPM, index, devp);
+}
+
+static int tcpm_post_bind(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	const char *cap_str;
+	ofnode node;
+	int ret;
+
+	/*
+	 * USB Power Delivery (USB PD) specification requires, that communication
+	 * with a sink happens within roughly 5 seconds. Otherwise the source
+	 * might assume that the sink does not support USB PD. Starting to do
+	 * USB PD communication after that results in a hard reset, which briefly
+	 * removes any power from the USB-C port.
+	 *
+	 * On systems with alternative power supplies this is not an issue, but
+	 * systems, which get soleley powered through their USB-C port will end
+	 * up losing their power supply and doing a board level reset. The hard
+	 * reset will also restart the 5 second timeout. That means a operating
+	 * system initializing USB PD will put the system into a boot loop when
+	 * it takes more than 5 seconds from cold boot to the operating system
+	 * starting to transmit USB PD messages.
+	 *
+	 * The issue can be avoided by doing the initial USB PD communication
+	 * in U-Boot. The operating system can then re-negotiate by doing a
+	 * soft reset, which does not trigger removal of the supply voltage.
+	 *
+	 * Since the TCPM state machine is quite complex and depending on the
+	 * remote side can take quite some time to finish, this tries to limit
+	 * the automatic probing to systems probably relying on power being
+	 * provided by the USB-C port(s):
+	 *
+	 * 1. self-powered devices won't reset when the USB-C port looses power
+	 * 2. if the power is allowed to go into anything else than sink mode
+	 *    it is not the only power source
+	 */
+	ret = drvops->get_connector_node(dev, &node);
+	if (ret)
+		return ret;
+
+	if (ofnode_read_bool(node, "self-powered"))
+		return 0;
+
+	cap_str = ofnode_read_string(node, "power-role");
+	if (!cap_str)
+		return -EINVAL;
+
+	if (strcmp("sink", cap_str))
+		return 0;
+
+	/* Do not auto-probe PD controller when PD is disabled */
+	if (ofnode_read_bool(node, "pd-disable"))
+		return 0;
+
+	dev_info(dev, "probing Type-C port manager...");
+
+	dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+	return 0;
+}
+
+UCLASS_DRIVER(tcpm) = {
+	.id		= UCLASS_TCPM,
+	.name		= "tcpm",
+	.per_device_plat_auto	= sizeof(struct tcpm_port),
+	.post_bind	= tcpm_post_bind,
+	.post_probe	= tcpm_post_probe,
+};
diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c
new file mode 100644
index 0000000..0aee57c
--- /dev/null
+++ b/drivers/usb/tcpm/tcpm.c
@@ -0,0 +1,2288 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2017 Google, Inc
+ *
+ * USB Power Delivery protocol stack.
+ */
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/devres.h>
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <time.h>
+#include <usb/tcpm.h>
+#include "tcpm-internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const char * const tcpm_states[] = {
+	FOREACH_TCPM_STATE(GENERATE_TCPM_STRING)
+};
+
+const char * const typec_pd_rev_name[] = {
+	[PD_REV10]		= "rev1",
+	[PD_REV20]		= "rev2",
+	[PD_REV30]		= "rev3",
+};
+
+const char * const typec_role_name[] = {
+	[TYPEC_SINK]		= "sink",
+	[TYPEC_SOURCE]		= "source",
+};
+
+const char * const typec_data_role_name[] = {
+	[TYPEC_DEVICE]		= "device",
+	[TYPEC_HOST]		= "host",
+};
+
+const char * const typec_orientation_name[] = {
+	[TYPEC_ORIENTATION_NONE]	= "none",
+	[TYPEC_ORIENTATION_NORMAL]	= "normal",
+	[TYPEC_ORIENTATION_REVERSE]	= "reverse",
+};
+
+const char * const typec_cc_status_name[] = {
+	[TYPEC_CC_OPEN]		= "open",
+	[TYPEC_CC_RA]		= "ra",
+	[TYPEC_CC_RD]		= "rd",
+	[TYPEC_CC_RP_DEF]	= "rp-def",
+	[TYPEC_CC_RP_1_5]	= "rp-1.5",
+	[TYPEC_CC_RP_3_0]	= "rp-3.0",
+};
+
+static inline bool tcpm_cc_is_sink(enum typec_cc_status cc)
+{
+	return cc == TYPEC_CC_RP_DEF ||
+	       cc == TYPEC_CC_RP_1_5 ||
+	       cc == TYPEC_CC_RP_3_0;
+}
+
+static inline bool tcpm_port_is_sink(struct tcpm_port *port)
+{
+	bool cc1_is_snk = tcpm_cc_is_sink(port->cc1);
+	bool cc2_is_snk = tcpm_cc_is_sink(port->cc2);
+
+	return (cc1_is_snk && !cc2_is_snk) ||
+	       (cc2_is_snk && !cc1_is_snk);
+}
+
+static inline bool tcpm_cc_is_source(enum typec_cc_status cc)
+{
+	return cc == TYPEC_CC_RD;
+}
+
+static inline bool tcpm_port_is_source(struct tcpm_port *port)
+{
+	bool cc1_is_src = tcpm_cc_is_source(port->cc1);
+	bool cc2_is_src = tcpm_cc_is_source(port->cc2);
+
+	return (cc1_is_src && !cc2_is_src) ||
+	       (cc2_is_src && !cc1_is_src);
+}
+
+static inline bool tcpm_try_src(struct tcpm_port *port)
+{
+	return port->try_role == TYPEC_SOURCE &&
+	       port->port_type == TYPEC_PORT_DRP;
+}
+
+static inline void tcpm_reset_event_cnt(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	port->poll_event_cnt = 0;
+}
+
+static enum tcpm_state tcpm_default_state(struct tcpm_port *port)
+{
+	if (port->port_type == TYPEC_PORT_DRP) {
+		if (port->try_role == TYPEC_SINK)
+			return SNK_UNATTACHED;
+		else if (port->try_role == TYPEC_SOURCE)
+			return SRC_UNATTACHED;
+	} else if (port->port_type == TYPEC_PORT_SNK) {
+		return SNK_UNATTACHED;
+	}
+	return SRC_UNATTACHED;
+}
+
+static bool tcpm_port_is_disconnected(struct tcpm_port *port)
+{
+	return (!port->attached && port->cc1 == TYPEC_CC_OPEN &&
+		port->cc2 == TYPEC_CC_OPEN) ||
+	       (port->attached && ((port->polarity == TYPEC_POLARITY_CC1 &&
+				    port->cc1 == TYPEC_CC_OPEN) ||
+				   (port->polarity == TYPEC_POLARITY_CC2 &&
+				    port->cc2 == TYPEC_CC_OPEN)));
+}
+
+static void tcpm_set_cc(struct udevice *dev, enum typec_cc_status cc)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	dev_dbg(dev, "TCPM: set cc = %d\n", cc);
+	port->cc_req = cc;
+	drvops->set_cc(dev, cc);
+}
+
+/*
+ * Determine RP value to set based on maximum current supported
+ * by a port if configured as source.
+ * Returns CC value to report to link partner.
+ */
+static enum typec_cc_status tcpm_rp_cc(struct tcpm_port *port)
+{
+	const u32 *src_pdo = port->src_pdo;
+	int nr_pdo = port->nr_src_pdo;
+	int i;
+
+	/*
+	 * Search for first entry with matching voltage.
+	 * It should report the maximum supported current.
+	 */
+	for (i = 0; i < nr_pdo; i++) {
+		const u32 pdo = src_pdo[i];
+
+		if (pdo_type(pdo) == PDO_TYPE_FIXED &&
+		    pdo_fixed_voltage(pdo) == 5000) {
+			unsigned int curr = pdo_max_current(pdo);
+
+			if (curr >= 3000)
+				return TYPEC_CC_RP_3_0;
+			else if (curr >= 1500)
+				return TYPEC_CC_RP_1_5;
+			return TYPEC_CC_RP_DEF;
+		}
+	}
+
+	return TYPEC_CC_RP_DEF;
+}
+
+static void tcpm_check_and_run_delayed_work(struct udevice *dev);
+
+static bool tcpm_transmit_helper(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	drvops->poll_event(dev);
+	udelay(500);
+	tcpm_check_and_run_delayed_work(dev);
+	return port->tx_complete;
+}
+
+static int tcpm_pd_transmit(struct udevice *dev,
+			    enum tcpm_transmit_type type,
+			    const struct pd_message *msg)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	u32 timeout_us = PD_T_TCPC_TX_TIMEOUT * 1000;
+	bool tx_complete;
+	int ret;
+
+	if (msg)
+		dev_dbg(dev, "TCPM: PD TX, header: %#x\n",
+			le16_to_cpu(msg->header));
+	else
+		dev_dbg(dev, "TCPM: PD TX, type: %#x\n", type);
+
+	port->tx_complete = false;
+	ret = drvops->pd_transmit(dev, type, msg, port->negotiated_rev);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * At this point we basically need to block until the TCPM controller
+	 * returns successful transmission. Since this is usually done using
+	 * the generic interrupt status bits, we poll for any events. That
+	 * will clear the interrupt status, so we also need to process any
+	 * of the incoming events. This means we will do more processing and
+	 * thus let's give everything a bit more time.
+	 */
+	timeout_us *= 5;
+	ret = read_poll_timeout(tcpm_transmit_helper, tx_complete,
+				!tx_complete, false, timeout_us, dev);
+	if (ret < 0) {
+		dev_err(dev, "TCPM: PD transmit data failed: %d\n", ret);
+		return ret;
+	}
+
+	switch (port->tx_status) {
+	case TCPC_TX_SUCCESS:
+		port->message_id = (port->message_id + 1) & PD_HEADER_ID_MASK;
+		break;
+	case TCPC_TX_DISCARDED:
+		ret = -EAGAIN;
+		break;
+	case TCPC_TX_FAILED:
+	default:
+		ret = -EIO;
+		break;
+	}
+
+	return ret;
+}
+
+void tcpm_pd_transmit_complete(struct udevice *dev,
+			       enum tcpm_transmit_status status)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	dev_dbg(dev, "TCPM: PD TX complete, status: %u\n", status);
+	tcpm_reset_event_cnt(dev);
+	port->tx_status = status;
+	port->tx_complete = true;
+}
+
+static int tcpm_set_polarity(struct udevice *dev,
+			     enum typec_cc_polarity polarity)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	int ret;
+
+	dev_dbg(dev, "TCPM: set polarity = %d\n", polarity);
+
+	if (drvops->set_polarity) {
+		ret = drvops->set_polarity(dev, polarity);
+		if (ret < 0)
+			return ret;
+	}
+
+	port->polarity = polarity;
+
+	return 0;
+}
+
+static int tcpm_set_vconn(struct udevice *dev, bool enable)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	dev_dbg(dev, "TCPM: set vconn = %d\n", enable);
+
+	ret = drvops->set_vconn(dev, enable);
+	if (!ret)
+		port->vconn_role = enable ? TYPEC_SOURCE : TYPEC_SINK;
+
+	return ret;
+}
+
+static inline u32 tcpm_get_current_limit(struct tcpm_port *port)
+{
+	switch (port->polarity ? port->cc2 : port->cc1) {
+	case TYPEC_CC_RP_1_5:
+		return 1500;
+	case TYPEC_CC_RP_3_0:
+		return 3000;
+	case TYPEC_CC_RP_DEF:
+	default:
+		return 0;
+	}
+}
+
+static int tcpm_set_current_limit(struct udevice *dev, u32 max_ma, u32 mv)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret = -EOPNOTSUPP;
+
+	dev_info(dev, "TCPM: set voltage limit = %u mV\n", mv);
+	dev_info(dev, "TCPM: set current limit = %u mA\n", max_ma);
+
+	port->supply_voltage = mv;
+	port->current_limit = max_ma;
+
+	return ret;
+}
+
+static int tcpm_set_attached_state(struct udevice *dev, bool attached)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	return drvops->set_roles(dev, attached, port->pwr_role,
+				 port->data_role);
+}
+
+static int tcpm_set_roles(struct udevice *dev, bool attached,
+			  enum typec_role role, enum typec_data_role data)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	ret = drvops->set_roles(dev, attached, role, data);
+	if (ret < 0)
+		return ret;
+
+	port->pwr_role = role;
+	port->data_role = data;
+
+	return 0;
+}
+
+static int tcpm_pd_send_source_caps(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	struct pd_message msg;
+	int i;
+
+	memset(&msg, 0, sizeof(msg));
+
+	if (!port->nr_src_pdo) {
+		/* No source capabilities defined, sink only */
+		msg.header = PD_HEADER_LE(PD_CTRL_REJECT,
+					  port->pwr_role,
+					  port->data_role,
+					  port->negotiated_rev,
+					  port->message_id, 0);
+	} else {
+		msg.header = PD_HEADER_LE(PD_DATA_SOURCE_CAP,
+					  port->pwr_role,
+					  port->data_role,
+					  port->negotiated_rev,
+					  port->message_id,
+					  port->nr_src_pdo);
+	}
+
+	for (i = 0; i < port->nr_src_pdo; i++)
+		msg.payload[i] = cpu_to_le32(port->src_pdo[i]);
+
+	return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+static int tcpm_pd_send_sink_caps(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	struct pd_message msg;
+	unsigned int i;
+
+	memset(&msg, 0, sizeof(msg));
+
+	if (!port->nr_snk_pdo) {
+		/* No sink capabilities defined, source only */
+		msg.header = PD_HEADER_LE(PD_CTRL_REJECT,
+					  port->pwr_role,
+					  port->data_role,
+					  port->negotiated_rev,
+					  port->message_id, 0);
+	} else {
+		msg.header = PD_HEADER_LE(PD_DATA_SINK_CAP,
+					  port->pwr_role,
+					  port->data_role,
+					  port->negotiated_rev,
+					  port->message_id,
+					  port->nr_snk_pdo);
+	}
+
+	for (i = 0; i < port->nr_snk_pdo; i++)
+		msg.payload[i] = cpu_to_le32(port->snk_pdo[i]);
+
+	return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+static void tcpm_state_machine(struct udevice *dev);
+
+static inline void tcpm_timer_uninit(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	port->delay_target = 0;
+}
+
+static void tcpm_timer_init(struct udevice *dev, uint32_t ms)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	unsigned long time_us = ms * 1000;
+
+	port->delay_target = timer_get_us() + time_us;
+}
+
+static void tcpm_check_and_run_delayed_work(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	/* no delayed state changes scheduled */
+	if (port->delay_target == 0)
+		return;
+
+	/* it's not yet time */
+	if (timer_get_us() < port->delay_target)
+		return;
+
+	tcpm_timer_uninit(dev);
+	tcpm_state_machine(dev);
+}
+
+static void mod_tcpm_delayed_work(struct udevice *dev, unsigned int delay_ms)
+{
+	if (delay_ms) {
+		tcpm_timer_init(dev, delay_ms);
+	} else {
+		tcpm_timer_uninit(dev);
+		tcpm_state_machine(dev);
+	}
+}
+
+static void tcpm_set_state(struct udevice *dev, enum tcpm_state state,
+			   unsigned int delay_ms)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	if (delay_ms) {
+		dev_dbg(dev, "TCPM: pending state change %s -> %s @ %u ms [%s]\n",
+			tcpm_states[port->state], tcpm_states[state], delay_ms,
+			typec_pd_rev_name[port->negotiated_rev]);
+		port->delayed_state = state;
+		mod_tcpm_delayed_work(dev, delay_ms);
+		port->delay_ms = delay_ms;
+	} else {
+		dev_dbg(dev, "TCPM: state change %s -> %s\n",
+			tcpm_states[port->state], tcpm_states[state]);
+		port->delayed_state = INVALID_STATE;
+		port->prev_state = port->state;
+		port->state = state;
+		/*
+		 * Don't re-queue the state machine work item if we're currently
+		 * in the state machine and we're immediately changing states.
+		 * tcpm_state_machine_work() will continue running the state
+		 * machine.
+		 */
+		if (!port->state_machine_running)
+			mod_tcpm_delayed_work(dev, 0);
+	}
+}
+
+static void tcpm_set_state_cond(struct udevice *dev, enum tcpm_state state,
+				unsigned int delay_ms)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	if (port->enter_state == port->state)
+		tcpm_set_state(dev, state, delay_ms);
+	else
+		dev_dbg(dev, "TCPM: skipped %sstate change %s -> %s [%u ms], context state %s [%s]\n",
+			delay_ms ? "delayed " : "",
+			tcpm_states[port->state], tcpm_states[state],
+			delay_ms, tcpm_states[port->enter_state],
+			typec_pd_rev_name[port->negotiated_rev]);
+}
+
+static void tcpm_queue_message(struct udevice *dev,
+			       enum pd_msg_request message)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	port->queued_message = message;
+	mod_tcpm_delayed_work(dev, 0);
+}
+
+enum pdo_err {
+	PDO_NO_ERR,
+	PDO_ERR_NO_VSAFE5V,
+	PDO_ERR_VSAFE5V_NOT_FIRST,
+	PDO_ERR_PDO_TYPE_NOT_IN_ORDER,
+	PDO_ERR_FIXED_NOT_SORTED,
+	PDO_ERR_VARIABLE_BATT_NOT_SORTED,
+	PDO_ERR_DUPE_PDO,
+	PDO_ERR_PPS_APDO_NOT_SORTED,
+	PDO_ERR_DUPE_PPS_APDO,
+};
+
+static const char * const pdo_err_msg[] = {
+	[PDO_ERR_NO_VSAFE5V] =
+	" err: source/sink caps should at least have vSafe5V",
+	[PDO_ERR_VSAFE5V_NOT_FIRST] =
+	" err: vSafe5V Fixed Supply Object Shall always be the first object",
+	[PDO_ERR_PDO_TYPE_NOT_IN_ORDER] =
+	" err: PDOs should be in the following order: Fixed; Battery; Variable",
+	[PDO_ERR_FIXED_NOT_SORTED] =
+	" err: Fixed supply pdos should be in increasing order of their fixed voltage",
+	[PDO_ERR_VARIABLE_BATT_NOT_SORTED] =
+	" err: Variable/Battery supply pdos should be in increasing order of their minimum voltage",
+	[PDO_ERR_DUPE_PDO] =
+	" err: Variable/Batt supply pdos cannot have same min/max voltage",
+	[PDO_ERR_PPS_APDO_NOT_SORTED] =
+	" err: Programmable power supply apdos should be in increasing order of their maximum voltage",
+	[PDO_ERR_DUPE_PPS_APDO] =
+	" err: Programmable power supply apdos cannot have same min/max voltage and max current",
+};
+
+static enum pdo_err tcpm_caps_err(struct udevice *dev, const u32 *pdo,
+				  unsigned int nr_pdo)
+{
+	unsigned int i;
+
+	/* Should at least contain vSafe5v */
+	if (nr_pdo < 1)
+		return PDO_ERR_NO_VSAFE5V;
+
+	/* The vSafe5V Fixed Supply Object Shall always be the first object */
+	if (pdo_type(pdo[0]) != PDO_TYPE_FIXED ||
+	    pdo_fixed_voltage(pdo[0]) != VSAFE5V)
+		return PDO_ERR_VSAFE5V_NOT_FIRST;
+
+	for (i = 1; i < nr_pdo; i++) {
+		if (pdo_type(pdo[i]) < pdo_type(pdo[i - 1])) {
+			return PDO_ERR_PDO_TYPE_NOT_IN_ORDER;
+		} else if (pdo_type(pdo[i]) == pdo_type(pdo[i - 1])) {
+			enum pd_pdo_type type = pdo_type(pdo[i]);
+
+			switch (type) {
+			/*
+			 * The remaining Fixed Supply Objects, if
+			 * present, shall be sent in voltage order;
+			 * lowest to highest.
+			 */
+			case PDO_TYPE_FIXED:
+				if (pdo_fixed_voltage(pdo[i]) <=
+				    pdo_fixed_voltage(pdo[i - 1]))
+					return PDO_ERR_FIXED_NOT_SORTED;
+				break;
+			/*
+			 * The Battery Supply Objects and Variable
+			 * supply, if present shall be sent in Minimum
+			 * Voltage order; lowest to highest.
+			 */
+			case PDO_TYPE_VAR:
+			case PDO_TYPE_BATT:
+				if (pdo_min_voltage(pdo[i]) <
+				    pdo_min_voltage(pdo[i - 1]))
+					return PDO_ERR_VARIABLE_BATT_NOT_SORTED;
+				else if ((pdo_min_voltage(pdo[i]) ==
+					  pdo_min_voltage(pdo[i - 1])) &&
+					 (pdo_max_voltage(pdo[i]) ==
+					  pdo_max_voltage(pdo[i - 1])))
+					return PDO_ERR_DUPE_PDO;
+				break;
+			/*
+			 * The Programmable Power Supply APDOs, if present,
+			 * shall be sent in Maximum Voltage order;
+			 * lowest to highest.
+			 */
+			case PDO_TYPE_APDO:
+				if (pdo_apdo_type(pdo[i]) != APDO_TYPE_PPS)
+					break;
+
+				if (pdo_pps_apdo_max_voltage(pdo[i]) <
+				    pdo_pps_apdo_max_voltage(pdo[i - 1]))
+					return PDO_ERR_PPS_APDO_NOT_SORTED;
+				else if (pdo_pps_apdo_min_voltage(pdo[i]) ==
+					  pdo_pps_apdo_min_voltage(pdo[i - 1]) &&
+					 pdo_pps_apdo_max_voltage(pdo[i]) ==
+					  pdo_pps_apdo_max_voltage(pdo[i - 1]) &&
+					 pdo_pps_apdo_max_current(pdo[i]) ==
+					  pdo_pps_apdo_max_current(pdo[i - 1]))
+					return PDO_ERR_DUPE_PPS_APDO;
+				break;
+			default:
+				dev_err(dev, "TCPM: Unknown pdo type\n");
+			}
+		}
+	}
+
+	return PDO_NO_ERR;
+}
+
+static int tcpm_validate_caps(struct udevice *dev, const u32 *pdo,
+			      unsigned int nr_pdo)
+{
+	enum pdo_err err_index = tcpm_caps_err(dev, pdo, nr_pdo);
+
+	if (err_index != PDO_NO_ERR) {
+		dev_err(dev, "TCPM:%s\n", pdo_err_msg[err_index]);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * PD (data, control) command handling functions
+ */
+static inline enum tcpm_state ready_state(struct tcpm_port *port)
+{
+	if (port->pwr_role == TYPEC_SOURCE)
+		return SRC_READY;
+	else
+		return SNK_READY;
+}
+
+static void tcpm_pd_data_request(struct udevice *dev,
+				 const struct pd_message *msg)
+{
+	enum pd_data_msg_type type = pd_header_type_le(msg->header);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	unsigned int cnt = pd_header_cnt_le(msg->header);
+	unsigned int rev = pd_header_rev_le(msg->header);
+	unsigned int i;
+
+	switch (type) {
+	case PD_DATA_SOURCE_CAP:
+		for (i = 0; i < cnt; i++)
+			port->source_caps[i] = le32_to_cpu(msg->payload[i]);
+
+		port->nr_source_caps = cnt;
+
+		tcpm_validate_caps(dev, port->source_caps,
+				   port->nr_source_caps);
+
+		/*
+		 * Adjust revision in subsequent message headers, as required,
+		 * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't
+		 * support Rev 1.0 so just do nothing in that scenario.
+		 */
+		if (rev == PD_REV10)
+			break;
+
+		if (rev < PD_MAX_REV)
+			port->negotiated_rev = rev;
+
+		if ((pdo_type(port->source_caps[0]) == PDO_TYPE_FIXED) &&
+		    (port->source_caps[0] & PDO_FIXED_DUAL_ROLE) &&
+		    (port->source_caps[0] & PDO_FIXED_DATA_SWAP)) {
+			/* Dual role power and data, eg: self-powered Type-C */
+			port->wait_dr_swap_message = true;
+		} else {
+			/* Non-Dual role power, eg: adapter */
+			port->wait_dr_swap_message = false;
+		}
+
+		/*
+		 * This message may be received even if VBUS is not
+		 * present. This is quite unexpected; see USB PD
+		 * specification, sections 8.3.3.6.3.1 and 8.3.3.6.3.2.
+		 * However, at the same time, we must be ready to
+		 * receive this message and respond to it 15ms after
+		 * receiving PS_RDY during power swap operations, no matter
+		 * if VBUS is available or not (USB PD specification,
+		 * section 6.5.9.2).
+		 * So we need to accept the message either way,
+		 * but be prepared to keep waiting for VBUS after it was
+		 * handled.
+		 */
+		tcpm_set_state(dev, SNK_NEGOTIATE_CAPABILITIES, 0);
+		break;
+	case PD_DATA_REQUEST:
+		/*
+		 * Adjust revision in subsequent message headers, as required,
+		 * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't
+		 * support Rev 1.0 so just reject in that scenario.
+		 */
+		if (rev == PD_REV10) {
+			tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+			break;
+		}
+
+		if (rev < PD_MAX_REV)
+			port->negotiated_rev = rev;
+
+		port->sink_request = le32_to_cpu(msg->payload[0]);
+
+		tcpm_set_state(dev, SRC_NEGOTIATE_CAPABILITIES, 0);
+		break;
+	case PD_DATA_SINK_CAP:
+		/* We don't do anything with this at the moment... */
+		for (i = 0; i < cnt; i++)
+			port->sink_caps[i] = le32_to_cpu(msg->payload[i]);
+
+		port->nr_sink_caps = cnt;
+		break;
+	default:
+		break;
+	}
+}
+
+static void tcpm_pd_ctrl_request(struct udevice *dev,
+				 const struct pd_message *msg)
+{
+	enum pd_ctrl_msg_type type = pd_header_type_le(msg->header);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	enum tcpm_state next_state;
+
+	switch (type) {
+	case PD_CTRL_GOOD_CRC:
+	case PD_CTRL_PING:
+		break;
+	case PD_CTRL_GET_SOURCE_CAP:
+		switch (port->state) {
+		case SRC_READY:
+		case SNK_READY:
+			tcpm_queue_message(dev, PD_MSG_DATA_SOURCE_CAP);
+			break;
+		default:
+			tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+			break;
+		}
+		break;
+	case PD_CTRL_GET_SINK_CAP:
+		switch (port->state) {
+		case SRC_READY:
+		case SNK_READY:
+			tcpm_queue_message(dev, PD_MSG_DATA_SINK_CAP);
+			break;
+		default:
+			tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+			break;
+		}
+		break;
+	case PD_CTRL_GOTO_MIN:
+		break;
+	case PD_CTRL_PS_RDY:
+		switch (port->state) {
+		case SNK_TRANSITION_SINK:
+			if (port->vbus_present) {
+				tcpm_set_current_limit(dev,
+						       port->req_current_limit,
+						       port->req_supply_voltage);
+				port->explicit_contract = true;
+				tcpm_set_state(dev, SNK_READY, 0);
+			} else {
+				/*
+				 * Seen after power swap. Keep waiting for VBUS
+				 * in a transitional state.
+				 */
+				tcpm_set_state(dev,
+					       SNK_TRANSITION_SINK_VBUS, 0);
+			}
+			break;
+		default:
+			break;
+		}
+		break;
+	case PD_CTRL_REJECT:
+	case PD_CTRL_WAIT:
+	case PD_CTRL_NOT_SUPP:
+		switch (port->state) {
+		case SNK_NEGOTIATE_CAPABILITIES:
+			/* USB PD specification, Figure 8-43 */
+			if (port->explicit_contract)
+				next_state = SNK_READY;
+			else
+				next_state = SNK_WAIT_CAPABILITIES;
+
+			tcpm_set_state(dev, next_state, 0);
+			break;
+		default:
+			break;
+		}
+		break;
+	case PD_CTRL_ACCEPT:
+		switch (port->state) {
+		case SNK_NEGOTIATE_CAPABILITIES:
+			tcpm_set_state(dev, SNK_TRANSITION_SINK, 0);
+			break;
+		case SOFT_RESET_SEND:
+			port->message_id = 0;
+			port->rx_msgid = -1;
+			if (port->pwr_role == TYPEC_SOURCE)
+				next_state = SRC_SEND_CAPABILITIES;
+			else
+				next_state = SNK_WAIT_CAPABILITIES;
+			tcpm_set_state(dev, next_state, 0);
+			break;
+		default:
+			break;
+		}
+		break;
+	case PD_CTRL_SOFT_RESET:
+		tcpm_set_state(dev, SOFT_RESET, 0);
+		break;
+	case PD_CTRL_DR_SWAP:
+		if (port->port_type != TYPEC_PORT_DRP) {
+			tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+			break;
+		}
+		/*
+		 * 6.3.9: If an alternate mode is active, a request to swap
+		 * alternate modes shall trigger a port reset.
+		 */
+		switch (port->state) {
+		case SRC_READY:
+		case SNK_READY:
+			tcpm_set_state(dev, DR_SWAP_ACCEPT, 0);
+			break;
+		default:
+			tcpm_queue_message(dev, PD_MSG_CTRL_WAIT);
+			break;
+		}
+		break;
+	case PD_CTRL_PR_SWAP:
+	case PD_CTRL_VCONN_SWAP:
+	case PD_CTRL_GET_SOURCE_CAP_EXT:
+	case PD_CTRL_GET_STATUS:
+	case PD_CTRL_FR_SWAP:
+	case PD_CTRL_GET_PPS_STATUS:
+	case PD_CTRL_GET_COUNTRY_CODES:
+		/* Currently not supported */
+		dev_err(dev, "TCPM: Currently not supported type %#x\n", type);
+		tcpm_queue_message(dev, PD_MSG_CTRL_NOT_SUPP);
+		break;
+	default:
+		dev_err(dev, "TCPM: Unrecognized ctrl message type %#x\n", type);
+		break;
+	}
+}
+
+static void tcpm_pd_rx_handler(struct udevice *dev,
+			       const struct pd_message *msg)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	unsigned int cnt = pd_header_cnt_le(msg->header);
+	bool remote_is_host, local_is_host;
+
+	dev_dbg(dev, "TCPM: PD RX, header: %#x [%d]\n",
+		le16_to_cpu(msg->header), port->attached);
+
+	if (port->attached) {
+		enum pd_ctrl_msg_type type = pd_header_type_le(msg->header);
+		unsigned int msgid = pd_header_msgid_le(msg->header);
+
+		/*
+		 * USB PD standard, 6.6.1.2:
+		 * "... if MessageID value in a received Message is the
+		 * same as the stored value, the receiver shall return a
+		 * GoodCRC Message with that MessageID value and drop
+		 * the Message (this is a retry of an already received
+		 * Message). Note: this shall not apply to the Soft_Reset
+		 * Message which always has a MessageID value of zero."
+		 */
+		if (msgid == port->rx_msgid && type != PD_CTRL_SOFT_RESET)
+			return;
+		port->rx_msgid = msgid;
+
+		/*
+		 * If both ends believe to be DFP/host, we have a data role
+		 * mismatch.
+		 */
+		remote_is_host = !!(le16_to_cpu(msg->header) & PD_HEADER_DATA_ROLE);
+		local_is_host = port->data_role == TYPEC_HOST;
+		if (remote_is_host == local_is_host) {
+			dev_err(dev, "TCPM: data role mismatch, initiating error recovery\n");
+			tcpm_set_state(dev, ERROR_RECOVERY, 0);
+		} else {
+			if (cnt)
+				tcpm_pd_data_request(dev, msg);
+			else
+				tcpm_pd_ctrl_request(dev, msg);
+		}
+	}
+}
+
+void tcpm_pd_receive(struct udevice *dev, const struct pd_message *msg)
+{
+	tcpm_reset_event_cnt(dev);
+	tcpm_pd_rx_handler(dev, msg);
+}
+
+static int tcpm_pd_send_control(struct udevice *dev,
+				enum pd_ctrl_msg_type type)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	struct pd_message msg;
+
+	memset(&msg, 0, sizeof(msg));
+	msg.header = PD_HEADER_LE(type, port->pwr_role,
+				  port->data_role,
+				  port->negotiated_rev,
+				  port->message_id, 0);
+
+	return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+/*
+ * Send queued message without affecting state.
+ * Return true if state machine should go back to sleep,
+ * false otherwise.
+ */
+static bool tcpm_send_queued_message(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	enum pd_msg_request queued_message;
+	int max_messages = 100;
+
+	do {
+		queued_message = port->queued_message;
+		port->queued_message = PD_MSG_NONE;
+		max_messages--;
+
+		switch (queued_message) {
+		case PD_MSG_CTRL_WAIT:
+			tcpm_pd_send_control(dev, PD_CTRL_WAIT);
+			break;
+		case PD_MSG_CTRL_REJECT:
+			tcpm_pd_send_control(dev, PD_CTRL_REJECT);
+			break;
+		case PD_MSG_CTRL_NOT_SUPP:
+			tcpm_pd_send_control(dev, PD_CTRL_NOT_SUPP);
+			break;
+		case PD_MSG_DATA_SINK_CAP:
+			tcpm_pd_send_sink_caps(dev);
+			break;
+		case PD_MSG_DATA_SOURCE_CAP:
+			tcpm_pd_send_source_caps(dev);
+			break;
+		default:
+			break;
+		}
+	} while (max_messages > 0 && port->queued_message != PD_MSG_NONE);
+
+	if (!max_messages)
+		dev_err(dev, "Aborted sending of too many queued messages\n");
+
+	return false;
+}
+
+static int tcpm_pd_check_request(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	u32 pdo, rdo = port->sink_request;
+	unsigned int max, op, pdo_max, index;
+	enum pd_pdo_type type;
+
+	index = rdo_index(rdo);
+	if (!index || index > port->nr_src_pdo)
+		return -EINVAL;
+
+	pdo = port->src_pdo[index - 1];
+	type = pdo_type(pdo);
+	switch (type) {
+	case PDO_TYPE_FIXED:
+	case PDO_TYPE_VAR:
+		max = rdo_max_current(rdo);
+		op = rdo_op_current(rdo);
+		pdo_max = pdo_max_current(pdo);
+
+		if (op > pdo_max)
+			return -EINVAL;
+		if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH))
+			return -EINVAL;
+
+		if (type == PDO_TYPE_FIXED)
+			dev_dbg(dev, "TCPM: Requested %u mV, %u mA for %u / %u mA\n",
+				pdo_fixed_voltage(pdo), pdo_max, op, max);
+		else
+			dev_dbg(dev, "TCPM: Requested %u -> %u mV, %u mA for %u / %u mA\n",
+				pdo_min_voltage(pdo), pdo_max_voltage(pdo),
+				pdo_max, op, max);
+		break;
+	case PDO_TYPE_BATT:
+		max = rdo_max_power(rdo);
+		op = rdo_op_power(rdo);
+		pdo_max = pdo_max_power(pdo);
+
+		if (op > pdo_max)
+			return -EINVAL;
+		if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH))
+			return -EINVAL;
+		dev_info(dev, "TCPM: Requested %u -> %u mV, %u mW for %u / %u mW\n",
+			 pdo_min_voltage(pdo), pdo_max_voltage(pdo),
+			 pdo_max, op, max);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+#define min_power(x, y) min(pdo_max_power(x), pdo_max_power(y))
+#define min_current(x, y) min(pdo_max_current(x), pdo_max_current(y))
+
+static int tcpm_pd_select_pdo(struct udevice *dev, int *sink_pdo,
+			      int *src_pdo)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	unsigned int i, j, max_src_mv = 0, min_src_mv = 0, max_mw = 0,
+		     max_mv = 0, src_mw = 0, src_ma = 0, max_snk_mv = 0,
+		     min_snk_mv = 0;
+	int ret = -EINVAL;
+
+	/*
+	 * Select the source PDO providing the most power which has a
+	 * matchig sink cap.
+	 */
+	for (i = 0; i < port->nr_source_caps; i++) {
+		u32 pdo = port->source_caps[i];
+		enum pd_pdo_type type = pdo_type(pdo);
+
+		switch (type) {
+		case PDO_TYPE_FIXED:
+			max_src_mv = pdo_fixed_voltage(pdo);
+			min_src_mv = max_src_mv;
+			break;
+		case PDO_TYPE_BATT:
+		case PDO_TYPE_VAR:
+			max_src_mv = pdo_max_voltage(pdo);
+			min_src_mv = pdo_min_voltage(pdo);
+			break;
+		case PDO_TYPE_APDO:
+			continue;
+		default:
+			dev_err(dev, "TCPM: Invalid source PDO type, ignoring\n");
+			continue;
+		}
+
+		switch (type) {
+		case PDO_TYPE_FIXED:
+		case PDO_TYPE_VAR:
+			src_ma = pdo_max_current(pdo);
+			src_mw = src_ma * min_src_mv / 1000;
+			break;
+		case PDO_TYPE_BATT:
+			src_mw = pdo_max_power(pdo);
+			break;
+		case PDO_TYPE_APDO:
+			continue;
+		default:
+			dev_err(dev, "TCPM: Invalid source PDO type, ignoring\n");
+			continue;
+		}
+
+		for (j = 0; j < port->nr_snk_pdo; j++) {
+			pdo = port->snk_pdo[j];
+
+			switch (pdo_type(pdo)) {
+			case PDO_TYPE_FIXED:
+				max_snk_mv = pdo_fixed_voltage(pdo);
+				min_snk_mv = max_snk_mv;
+				break;
+			case PDO_TYPE_BATT:
+			case PDO_TYPE_VAR:
+				max_snk_mv = pdo_max_voltage(pdo);
+				min_snk_mv = pdo_min_voltage(pdo);
+				break;
+			case PDO_TYPE_APDO:
+				continue;
+			default:
+				dev_err(dev, "TCPM: Invalid sink PDO type, ignoring\n");
+				continue;
+			}
+
+			if (max_src_mv <= max_snk_mv && min_src_mv >= min_snk_mv) {
+				/* Prefer higher voltages if available */
+				if ((src_mw == max_mw && min_src_mv > max_mv) ||
+				    src_mw > max_mw) {
+					*src_pdo = i;
+					*sink_pdo = j;
+					max_mw = src_mw;
+					max_mv = min_src_mv;
+					ret = 0;
+				}
+			}
+		}
+	}
+
+	return ret;
+}
+
+static int tcpm_pd_build_request(struct udevice *dev, u32 *rdo)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	unsigned int mv, ma, mw, flags;
+	unsigned int max_ma, max_mw;
+	enum pd_pdo_type type;
+	u32 pdo, matching_snk_pdo;
+	int src_pdo_index = 0;
+	int snk_pdo_index = 0;
+	int ret;
+
+	ret = tcpm_pd_select_pdo(dev, &snk_pdo_index, &src_pdo_index);
+	if (ret < 0)
+		return ret;
+
+	pdo = port->source_caps[src_pdo_index];
+	matching_snk_pdo = port->snk_pdo[snk_pdo_index];
+	type = pdo_type(pdo);
+
+	switch (type) {
+	case PDO_TYPE_FIXED:
+		mv = pdo_fixed_voltage(pdo);
+		break;
+	case PDO_TYPE_BATT:
+	case PDO_TYPE_VAR:
+		mv = pdo_min_voltage(pdo);
+		break;
+	default:
+		dev_err(dev, "TCPM: Invalid PDO selected!\n");
+		return -EINVAL;
+	}
+
+	/* Select maximum available current within the sink pdo's limit */
+	if (type == PDO_TYPE_BATT) {
+		mw = min_power(pdo, matching_snk_pdo);
+		ma = 1000 * mw / mv;
+	} else {
+		ma = min_current(pdo, matching_snk_pdo);
+		mw = ma * mv / 1000;
+	}
+
+	flags = RDO_USB_COMM | RDO_NO_SUSPEND;
+
+	/* Set mismatch bit if offered power is less than operating power */
+	max_ma = ma;
+	max_mw = mw;
+	if (mw < port->operating_snk_mw) {
+		flags |= RDO_CAP_MISMATCH;
+		if (type == PDO_TYPE_BATT &&
+		    (pdo_max_power(matching_snk_pdo) > pdo_max_power(pdo)))
+			max_mw = pdo_max_power(matching_snk_pdo);
+		else if (pdo_max_current(matching_snk_pdo) >
+			 pdo_max_current(pdo))
+			max_ma = pdo_max_current(matching_snk_pdo);
+	}
+
+	dev_dbg(dev, "TCPM: cc=%d cc1=%d cc2=%d vbus=%d vconn=%s polarity=%d\n",
+		port->cc_req, port->cc1, port->cc2, port->vbus_source,
+		port->vconn_role == TYPEC_SOURCE ? "source" : "sink",
+		port->polarity);
+
+	if (type == PDO_TYPE_BATT) {
+		*rdo = RDO_BATT(src_pdo_index + 1, mw, max_mw, flags);
+
+		dev_info(dev, "TCPM: requesting PDO %d: %u mV, %u mW%s\n",
+			 src_pdo_index, mv, mw,
+			 flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+	} else {
+		*rdo = RDO_FIXED(src_pdo_index + 1, ma, max_ma, flags);
+
+		dev_info(dev, "TCPM: requesting PDO %d: %u mV, %u mA%s\n",
+			 src_pdo_index, mv, ma,
+			 flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+	}
+
+	port->req_current_limit = ma;
+	port->req_supply_voltage = mv;
+
+	return 0;
+}
+
+static int tcpm_pd_send_request(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	struct pd_message msg;
+	int ret;
+	u32 rdo;
+
+	ret = tcpm_pd_build_request(dev, &rdo);
+	if (ret < 0)
+		return ret;
+
+	memset(&msg, 0, sizeof(msg));
+	msg.header = PD_HEADER_LE(PD_DATA_REQUEST,
+				  port->pwr_role,
+				  port->data_role,
+				  port->negotiated_rev,
+				  port->message_id, 1);
+	msg.payload[0] = cpu_to_le32(rdo);
+
+	return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+static int tcpm_set_vbus(struct udevice *dev, bool enable)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	int ret;
+
+	if (enable && port->vbus_charge)
+		return -EINVAL;
+
+	dev_dbg(dev, "TCPM: set vbus = %d charge = %d\n",
+		enable, port->vbus_charge);
+
+	ret = drvops->set_vbus(dev, enable, port->vbus_charge);
+	if (ret < 0)
+		return ret;
+
+	port->vbus_source = enable;
+	return 0;
+}
+
+static int tcpm_set_charge(struct udevice *dev, bool charge)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	if (charge && port->vbus_source)
+		return -EINVAL;
+
+	if (charge != port->vbus_charge) {
+		dev_dbg(dev, "TCPM: set vbus = %d charge = %d\n",
+			port->vbus_source, charge);
+		ret = drvops->set_vbus(dev, port->vbus_source,
+					   charge);
+		if (ret < 0)
+			return ret;
+	}
+	port->vbus_charge = charge;
+	return 0;
+}
+
+static bool tcpm_start_toggling(struct udevice *dev, enum typec_cc_status cc)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	if (!drvops->start_toggling)
+		return false;
+
+	dev_dbg(dev, "TCPM: Start toggling\n");
+	ret = drvops->start_toggling(dev, port->port_type, cc);
+	return ret == 0;
+}
+
+static int tcpm_init_vbus(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	ret = drvops->set_vbus(dev, false, false);
+	port->vbus_source = false;
+	port->vbus_charge = false;
+	return ret;
+}
+
+static int tcpm_init_vconn(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	ret = drvops->set_vconn(dev, false);
+	port->vconn_role = TYPEC_SINK;
+	return ret;
+}
+
+static inline void tcpm_typec_connect(struct tcpm_port *port)
+{
+	if (!port->connected)
+		port->connected = true;
+}
+
+static int tcpm_src_attach(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	enum typec_cc_polarity polarity =
+				port->cc2 == TYPEC_CC_RD ? TYPEC_POLARITY_CC2
+							 : TYPEC_POLARITY_CC1;
+	int ret;
+
+	if (port->attached)
+		return 0;
+
+	ret = tcpm_set_polarity(dev, polarity);
+	if (ret < 0)
+		return ret;
+
+	ret = tcpm_set_roles(dev, true, TYPEC_SOURCE, TYPEC_HOST);
+	if (ret < 0)
+		return ret;
+
+	ret = drvops->set_pd_rx(dev, true);
+	if (ret < 0)
+		goto out_disable_mux;
+
+	/*
+	 * USB Type-C specification, version 1.2,
+	 * chapter 4.5.2.2.8.1 (Attached.SRC Requirements)
+	 * Enable VCONN only if the non-RD port is set to RA.
+	 */
+	if ((polarity == TYPEC_POLARITY_CC1 && port->cc2 == TYPEC_CC_RA) ||
+	    (polarity == TYPEC_POLARITY_CC2 && port->cc1 == TYPEC_CC_RA)) {
+		ret = tcpm_set_vconn(dev, true);
+		if (ret < 0)
+			goto out_disable_pd;
+	}
+
+	ret = tcpm_set_vbus(dev, true);
+	if (ret < 0)
+		goto out_disable_vconn;
+
+	port->pd_capable = false;
+
+	port->partner = NULL;
+
+	port->attached = true;
+
+	return 0;
+
+out_disable_vconn:
+	tcpm_set_vconn(dev, false);
+out_disable_pd:
+	drvops->set_pd_rx(dev, false);
+out_disable_mux:
+	dev_err(dev, "TCPM: CC connected in %s as DFP\n",
+		polarity ? "CC2" : "CC1");
+	return 0;
+}
+
+static inline void tcpm_typec_disconnect(struct tcpm_port *port)
+{
+	if (port->connected) {
+		port->partner = NULL;
+		port->connected = false;
+	}
+}
+
+static void tcpm_reset_port(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	tcpm_timer_uninit(dev);
+	tcpm_typec_disconnect(port);
+	tcpm_reset_event_cnt(dev);
+	port->wait_dr_swap_message = false;
+	port->attached = false;
+	port->pd_capable = false;
+
+	/*
+	 * First Rx ID should be 0; set this to a sentinel of -1 so that
+	 * we can check tcpm_pd_rx_handler() if we had seen it before.
+	 */
+	port->rx_msgid = -1;
+
+	drvops->set_pd_rx(dev, false);
+	tcpm_init_vbus(dev);	/* also disables charging */
+	tcpm_init_vconn(dev);
+	tcpm_set_current_limit(dev, 0, 0);
+	tcpm_set_polarity(dev, TYPEC_POLARITY_CC1);
+	tcpm_set_attached_state(dev, false);
+	port->nr_sink_caps = 0;
+}
+
+static void tcpm_detach(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	if (tcpm_port_is_disconnected(port))
+		port->hard_reset_count = 0;
+
+	if (!port->attached)
+		return;
+
+	tcpm_reset_port(dev);
+}
+
+static void tcpm_src_detach(struct udevice *dev)
+{
+	tcpm_detach(dev);
+}
+
+static int tcpm_snk_attach(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	if (port->attached)
+		return 0;
+
+	ret = tcpm_set_polarity(dev, port->cc2 != TYPEC_CC_OPEN ?
+				TYPEC_POLARITY_CC2 : TYPEC_POLARITY_CC1);
+	if (ret < 0)
+		return ret;
+
+	ret = tcpm_set_roles(dev, true, TYPEC_SINK, TYPEC_DEVICE);
+	if (ret < 0)
+		return ret;
+
+	port->pd_capable = false;
+
+	port->partner = NULL;
+
+	port->attached = true;
+	dev_info(dev, "TCPM: CC connected in %s as UFP\n",
+		 port->cc1 != TYPEC_CC_OPEN ? "CC1" : "CC2");
+
+	return 0;
+}
+
+static void tcpm_snk_detach(struct udevice *dev)
+{
+	tcpm_detach(dev);
+}
+
+static inline enum tcpm_state hard_reset_state(struct tcpm_port *port)
+{
+	if (port->hard_reset_count < PD_N_HARD_RESET_COUNT)
+		return HARD_RESET_SEND;
+	if (port->pd_capable)
+		return ERROR_RECOVERY;
+	if (port->pwr_role == TYPEC_SOURCE)
+		return SRC_UNATTACHED;
+	if (port->state == SNK_WAIT_CAPABILITIES)
+		return SNK_READY;
+	return SNK_UNATTACHED;
+}
+
+static inline enum tcpm_state unattached_state(struct tcpm_port *port)
+{
+	if (port->port_type == TYPEC_PORT_DRP) {
+		if (port->pwr_role == TYPEC_SOURCE)
+			return SRC_UNATTACHED;
+		else
+			return SNK_UNATTACHED;
+	} else if (port->port_type == TYPEC_PORT_SRC) {
+		return SRC_UNATTACHED;
+	}
+
+	return SNK_UNATTACHED;
+}
+
+static void run_state_machine(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int ret;
+
+	port->enter_state = port->state;
+	switch (port->state) {
+	case TOGGLING:
+		break;
+	/* SRC states */
+	case SRC_UNATTACHED:
+		tcpm_src_detach(dev);
+		if (tcpm_start_toggling(dev, tcpm_rp_cc(port))) {
+			tcpm_set_state(dev, TOGGLING, 0);
+			break;
+		}
+		tcpm_set_cc(dev, tcpm_rp_cc(port));
+		if (port->port_type == TYPEC_PORT_DRP)
+			tcpm_set_state(dev, SNK_UNATTACHED, PD_T_DRP_SNK);
+		break;
+	case SRC_ATTACH_WAIT:
+		if (tcpm_port_is_source(port))
+			tcpm_set_state(dev, SRC_ATTACHED, PD_T_CC_DEBOUNCE);
+		break;
+
+	case SRC_ATTACHED:
+		ret = tcpm_src_attach(dev);
+		/*
+		 * Currently, vbus control is not implemented,
+		 * and the SRC detection process cannot be fully implemented.
+		 */
+		tcpm_set_state(dev, SRC_READY, 0);
+		break;
+	case SRC_STARTUP:
+		port->caps_count = 0;
+		port->negotiated_rev = PD_MAX_REV;
+		port->message_id = 0;
+		port->rx_msgid = -1;
+		port->explicit_contract = false;
+		tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0);
+		break;
+	case SRC_SEND_CAPABILITIES:
+		port->caps_count++;
+		if (port->caps_count > PD_N_CAPS_COUNT) {
+			tcpm_set_state(dev, SRC_READY, 0);
+			break;
+		}
+		ret = tcpm_pd_send_source_caps(dev);
+		if (ret < 0) {
+			tcpm_set_state(dev, SRC_SEND_CAPABILITIES,
+				       PD_T_SEND_SOURCE_CAP);
+		} else {
+			/*
+			 * Per standard, we should clear the reset counter here.
+			 * However, that can result in state machine hang-ups.
+			 * Reset it only in READY state to improve stability.
+			 */
+			/* port->hard_reset_count = 0; */
+			port->caps_count = 0;
+			port->pd_capable = true;
+			tcpm_set_state_cond(dev, SRC_SEND_CAPABILITIES_TIMEOUT,
+					    PD_T_SEND_SOURCE_CAP);
+		}
+		break;
+	case SRC_SEND_CAPABILITIES_TIMEOUT:
+		/*
+		 * Error recovery for a PD_DATA_SOURCE_CAP reply timeout.
+		 *
+		 * PD 2.0 sinks are supposed to accept src-capabilities with a
+		 * 3.0 header and simply ignore any src PDOs which the sink does
+		 * not understand such as PPS but some 2.0 sinks instead ignore
+		 * the entire PD_DATA_SOURCE_CAP message, causing contract
+		 * negotiation to fail.
+		 *
+		 * After PD_N_HARD_RESET_COUNT hard-reset attempts, we try
+		 * sending src-capabilities with a lower PD revision to
+		 * make these broken sinks work.
+		 */
+		if (port->hard_reset_count < PD_N_HARD_RESET_COUNT) {
+			tcpm_set_state(dev, HARD_RESET_SEND, 0);
+		} else if (port->negotiated_rev > PD_REV20) {
+			port->negotiated_rev--;
+			port->hard_reset_count = 0;
+			tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0);
+		} else {
+			tcpm_set_state(dev, hard_reset_state(port), 0);
+		}
+		break;
+	case SRC_NEGOTIATE_CAPABILITIES:
+		ret = tcpm_pd_check_request(dev);
+		if (ret < 0) {
+			tcpm_pd_send_control(dev, PD_CTRL_REJECT);
+			if (!port->explicit_contract) {
+				tcpm_set_state(dev,
+					       SRC_WAIT_NEW_CAPABILITIES, 0);
+			} else {
+				tcpm_set_state(dev, SRC_READY, 0);
+			}
+		} else {
+			tcpm_pd_send_control(dev, PD_CTRL_ACCEPT);
+			tcpm_set_state(dev, SRC_TRANSITION_SUPPLY,
+				       PD_T_SRC_TRANSITION);
+		}
+		break;
+	case SRC_TRANSITION_SUPPLY:
+		/* XXX: regulator_set_voltage(vbus, ...) */
+		tcpm_pd_send_control(dev, PD_CTRL_PS_RDY);
+		port->explicit_contract = true;
+		tcpm_set_state_cond(dev, SRC_READY, 0);
+		break;
+	case SRC_READY:
+		port->hard_reset_count = 0;
+
+		tcpm_typec_connect(port);
+		break;
+	case SRC_WAIT_NEW_CAPABILITIES:
+		/* Nothing to do... */
+		break;
+
+	/* SNK states */
+	case SNK_UNATTACHED:
+		tcpm_snk_detach(dev);
+		if (tcpm_start_toggling(dev, TYPEC_CC_RD)) {
+			tcpm_set_state(dev, TOGGLING, 0);
+			break;
+		}
+		tcpm_set_cc(dev, TYPEC_CC_RD);
+		if (port->port_type == TYPEC_PORT_DRP)
+			tcpm_set_state(dev, SRC_UNATTACHED, PD_T_DRP_SRC);
+		break;
+	case SNK_ATTACH_WAIT:
+		if ((port->cc1 == TYPEC_CC_OPEN &&
+		     port->cc2 != TYPEC_CC_OPEN) ||
+		    (port->cc1 != TYPEC_CC_OPEN &&
+		     port->cc2 == TYPEC_CC_OPEN))
+			tcpm_set_state(dev, SNK_DEBOUNCED,
+				       PD_T_CC_DEBOUNCE);
+		else if (tcpm_port_is_disconnected(port))
+			tcpm_set_state(dev, SNK_UNATTACHED,
+				       PD_T_CC_DEBOUNCE);
+		break;
+	case SNK_DEBOUNCED:
+		if (tcpm_port_is_disconnected(port))
+			tcpm_set_state(dev, SNK_UNATTACHED, PD_T_PD_DEBOUNCE);
+		else if (port->vbus_present)
+			tcpm_set_state(dev, SNK_ATTACHED, 0);
+		else
+			/* Wait for VBUS, but not forever */
+			tcpm_set_state(dev, PORT_RESET, PD_T_PS_SOURCE_ON);
+		break;
+	case SNK_ATTACHED:
+		ret = tcpm_snk_attach(dev);
+		if (ret < 0)
+			tcpm_set_state(dev, SNK_UNATTACHED, 0);
+		else
+			tcpm_set_state(dev, SNK_STARTUP, 0);
+		break;
+	case SNK_STARTUP:
+		port->negotiated_rev = PD_MAX_REV;
+		port->message_id = 0;
+		port->rx_msgid = -1;
+		port->explicit_contract = false;
+		tcpm_set_state(dev, SNK_DISCOVERY, 0);
+		break;
+	case SNK_DISCOVERY:
+		if (port->vbus_present) {
+			tcpm_set_current_limit(dev,
+					       tcpm_get_current_limit(port),
+					       5000);
+			tcpm_set_charge(dev, true);
+			tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0);
+			break;
+		}
+		/*
+		 * For DRP, timeouts differ. Also, handling is supposed to be
+		 * different and much more complex (dead battery detection;
+		 * see USB power delivery specification, section 8.3.3.6.1.5.1).
+		 */
+		tcpm_set_state(dev, hard_reset_state(port),
+			       port->port_type == TYPEC_PORT_DRP ?
+					PD_T_DB_DETECT : PD_T_NO_RESPONSE);
+		break;
+	case SNK_DISCOVERY_DEBOUNCE:
+		tcpm_set_state(dev, SNK_DISCOVERY_DEBOUNCE_DONE,
+			       PD_T_CC_DEBOUNCE);
+		break;
+	case SNK_DISCOVERY_DEBOUNCE_DONE:
+		tcpm_set_state(dev, unattached_state(port), 0);
+		break;
+	case SNK_WAIT_CAPABILITIES:
+		ret = drvops->set_pd_rx(dev, true);
+		if (ret < 0) {
+			tcpm_set_state(dev, SNK_READY, 0);
+			break;
+		}
+		/*
+		 * If VBUS has never been low, and we time out waiting
+		 * for source cap, try a soft reset first, in case we
+		 * were already in a stable contract before this boot.
+		 * Do this only once.
+		 */
+		if (port->vbus_never_low) {
+			port->vbus_never_low = false;
+			tcpm_set_state(dev, SOFT_RESET_SEND,
+				       PD_T_SINK_WAIT_CAP);
+		} else {
+			tcpm_set_state(dev, hard_reset_state(port),
+				       PD_T_SINK_WAIT_CAP);
+		}
+		break;
+	case SNK_NEGOTIATE_CAPABILITIES:
+		port->pd_capable = true;
+		port->hard_reset_count = 0;
+		ret = tcpm_pd_send_request(dev);
+		if (ret < 0) {
+			/* Let the Source send capabilities again. */
+			tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0);
+		} else {
+			tcpm_set_state_cond(dev, hard_reset_state(port),
+					    PD_T_SENDER_RESPONSE);
+		}
+		break;
+	case SNK_TRANSITION_SINK:
+	case SNK_TRANSITION_SINK_VBUS:
+		tcpm_set_state(dev, hard_reset_state(port),
+			       PD_T_PS_TRANSITION);
+		break;
+	case SNK_READY:
+		port->update_sink_caps = false;
+		tcpm_typec_connect(port);
+		/*
+		 * Here poll_event_cnt is cleared, waiting for self-powered Type-C devices
+		 * to send DR_swap Messge until 1s (TCPM_POLL_EVENT_TIME_OUT * 500us)timeout
+		 */
+		if (port->wait_dr_swap_message)
+			tcpm_reset_event_cnt(dev);
+
+		break;
+
+	/* Hard_Reset states */
+	case HARD_RESET_SEND:
+		tcpm_pd_transmit(dev, TCPC_TX_HARD_RESET, NULL);
+		tcpm_set_state(dev, HARD_RESET_START, 0);
+		port->wait_dr_swap_message = false;
+		break;
+	case HARD_RESET_START:
+		port->hard_reset_count++;
+		drvops->set_pd_rx(dev, false);
+		port->nr_sink_caps = 0;
+		if (port->pwr_role == TYPEC_SOURCE)
+			tcpm_set_state(dev, SRC_HARD_RESET_VBUS_OFF,
+				       PD_T_PS_HARD_RESET);
+		else
+			tcpm_set_state(dev, SNK_HARD_RESET_SINK_OFF, 0);
+		break;
+	case SRC_HARD_RESET_VBUS_OFF:
+		tcpm_set_vconn(dev, true);
+		tcpm_set_vbus(dev, false);
+		tcpm_set_roles(dev, port->self_powered, TYPEC_SOURCE,
+			       TYPEC_HOST);
+		tcpm_set_state(dev, SRC_HARD_RESET_VBUS_ON, PD_T_SRC_RECOVER);
+		break;
+	case SRC_HARD_RESET_VBUS_ON:
+		tcpm_set_vconn(dev, true);
+		tcpm_set_vbus(dev, true);
+		drvops->set_pd_rx(dev, true);
+		tcpm_set_attached_state(dev, true);
+		tcpm_set_state(dev, SRC_UNATTACHED, PD_T_PS_SOURCE_ON);
+		break;
+	case SNK_HARD_RESET_SINK_OFF:
+		tcpm_set_vconn(dev, false);
+		if (port->pd_capable)
+			tcpm_set_charge(dev, false);
+		tcpm_set_roles(dev, port->self_powered, TYPEC_SINK,
+			       TYPEC_DEVICE);
+		/*
+		 * VBUS may or may not toggle, depending on the adapter.
+		 * If it doesn't toggle, transition to SNK_HARD_RESET_SINK_ON
+		 * directly after timeout.
+		 */
+		tcpm_set_state(dev, SNK_HARD_RESET_SINK_ON, PD_T_SAFE_0V);
+		break;
+	case SNK_HARD_RESET_WAIT_VBUS:
+		/* Assume we're disconnected if VBUS doesn't come back. */
+		tcpm_set_state(dev, SNK_UNATTACHED,
+			       PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON);
+		break;
+	case SNK_HARD_RESET_SINK_ON:
+		/* Note: There is no guarantee that VBUS is on in this state */
+		/*
+		 * XXX:
+		 * The specification suggests that dual mode ports in sink
+		 * mode should transition to state PE_SRC_Transition_to_default.
+		 * See USB power delivery specification chapter 8.3.3.6.1.3.
+		 * This would mean to
+		 * - turn off VCONN, reset power supply
+		 * - request hardware reset
+		 * - turn on VCONN
+		 * - Transition to state PE_Src_Startup
+		 * SNK only ports shall transition to state Snk_Startup
+		 * (see chapter 8.3.3.3.8).
+		 * Similar, dual-mode ports in source mode should transition
+		 * to PE_SNK_Transition_to_default.
+		 */
+		if (port->pd_capable) {
+			tcpm_set_current_limit(dev,
+					       tcpm_get_current_limit(port),
+					       5000);
+			tcpm_set_charge(dev, true);
+		}
+		tcpm_set_attached_state(dev, true);
+		tcpm_set_state(dev, SNK_STARTUP, 0);
+		break;
+
+	/* Soft_Reset states */
+	case SOFT_RESET:
+		port->message_id = 0;
+		port->rx_msgid = -1;
+		tcpm_pd_send_control(dev, PD_CTRL_ACCEPT);
+		if (port->pwr_role == TYPEC_SOURCE)
+			tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0);
+		else
+			tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0);
+		break;
+	case SOFT_RESET_SEND:
+		port->message_id = 0;
+		port->rx_msgid = -1;
+		if (tcpm_pd_send_control(dev, PD_CTRL_SOFT_RESET))
+			tcpm_set_state_cond(dev, hard_reset_state(port), 0);
+		else
+			tcpm_set_state_cond(dev, hard_reset_state(port),
+					    PD_T_SENDER_RESPONSE);
+		break;
+
+	/* DR_Swap states */
+	case DR_SWAP_ACCEPT:
+		tcpm_pd_send_control(dev, PD_CTRL_ACCEPT);
+		tcpm_set_state_cond(dev, DR_SWAP_CHANGE_DR, 0);
+		break;
+	case DR_SWAP_CHANGE_DR:
+		if (port->data_role == TYPEC_HOST) {
+			tcpm_set_roles(dev, true, port->pwr_role,
+				       TYPEC_DEVICE);
+		} else {
+			tcpm_set_roles(dev, true, port->pwr_role,
+				       TYPEC_HOST);
+		}
+		/* DR_swap process complete, wait_dr_swap_message is cleared */
+		port->wait_dr_swap_message = false;
+		tcpm_set_state(dev, ready_state(port), 0);
+		break;
+	case ERROR_RECOVERY:
+		tcpm_set_state(dev, PORT_RESET, 0);
+		break;
+	case PORT_RESET:
+		tcpm_reset_port(dev);
+		if (port->self_powered)
+			tcpm_set_cc(dev, TYPEC_CC_OPEN);
+		else
+			tcpm_set_cc(dev, tcpm_default_state(port) == SNK_UNATTACHED ?
+				    TYPEC_CC_RD : tcpm_rp_cc(port));
+		tcpm_set_state(dev, PORT_RESET_WAIT_OFF,
+			       PD_T_ERROR_RECOVERY);
+		break;
+	case PORT_RESET_WAIT_OFF:
+		tcpm_set_state(dev,
+			       tcpm_default_state(port),
+			       port->vbus_present ? PD_T_PS_SOURCE_OFF : 0);
+		break;
+	default:
+		dev_err(dev, "TCPM: Unexpected port state %d\n", port->state);
+		break;
+	}
+}
+
+static void tcpm_state_machine(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	enum tcpm_state prev_state;
+
+	mutex_lock(&port->lock);
+	port->state_machine_running = true;
+
+	if (port->queued_message && tcpm_send_queued_message(dev))
+		goto done;
+
+	/* If we were queued due to a delayed state change, update it now */
+	if (port->delayed_state) {
+		dev_dbg(dev, "TCPM: state change %s -> %s [delayed %ld ms]\n",
+			tcpm_states[port->state],
+			tcpm_states[port->delayed_state], port->delay_ms);
+		port->prev_state = port->state;
+		port->state = port->delayed_state;
+		port->delayed_state = INVALID_STATE;
+	}
+
+	/*
+	 * Continue running as long as we have (non-delayed) state changes
+	 * to make.
+	 */
+	do {
+		prev_state = port->state;
+		run_state_machine(dev);
+		if (port->queued_message)
+			tcpm_send_queued_message(dev);
+	} while (port->state != prev_state && !port->delayed_state);
+
+done:
+	port->state_machine_running = false;
+	mutex_unlock(&port->lock);
+}
+
+static void _tcpm_cc_change(struct udevice *dev, enum typec_cc_status cc1,
+			    enum typec_cc_status cc2)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	enum typec_cc_status old_cc1, old_cc2;
+	enum tcpm_state new_state;
+
+	old_cc1 = port->cc1;
+	old_cc2 = port->cc2;
+	port->cc1 = cc1;
+	port->cc2 = cc2;
+
+	dev_dbg(dev, "TCPM: CC1: %u -> %u, CC2: %u -> %u [state %s, polarity %d, %s]\n",
+		old_cc1, cc1, old_cc2, cc2, tcpm_states[port->state],
+		port->polarity,
+		tcpm_port_is_disconnected(port) ? "disconnected" : "connected");
+
+	switch (port->state) {
+	case TOGGLING:
+		if (tcpm_port_is_source(port))
+			tcpm_set_state(dev, SRC_ATTACH_WAIT, 0);
+		else if (tcpm_port_is_sink(port))
+			tcpm_set_state(dev, SNK_ATTACH_WAIT, 0);
+		break;
+	case SRC_UNATTACHED:
+	case SRC_ATTACH_WAIT:
+		if (tcpm_port_is_disconnected(port))
+			tcpm_set_state(dev, SRC_UNATTACHED, 0);
+		else if (cc1 != old_cc1 || cc2 != old_cc2)
+			tcpm_set_state(dev, SRC_ATTACH_WAIT, 0);
+		break;
+	case SRC_ATTACHED:
+	case SRC_SEND_CAPABILITIES:
+	case SRC_READY:
+		if (tcpm_port_is_disconnected(port) ||
+		    !tcpm_port_is_source(port))
+			tcpm_set_state(dev, SRC_UNATTACHED, 0);
+		break;
+	case SNK_UNATTACHED:
+		if (tcpm_port_is_sink(port))
+			tcpm_set_state(dev, SNK_ATTACH_WAIT, 0);
+		break;
+	case SNK_ATTACH_WAIT:
+		if ((port->cc1 == TYPEC_CC_OPEN &&
+		     port->cc2 != TYPEC_CC_OPEN) ||
+		    (port->cc1 != TYPEC_CC_OPEN &&
+		     port->cc2 == TYPEC_CC_OPEN))
+			new_state = SNK_DEBOUNCED;
+		else if (tcpm_port_is_disconnected(port))
+			new_state = SNK_UNATTACHED;
+		else
+			break;
+		if (new_state != port->delayed_state)
+			tcpm_set_state(dev, SNK_ATTACH_WAIT, 0);
+		break;
+	case SNK_DEBOUNCED:
+		if (tcpm_port_is_disconnected(port))
+			new_state = SNK_UNATTACHED;
+		else if (port->vbus_present)
+			new_state = tcpm_try_src(port) ? INVALID_STATE : SNK_ATTACHED;
+		else
+			new_state = SNK_UNATTACHED;
+		if (new_state != port->delayed_state)
+			tcpm_set_state(dev, SNK_DEBOUNCED, 0);
+		break;
+	case SNK_READY:
+		if (tcpm_port_is_disconnected(port))
+			tcpm_set_state(dev, unattached_state(port), 0);
+		else if (!port->pd_capable &&
+			 (cc1 != old_cc1 || cc2 != old_cc2))
+			tcpm_set_current_limit(dev,
+					       tcpm_get_current_limit(port),
+					       5000);
+		break;
+
+	case SNK_DISCOVERY:
+		/* CC line is unstable, wait for debounce */
+		if (tcpm_port_is_disconnected(port))
+			tcpm_set_state(dev, SNK_DISCOVERY_DEBOUNCE, 0);
+		break;
+	case SNK_DISCOVERY_DEBOUNCE:
+		break;
+
+	case PORT_RESET:
+	case PORT_RESET_WAIT_OFF:
+		/*
+		 * State set back to default mode once the timer completes.
+		 * Ignore CC changes here.
+		 */
+		break;
+	default:
+		/*
+		 * While acting as sink and auto vbus discharge is enabled, Allow disconnect
+		 * to be driven by vbus disconnect.
+		 */
+		if (tcpm_port_is_disconnected(port))
+			tcpm_set_state(dev, unattached_state(port), 0);
+		break;
+	}
+}
+
+static void _tcpm_pd_vbus_on(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	dev_dbg(dev, "TCPM: VBUS on event\n");
+	port->vbus_present = true;
+	/*
+	 * When vbus_present is true i.e. Voltage at VBUS is greater than VSAFE5V implicitly
+	 * states that vbus is not at VSAFE0V, hence clear the vbus_vsafe0v flag here.
+	 */
+	port->vbus_vsafe0v = false;
+
+	switch (port->state) {
+	case SNK_TRANSITION_SINK_VBUS:
+		port->explicit_contract = true;
+		tcpm_set_state(dev, SNK_READY, 0);
+		break;
+	case SNK_DISCOVERY:
+		tcpm_set_state(dev, SNK_DISCOVERY, 0);
+		break;
+	case SNK_DEBOUNCED:
+		tcpm_set_state(dev, SNK_ATTACHED, 0);
+		break;
+	case SNK_HARD_RESET_WAIT_VBUS:
+		tcpm_set_state(dev, SNK_HARD_RESET_SINK_ON, 0);
+		break;
+	case SRC_ATTACHED:
+		tcpm_set_state(dev, SRC_STARTUP, 0);
+		break;
+	case SRC_HARD_RESET_VBUS_ON:
+		tcpm_set_state(dev, SRC_STARTUP, 0);
+		break;
+
+	case PORT_RESET:
+	case PORT_RESET_WAIT_OFF:
+		/*
+		 * State set back to default mode once the timer completes.
+		 * Ignore vbus changes here.
+		 */
+		break;
+
+	default:
+		break;
+	}
+}
+
+static void _tcpm_pd_vbus_off(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	dev_dbg(dev, "TCPM: VBUS off event\n");
+	port->vbus_present = false;
+	port->vbus_never_low = false;
+	switch (port->state) {
+	case SNK_HARD_RESET_SINK_OFF:
+		tcpm_set_state(dev, SNK_HARD_RESET_WAIT_VBUS, 0);
+		break;
+	case HARD_RESET_SEND:
+		break;
+	case SNK_ATTACH_WAIT:
+		tcpm_set_state(dev, SNK_UNATTACHED, 0);
+		break;
+
+	case SNK_NEGOTIATE_CAPABILITIES:
+		break;
+
+	case PORT_RESET_WAIT_OFF:
+		tcpm_set_state(dev, tcpm_default_state(port), 0);
+		break;
+
+	case PORT_RESET:
+		/*
+		 * State set back to default mode once the timer completes.
+		 * Ignore vbus changes here.
+		 */
+		break;
+
+	default:
+		if (port->pwr_role == TYPEC_SINK && port->attached)
+			tcpm_set_state(dev, SNK_UNATTACHED, 0);
+		break;
+	}
+}
+
+void tcpm_cc_change(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	enum typec_cc_status cc1, cc2;
+
+	tcpm_reset_event_cnt(dev);
+	if (drvops->get_cc(dev, &cc1, &cc2) == 0)
+		_tcpm_cc_change(dev, cc1, cc2);
+}
+
+void tcpm_vbus_change(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	bool vbus;
+
+	tcpm_reset_event_cnt(dev);
+	vbus = drvops->get_vbus(dev);
+	if (vbus)
+		_tcpm_pd_vbus_on(dev);
+	else
+		_tcpm_pd_vbus_off(dev);
+}
+
+void tcpm_pd_hard_reset(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	tcpm_reset_event_cnt(dev);
+	dev_dbg(dev, "TCPM: Received hard reset\n");
+
+	/* If a hard reset message is received during the port reset process,
+	 * we should ignore it, that is, do not set port->state to HARD_RESET_START.
+	 */
+	if (port->state == PORT_RESET || port->state == PORT_RESET_WAIT_OFF)
+		return;
+
+	/*
+	 * If we keep receiving hard reset requests, executing the hard reset
+	 * must have failed. Revert to error recovery if that happens.
+	 */
+	tcpm_set_state(dev,
+		       port->hard_reset_count < PD_N_HARD_RESET_COUNT ?
+				HARD_RESET_START : ERROR_RECOVERY,
+		       0);
+}
+
+static void tcpm_init(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	enum typec_cc_status cc1, cc2;
+
+	drvops->init(dev);
+
+	tcpm_reset_port(dev);
+
+	/*
+	 * XXX
+	 * Should possibly wait for VBUS to settle if it was enabled locally
+	 * since tcpm_reset_port() will disable VBUS.
+	 */
+	port->vbus_present = drvops->get_vbus(dev);
+	if (port->vbus_present)
+		port->vbus_never_low = true;
+
+	/*
+	 * 1. When vbus_present is true, voltage on VBUS is already at VSAFE5V.
+	 * So implicitly vbus_vsafe0v = false.
+	 *
+	 * 2. When vbus_present is false and TCPC does NOT support querying
+	 * vsafe0v status, then, it's best to assume vbus is at VSAFE0V i.e.
+	 * vbus_vsafe0v is true.
+	 *
+	 * 3. When vbus_present is false and TCPC does support querying vsafe0v,
+	 * then, query tcpc for vsafe0v status.
+	 */
+	if (port->vbus_present)
+		port->vbus_vsafe0v = false;
+	else
+		port->vbus_vsafe0v = true;
+
+	tcpm_set_state(dev, tcpm_default_state(port), 0);
+
+	if (drvops->get_cc(dev, &cc1, &cc2) == 0)
+		_tcpm_cc_change(dev, cc1, cc2);
+}
+
+static int tcpm_fw_get_caps(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	ofnode node;
+	const char *cap_str;
+	int ret;
+	u32 mw;
+
+	ret = drvops->get_connector_node(dev, &node);
+	if (ret)
+		return ret;
+
+	cap_str = ofnode_read_string(node, "power-role");
+	if (!cap_str)
+		return -EINVAL;
+
+	if (!strcmp("dual", cap_str))
+		port->typec_type = TYPEC_PORT_DRP;
+	else if (!strcmp("source", cap_str))
+		port->typec_type = TYPEC_PORT_SRC;
+	else if (!strcmp("sink", cap_str))
+		port->typec_type = TYPEC_PORT_SNK;
+	else
+		return -EINVAL;
+
+	port->port_type = port->typec_type;
+
+	if (port->port_type == TYPEC_PORT_SNK)
+		goto sink;
+
+	/* Get source pdos */
+	ret = ofnode_read_size(node, "source-pdos") / sizeof(u32);
+	if (ret <= 0)
+		return -EINVAL;
+
+	port->nr_src_pdo = min(ret, PDO_MAX_OBJECTS);
+	ret = ofnode_read_u32_array(node, "source-pdos",
+				    port->src_pdo, port->nr_src_pdo);
+	if (ret || tcpm_validate_caps(dev, port->src_pdo, port->nr_src_pdo))
+		return -EINVAL;
+
+	if (port->port_type == TYPEC_PORT_SRC)
+		return 0;
+
+	/* Get the preferred power role for DRP */
+	cap_str = ofnode_read_string(node, "try-power-role");
+	if (!cap_str)
+		return -EINVAL;
+
+	if (!strcmp("sink", cap_str))
+		port->typec_prefer_role = TYPEC_SINK;
+	else if (!strcmp("source", cap_str))
+		port->typec_prefer_role = TYPEC_SOURCE;
+	else
+		return -EINVAL;
+
+	if (port->typec_prefer_role < 0)
+		return -EINVAL;
+sink:
+	/* Get sink pdos */
+	ret = ofnode_read_size(node, "sink-pdos") / sizeof(u32);
+	if (ret <= 0)
+		return -EINVAL;
+
+	port->nr_snk_pdo = min(ret, PDO_MAX_OBJECTS);
+	ret = ofnode_read_u32_array(node, "sink-pdos",
+				    port->snk_pdo, port->nr_snk_pdo);
+	if (ret || tcpm_validate_caps(dev, port->snk_pdo, port->nr_snk_pdo))
+		return -EINVAL;
+
+	if (ofnode_read_u32_array(node, "op-sink-microwatt", &mw, 1))
+		return -EINVAL;
+	port->operating_snk_mw = mw / 1000;
+
+	port->self_powered = ofnode_read_bool(node, "self-powered");
+
+	return 0;
+}
+
+static int tcpm_port_init(struct udevice *dev)
+{
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+	int err;
+
+	err = tcpm_fw_get_caps(dev);
+	if (err < 0) {
+		dev_err(dev, "TCPM: please check the dts config: %d\n", err);
+		return err;
+	}
+
+	port->try_role = port->typec_prefer_role;
+	port->port_type = port->typec_type;
+
+	tcpm_init(dev);
+
+	dev_info(dev, "TCPM: init finished\n");
+
+	return 0;
+}
+
+static void tcpm_poll_event(struct udevice *dev)
+{
+	const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+	struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+	if (!drvops->get_vbus(dev))
+		return;
+
+	while (port->poll_event_cnt < TCPM_POLL_EVENT_TIME_OUT) {
+		if (!port->wait_dr_swap_message &&
+		    (port->state == SNK_READY || port->state == SRC_READY))
+			break;
+
+		drvops->poll_event(dev);
+		port->poll_event_cnt++;
+		udelay(500);
+		tcpm_check_and_run_delayed_work(dev);
+	}
+
+	if (port->state != SNK_READY && port->state != SRC_READY)
+		dev_warn(dev, "TCPM: exit in state %s\n",
+			 tcpm_states[port->state]);
+
+	/*
+	 * At this time, call the callback function of the respective pd chip
+	 * to enter the low-power mode. In order to reduce the time spent on
+	 * the PD chip driver as much as possible, the tcpm framework does not
+	 * fully process the communication initiated by the device,so it should
+	 * be noted that we can disable the internal oscillator, etc., but do
+	 * not turn off the power of the transceiver module, otherwise the
+	 * self-powered Type-C device will initiate a Message(eg: self-powered
+	 * Type-C hub initiates a SINK capability request(PD_CTRL_GET_SINK_CAP))
+	 * and the pd chip cannot reply to GoodCRC, causing the self-powered Type-C
+	 * device to switch vbus to vSafe5v, or even turn off vbus.
+	 */
+	if (!drvops->enter_low_power_mode)
+		return;
+
+	if (drvops->enter_low_power_mode(dev, port->attached, port->pd_capable))
+		dev_err(dev, "TCPM: failed to enter low power\n");
+	else
+		dev_info(dev, "TCPM: PD chip enter low power mode\n");
+}
+
+int tcpm_post_probe(struct udevice *dev)
+{
+	int ret = tcpm_port_init(dev);
+
+	if (ret < 0) {
+		dev_err(dev, "failed to tcpm port init\n");
+		return ret;
+	}
+
+	tcpm_poll_event(dev);
+
+	return 0;
+}
diff --git a/dts/Kconfig b/dts/Kconfig
index 385058b..ffd50c04 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -242,11 +242,11 @@
 
 config OF_OVERLAY_LIST
 	string "List of device tree overlays to include for DT control"
-	depends on SPL_LOAD_FIT_APPLY_OVERLAY
 	help
 	  This option specifies a list of device tree overlays to use for DT
 	  control. This option can then be used by a FIT generator to include
-	  the overlays in the FIT image.
+	  the overlays in the FIT image or by binman when assembling an image
+	  that uses overlays during DT fixup.
 
 choice
 	prompt "OF LIST compression"
diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index 5b0658c..3e3f49a 100644
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h
@@ -21,8 +21,6 @@
  */
 #define CFG_SYS_BOOTMAPSZ		SZ_256M
 
-/* NAND support */
-
 /*****************************************************************************/
 #ifdef CONFIG_DISTRO_DEFAULTS
 /*****************************************************************************/
diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h
index af6dd4a..9cac31b 100644
--- a/include/configs/stm32mp15_common.h
+++ b/include/configs/stm32mp15_common.h
@@ -21,10 +21,6 @@
  */
 #define CFG_SYS_BOOTMAPSZ		SZ_256M
 
-/* NAND support */
-
-/* Ethernet need */
-
 #define STM32MP_FIP_IMAGE_GUID \
 	EFI_GUID(0x19d5df83, 0x11b0, 0x457b, 0xbe, 0x2c, \
 		 0x75, 0x59, 0xc1, 0x31, 0x42, 0xa5)
diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h
index 0f46671..2797fc6 100644
--- a/include/configs/stm32mp15_dh_dhsom.h
+++ b/include/configs/stm32mp15_dh_dhsom.h
@@ -37,16 +37,26 @@
 		"setenv loadaddr1 && "					\
 		"setenv sblkcnt && "					\
 		"setenv ublkcnt\0"					\
-	"dh_update_sd_to_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+	"dh_update_block_to_sf=" /* Erase SPI NOR and install U-Boot from block device */ \
 		"setexpr loadaddr1 ${loadaddr} + 0x1000000 && "		\
-		"load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && "	\
+		"load ${dh_update_iface} ${dh_update_dev} "		\
+			"${loadaddr1} /boot/u-boot-spl.stm32 && "	\
 		"env set filesize1 ${filesize} && "			\
-		"load mmc 0:4 ${loadaddr} /boot/u-boot.itb && "		\
+		"load ${dh_update_iface} ${dh_update_dev} "		\
+			"${loadaddr} /boot/u-boot.itb && "		\
 		"sf probe && sf erase 0 0x200000 && "			\
 		"sf update ${loadaddr1} 0 ${filesize1} && "		\
 		"sf update ${loadaddr1} 0x40000 ${filesize1} && "	\
 		"sf update ${loadaddr} 0x80000 ${filesize} && "		\
 		"env set filesize1 && env set loadaddr1\0"		\
+	"dh_update_sd_to_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+		"setenv dh_update_iface mmc && "			\
+		"setenv dh_update_dev 0:4 && "				\
+		"run dh_update_block_to_sf\0"				\
+	"dh_update_emmc_to_sf=" /* Erase SPI NOR and install U-Boot from eMMC */ \
+		"setenv dh_update_iface mmc && "			\
+		"setenv dh_update_dev 1:4 && "				\
+		"run dh_update_block_to_sf\0"				\
 	"stdin=serial\0"						\
 	"stdout=serial\0"						\
 	"stderr=serial\0"						\
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 5271e64..270088a 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -139,6 +139,7 @@
 	UCLASS_SYSCON,		/* System configuration device */
 	UCLASS_SYSINFO,		/* Device information from hardware */
 	UCLASS_SYSRESET,	/* System reset device */
+	UCLASS_TCPM,		/* TypeC port manager */
 	UCLASS_TEE,		/* Trusted Execution Environment device */
 	UCLASS_THERMAL,		/* Thermal sensor */
 	UCLASS_TIMER,		/* Timer device */
diff --git a/include/irq_func.h b/include/irq_func.h
index c7c4bab..fb2c540 100644
--- a/include/irq_func.h
+++ b/include/irq_func.h
@@ -10,6 +10,7 @@
 #define __IRQ_FUNC_H
 
 struct pt_regs;
+struct cmd_tbl;
 
 typedef void (interrupt_handler_t)(void *arg);
 
@@ -23,4 +24,7 @@
 void enable_interrupts(void);
 int disable_interrupts(void);
 
+/* Implemented in $(CPU)/interrupts.c */
+int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+
 #endif
diff --git a/include/serial.h b/include/serial.h
index d129dc3..eabc49f 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -298,9 +298,11 @@
 struct serial_dev_priv {
 	struct stdio_dev *sdev;
 
-	char *buf;
-	int rd_ptr;
-	int wr_ptr;
+#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER)
+	char buf[CONFIG_SERIAL_RX_BUFFER_SIZE];
+	uint rd_ptr;
+	uint wr_ptr;
+#endif
 };
 
 /* Access the serial operations for a device */
diff --git a/include/usb/pd.h b/include/usb/pd.h
new file mode 100644
index 0000000..cacda32
--- /dev/null
+++ b/include/usb/pd.h
@@ -0,0 +1,516 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ */
+
+#ifndef __LINUX_USB_PD_H
+#define __LINUX_USB_PD_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+enum typec_port_type {
+	TYPEC_PORT_SRC,
+	TYPEC_PORT_SNK,
+	TYPEC_PORT_DRP,
+};
+
+enum typec_data_role {
+	TYPEC_DEVICE,
+	TYPEC_HOST,
+};
+
+enum typec_role {
+	TYPEC_SINK,
+	TYPEC_SOURCE,
+};
+
+/* USB PD Messages */
+enum pd_ctrl_msg_type {
+	/* 0 Reserved */
+	PD_CTRL_GOOD_CRC = 1,
+	PD_CTRL_GOTO_MIN = 2,
+	PD_CTRL_ACCEPT = 3,
+	PD_CTRL_REJECT = 4,
+	PD_CTRL_PING = 5,
+	PD_CTRL_PS_RDY = 6,
+	PD_CTRL_GET_SOURCE_CAP = 7,
+	PD_CTRL_GET_SINK_CAP = 8,
+	PD_CTRL_DR_SWAP = 9,
+	PD_CTRL_PR_SWAP = 10,
+	PD_CTRL_VCONN_SWAP = 11,
+	PD_CTRL_WAIT = 12,
+	PD_CTRL_SOFT_RESET = 13,
+	/* 14-15 Reserved */
+	PD_CTRL_NOT_SUPP = 16,
+	PD_CTRL_GET_SOURCE_CAP_EXT = 17,
+	PD_CTRL_GET_STATUS = 18,
+	PD_CTRL_FR_SWAP = 19,
+	PD_CTRL_GET_PPS_STATUS = 20,
+	PD_CTRL_GET_COUNTRY_CODES = 21,
+	/* 22-31 Reserved */
+};
+
+enum pd_data_msg_type {
+	/* 0 Reserved */
+	PD_DATA_SOURCE_CAP = 1,
+	PD_DATA_REQUEST = 2,
+	PD_DATA_BIST = 3,
+	PD_DATA_SINK_CAP = 4,
+	PD_DATA_BATT_STATUS = 5,
+	PD_DATA_ALERT = 6,
+	PD_DATA_GET_COUNTRY_INFO = 7,
+	PD_DATA_ENTER_USB = 8,
+	/* 9-14 Reserved */
+	PD_DATA_VENDOR_DEF = 15,
+	/* 16-31 Reserved */
+};
+
+enum pd_ext_msg_type {
+	/* 0 Reserved */
+	PD_EXT_SOURCE_CAP_EXT = 1,
+	PD_EXT_STATUS = 2,
+	PD_EXT_GET_BATT_CAP = 3,
+	PD_EXT_GET_BATT_STATUS = 4,
+	PD_EXT_BATT_CAP = 5,
+	PD_EXT_GET_MANUFACTURER_INFO = 6,
+	PD_EXT_MANUFACTURER_INFO = 7,
+	PD_EXT_SECURITY_REQUEST = 8,
+	PD_EXT_SECURITY_RESPONSE = 9,
+	PD_EXT_FW_UPDATE_REQUEST = 10,
+	PD_EXT_FW_UPDATE_RESPONSE = 11,
+	PD_EXT_PPS_STATUS = 12,
+	PD_EXT_COUNTRY_INFO = 13,
+	PD_EXT_COUNTRY_CODES = 14,
+	/* 15-31 Reserved */
+};
+
+#define PD_REV10	0x0
+#define PD_REV20	0x1
+#define PD_REV30	0x2
+#define PD_MAX_REV	PD_REV30
+
+#define PD_HEADER_EXT_HDR	BIT(15)
+#define PD_HEADER_CNT_SHIFT	12
+#define PD_HEADER_CNT_MASK	0x7
+#define PD_HEADER_ID_SHIFT	9
+#define PD_HEADER_ID_MASK	0x7
+#define PD_HEADER_PWR_ROLE	BIT(8)
+#define PD_HEADER_REV_SHIFT	6
+#define PD_HEADER_REV_MASK	0x3
+#define PD_HEADER_DATA_ROLE	BIT(5)
+#define PD_HEADER_TYPE_SHIFT	0
+#define PD_HEADER_TYPE_MASK	0x1f
+
+#define PD_HEADER(type, pwr, data, rev, id, cnt, ext_hdr)		\
+	((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) |	\
+	 ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) |		\
+	 ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) |		\
+	 ((rev) << PD_HEADER_REV_SHIFT) |					\
+	 (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) |		\
+	 (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT) |	\
+	 ((ext_hdr) ? PD_HEADER_EXT_HDR : 0))
+
+#define PD_HEADER_LE(type, pwr, data, rev, id, cnt) \
+	cpu_to_le16(PD_HEADER((type), (pwr), (data), (rev), (id), (cnt), (0)))
+
+static inline unsigned int pd_header_cnt(u16 header)
+{
+	return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK;
+}
+
+static inline unsigned int pd_header_cnt_le(__le16 header)
+{
+	return pd_header_cnt(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_type(u16 header)
+{
+	return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK;
+}
+
+static inline unsigned int pd_header_type_le(__le16 header)
+{
+	return pd_header_type(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_msgid(u16 header)
+{
+	return (header >> PD_HEADER_ID_SHIFT) & PD_HEADER_ID_MASK;
+}
+
+static inline unsigned int pd_header_msgid_le(__le16 header)
+{
+	return pd_header_msgid(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_rev(u16 header)
+{
+	return (header >> PD_HEADER_REV_SHIFT) & PD_HEADER_REV_MASK;
+}
+
+static inline unsigned int pd_header_rev_le(__le16 header)
+{
+	return pd_header_rev(le16_to_cpu(header));
+}
+
+#define PD_EXT_HDR_CHUNKED		BIT(15)
+#define PD_EXT_HDR_CHUNK_NUM_SHIFT	11
+#define PD_EXT_HDR_CHUNK_NUM_MASK	0xf
+#define PD_EXT_HDR_REQ_CHUNK		BIT(10)
+#define PD_EXT_HDR_DATA_SIZE_SHIFT	0
+#define PD_EXT_HDR_DATA_SIZE_MASK	0x1ff
+
+#define PD_EXT_HDR(data_size, req_chunk, chunk_num, chunked)				\
+	((((data_size) & PD_EXT_HDR_DATA_SIZE_MASK) << PD_EXT_HDR_DATA_SIZE_SHIFT) |	\
+	 ((req_chunk) ? PD_EXT_HDR_REQ_CHUNK : 0) |					\
+	 (((chunk_num) & PD_EXT_HDR_CHUNK_NUM_MASK) << PD_EXT_HDR_CHUNK_NUM_SHIFT) |	\
+	 ((chunked) ? PD_EXT_HDR_CHUNKED : 0))
+
+#define PD_EXT_HDR_LE(data_size, req_chunk, chunk_num, chunked) \
+	cpu_to_le16(PD_EXT_HDR((data_size), (req_chunk), (chunk_num), (chunked)))
+
+static inline unsigned int pd_ext_header_chunk_num(u16 ext_header)
+{
+	return (ext_header >> PD_EXT_HDR_CHUNK_NUM_SHIFT) &
+		PD_EXT_HDR_CHUNK_NUM_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size(u16 ext_header)
+{
+	return (ext_header >> PD_EXT_HDR_DATA_SIZE_SHIFT) &
+		PD_EXT_HDR_DATA_SIZE_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size_le(__le16 ext_header)
+{
+	return pd_ext_header_data_size(le16_to_cpu(ext_header));
+}
+
+#define PD_MAX_PAYLOAD		7
+#define PD_EXT_MAX_CHUNK_DATA	26
+
+/*
+ * struct pd_chunked_ext_message_data - PD chunked extended message data as
+ *					 seen on wire
+ * @header:    PD extended message header
+ * @data:      PD extended message data
+ */
+struct pd_chunked_ext_message_data {
+	__le16 header;
+	u8 data[PD_EXT_MAX_CHUNK_DATA];
+} __packed;
+
+/*
+ * struct pd_message - PD message as seen on wire
+ * @header:    PD message header
+ * @payload:   PD message payload
+ * @ext_msg:   PD message chunked extended message data
+ */
+struct pd_message {
+	__le16 header;
+	union {
+		__le32 payload[PD_MAX_PAYLOAD];
+		struct pd_chunked_ext_message_data ext_msg;
+	};
+} __packed;
+
+/* PDO: Power Data Object */
+#define PDO_MAX_OBJECTS		7
+
+enum pd_pdo_type {
+	PDO_TYPE_FIXED = 0,
+	PDO_TYPE_BATT = 1,
+	PDO_TYPE_VAR = 2,
+	PDO_TYPE_APDO = 3,
+};
+
+#define PDO_TYPE_SHIFT		30
+#define PDO_TYPE_MASK		0x3
+
+#define PDO_TYPE(t)	((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK		0x3ff
+#define PDO_CURR_MASK		0x3ff
+#define PDO_PWR_MASK		0x3ff
+
+#define PDO_FIXED_DUAL_ROLE		BIT(29)	/* Power role swap supported */
+#define PDO_FIXED_SUSPEND		BIT(28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP		BIT(28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER		BIT(27) /* Externally powered */
+#define PDO_FIXED_USB_COMM		BIT(26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP		BIT(25) /* Data role swap supported */
+#define PDO_FIXED_UNCHUNK_EXT		BIT(24) /* Unchunked Extended Message supported (Source) */
+#define PDO_FIXED_FRS_CURR_MASK		(BIT(24) | BIT(23)) /* FR_Swap Current (Sink) */
+#define PDO_FIXED_FRS_CURR_SHIFT	23
+#define PDO_FIXED_VOLT_SHIFT		10	/* 50mV units */
+#define PDO_FIXED_CURR_SHIFT		0	/* 10mA units */
+
+#define PDO_FIXED_VOLT(mv)	((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma)	((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags)			\
+	(PDO_TYPE(PDO_TYPE_FIXED) | (flags) |		\
+	 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define VSAFE5V 5000 /* mv units */
+
+#define PDO_BATT_MAX_VOLT_SHIFT	20	/* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT	10	/* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT	0	/* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw)			\
+	(PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) |	\
+	 PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT	20	/* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT	10	/* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT	0	/* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma)				\
+	(PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) |	\
+	 PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+enum pd_apdo_type {
+	APDO_TYPE_PPS = 0,
+};
+
+#define PDO_APDO_TYPE_SHIFT	28	/* Only valid value currently is 0x0 - PPS */
+#define PDO_APDO_TYPE_MASK	0x3
+
+#define PDO_APDO_TYPE(t)	((t) << PDO_APDO_TYPE_SHIFT)
+
+#define PDO_PPS_APDO_MAX_VOLT_SHIFT	17	/* 100mV units */
+#define PDO_PPS_APDO_MIN_VOLT_SHIFT	8	/* 100mV units */
+#define PDO_PPS_APDO_MAX_CURR_SHIFT	0	/* 50mA units */
+
+#define PDO_PPS_APDO_VOLT_MASK	0xff
+#define PDO_PPS_APDO_CURR_MASK	0x7f
+
+#define PDO_PPS_APDO_MIN_VOLT(mv)	\
+	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_VOLT(mv)	\
+	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_CURR(ma)	\
+	((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT)
+
+#define PDO_PPS_APDO(min_mv, max_mv, max_ma)				\
+	(PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) |	\
+	PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) |	\
+	PDO_PPS_APDO_MAX_CURR(max_ma))
+
+static inline enum pd_pdo_type pdo_type(u32 pdo)
+{
+	return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_fixed_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_min_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_current(u32 pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int pdo_max_power(u32 pdo)
+{
+	return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250;
+}
+
+static inline enum pd_apdo_type pdo_apdo_type(u32 pdo)
+{
+	return (pdo >> PDO_APDO_TYPE_SHIFT) & PDO_APDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_pps_apdo_min_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_PPS_APDO_MIN_VOLT_SHIFT) &
+		PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_PPS_APDO_MAX_VOLT_SHIFT) &
+		PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_current(u32 pdo)
+{
+	return ((pdo >> PDO_PPS_APDO_MAX_CURR_SHIFT) &
+		PDO_PPS_APDO_CURR_MASK) * 50;
+}
+
+/* RDO: Request Data Object */
+#define RDO_OBJ_POS_SHIFT	28
+#define RDO_OBJ_POS_MASK	0x7
+#define RDO_GIVE_BACK		BIT(27)	/* Supports reduced operating current */
+#define RDO_CAP_MISMATCH	BIT(26) /* Not satisfied by source caps */
+#define RDO_USB_COMM		BIT(25) /* USB communications capable */
+#define RDO_NO_SUSPEND		BIT(24) /* USB Suspend not supported */
+
+#define RDO_PWR_MASK			0x3ff
+#define RDO_CURR_MASK			0x3ff
+
+#define RDO_FIXED_OP_CURR_SHIFT		10
+#define RDO_FIXED_MAX_CURR_SHIFT	0
+
+#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT)
+
+#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT)
+#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT)
+
+#define RDO_FIXED(idx, op_ma, max_ma, flags)			\
+	(RDO_OBJ(idx) | (flags) |				\
+	 PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma))
+
+#define RDO_BATT_OP_PWR_SHIFT		10	/* 250mW units */
+#define RDO_BATT_MAX_PWR_SHIFT		0	/* 250mW units */
+
+#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT)
+#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT)
+
+#define RDO_BATT(idx, op_mw, max_mw, flags)			\
+	(RDO_OBJ(idx) | (flags) |				\
+	 RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw))
+
+#define RDO_PROG_VOLT_MASK	0x7ff
+#define RDO_PROG_CURR_MASK	0x7f
+
+#define RDO_PROG_VOLT_SHIFT	9
+#define RDO_PROG_CURR_SHIFT	0
+
+#define RDO_PROG_VOLT_MV_STEP	20
+#define RDO_PROG_CURR_MA_STEP	50
+
+#define PDO_PROG_OUT_VOLT(mv)	\
+	((((mv) / RDO_PROG_VOLT_MV_STEP) & RDO_PROG_VOLT_MASK) << RDO_PROG_VOLT_SHIFT)
+#define PDO_PROG_OP_CURR(ma)	\
+	((((ma) / RDO_PROG_CURR_MA_STEP) & RDO_PROG_CURR_MASK) << RDO_PROG_CURR_SHIFT)
+
+#define RDO_PROG(idx, out_mv, op_ma, flags)			\
+	(RDO_OBJ(idx) | (flags) |				\
+	 PDO_PROG_OUT_VOLT(out_mv) | PDO_PROG_OP_CURR(op_ma))
+
+static inline unsigned int rdo_index(u32 rdo)
+{
+	return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK;
+}
+
+static inline unsigned int rdo_op_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_max_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) &
+		RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_op_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+static inline unsigned int rdo_max_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+/* Enter_USB Data Object */
+#define EUDO_USB_MODE_MASK		GENMASK(30, 28)
+#define EUDO_USB_MODE_SHIFT		28
+#define   EUDO_USB_MODE_USB2		0
+#define   EUDO_USB_MODE_USB3		1
+#define   EUDO_USB_MODE_USB4		2
+#define EUDO_USB4_DRD			BIT(26)
+#define EUDO_USB3_DRD			BIT(25)
+#define EUDO_CABLE_SPEED_MASK		GENMASK(23, 21)
+#define EUDO_CABLE_SPEED_SHIFT		21
+#define   EUDO_CABLE_SPEED_USB2		0
+#define   EUDO_CABLE_SPEED_USB3_GEN1	1
+#define   EUDO_CABLE_SPEED_USB4_GEN2	2
+#define   EUDO_CABLE_SPEED_USB4_GEN3	3
+#define EUDO_CABLE_TYPE_MASK		GENMASK(20, 19)
+#define EUDO_CABLE_TYPE_SHIFT		19
+#define   EUDO_CABLE_TYPE_PASSIVE	0
+#define   EUDO_CABLE_TYPE_RE_TIMER	1
+#define   EUDO_CABLE_TYPE_RE_DRIVER	2
+#define   EUDO_CABLE_TYPE_OPTICAL	3
+#define EUDO_CABLE_CURRENT_MASK		GENMASK(18, 17)
+#define EUDO_CABLE_CURRENT_SHIFT	17
+#define   EUDO_CABLE_CURRENT_NOTSUPP	0
+#define   EUDO_CABLE_CURRENT_3A		2
+#define   EUDO_CABLE_CURRENT_5A		3
+#define EUDO_PCIE_SUPPORT		BIT(16)
+#define EUDO_DP_SUPPORT			BIT(15)
+#define EUDO_TBT_SUPPORT		BIT(14)
+#define EUDO_HOST_PRESENT		BIT(13)
+
+/* USB PD timers and counters */
+#define PD_T_NO_RESPONSE	5000	/* 4.5 - 5.5 seconds */
+#define PD_T_DB_DETECT		10000	/* 10 - 15 seconds */
+#define PD_T_SEND_SOURCE_CAP	150	/* 100 - 200 ms */
+#define PD_T_SENDER_RESPONSE	60	/* 24 - 30 ms, relaxed */
+#define PD_T_RECEIVER_RESPONSE	15	/* 15ms max */
+#define PD_T_SOURCE_ACTIVITY	45
+#define PD_T_SINK_ACTIVITY	135
+#define PD_T_SINK_WAIT_CAP	310	/* 310 - 620 ms */
+#define PD_T_PS_TRANSITION	500
+#define PD_T_SRC_TRANSITION	35
+#define PD_T_DRP_SNK		40
+#define PD_T_DRP_SRC		30
+#define PD_T_PS_SOURCE_OFF	920
+#define PD_T_PS_SOURCE_ON	480
+#define PD_T_PS_SOURCE_ON_PRS	450	/* 390 - 480ms */
+#define PD_T_PS_HARD_RESET	30
+#define PD_T_SRC_RECOVER	760
+#define PD_T_SRC_RECOVER_MAX	1000
+#define PD_T_SRC_TURN_ON	275
+#define PD_T_SAFE_0V		650
+#define PD_T_VCONN_SOURCE_ON	100
+#define PD_T_SINK_REQUEST	100	/* 100 ms minimum */
+#define PD_T_ERROR_RECOVERY	100	/* minimum 25 is insufficient */
+#define PD_T_SRCSWAPSTDBY	625	/* Maximum of 650ms */
+#define PD_T_NEWSRC		250	/* Maximum of 275ms */
+#define PD_T_SWAP_SRC_START	20	/* Minimum of 20ms */
+#define PD_T_BIST_CONT_MODE	50	/* 30 - 60 ms */
+#define PD_T_SINK_TX		16	/* 16 - 20 ms */
+#define PD_T_CHUNK_NOT_SUPP	42	/* 40 - 50 ms */
+
+#define PD_T_DRP_TRY		100	/* 75 - 150 ms */
+#define PD_T_DRP_TRYWAIT	600	/* 400 - 800 ms */
+
+#define PD_T_CC_DEBOUNCE	200	/* 100 - 200 ms */
+#define PD_T_PD_DEBOUNCE	20	/* 10 - 20 ms */
+#define PD_T_TRY_CC_DEBOUNCE	15	/* 10 - 20 ms */
+
+#define PD_N_CAPS_COUNT		(PD_T_NO_RESPONSE / PD_T_SEND_SOURCE_CAP)
+#define PD_N_HARD_RESET_COUNT	1
+
+#define PD_P_SNK_STDBY_MW	2500	/* 2500 mW */
+
+/* Time to wait for TCPC to complete transmit */
+#define PD_T_TCPC_TX_TIMEOUT	100	/* in ms	*/
+
+#endif /* __LINUX_USB_PD_H */
diff --git a/include/usb/tcpm.h b/include/usb/tcpm.h
new file mode 100644
index 0000000..10f0515
--- /dev/null
+++ b/include/usb/tcpm.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ * Copyright 2024 Collabora
+ */
+
+#ifndef __LINUX_USB_TCPM_H
+#define __LINUX_USB_TCPM_H
+
+#include <dm/of.h>
+#include <linux/bitops.h>
+#include "pd.h"
+
+enum typec_orientation {
+	TYPEC_ORIENTATION_NONE,
+	TYPEC_ORIENTATION_NORMAL,
+	TYPEC_ORIENTATION_REVERSE,
+};
+
+enum typec_cc_status {
+	TYPEC_CC_OPEN,
+	TYPEC_CC_RA,
+	TYPEC_CC_RD,
+	TYPEC_CC_RP_DEF,
+	TYPEC_CC_RP_1_5,
+	TYPEC_CC_RP_3_0,
+};
+
+enum typec_cc_polarity {
+	TYPEC_POLARITY_CC1,
+	TYPEC_POLARITY_CC2,
+};
+
+enum tcpm_transmit_status {
+	TCPC_TX_SUCCESS = 0,
+	TCPC_TX_DISCARDED = 1,
+	TCPC_TX_FAILED = 2,
+};
+
+enum tcpm_transmit_type {
+	TCPC_TX_SOP = 0,
+	TCPC_TX_SOP_PRIME = 1,
+	TCPC_TX_SOP_PRIME_PRIME = 2,
+	TCPC_TX_SOP_DEBUG_PRIME = 3,
+	TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4,
+	TCPC_TX_HARD_RESET = 5,
+	TCPC_TX_CABLE_RESET = 6,
+	TCPC_TX_BIST_MODE_2 = 7
+};
+
+struct dm_tcpm_ops {
+	int (*get_connector_node)(struct udevice *dev, ofnode *connector_node);
+	int (*init)(struct udevice *dev);
+	int (*get_vbus)(struct udevice *dev);
+	int (*set_cc)(struct udevice *dev, enum typec_cc_status cc);
+	int (*get_cc)(struct udevice *dev, enum typec_cc_status *cc1,
+		      enum typec_cc_status *cc2);
+	int (*set_polarity)(struct udevice *dev,
+			    enum typec_cc_polarity polarity);
+	int (*set_vconn)(struct udevice *dev, bool on);
+	int (*set_vbus)(struct udevice *dev, bool on, bool charge);
+	int (*set_pd_rx)(struct udevice *dev, bool on);
+	int (*set_roles)(struct udevice *dev, bool attached,
+			 enum typec_role role, enum typec_data_role data);
+	int (*start_toggling)(struct udevice *dev,
+			      enum typec_port_type port_type,
+			      enum typec_cc_status cc);
+	int (*pd_transmit)(struct udevice *dev, enum tcpm_transmit_type type,
+			   const struct pd_message *msg, unsigned int negotiated_rev);
+	void (*poll_event)(struct udevice *dev);
+	int (*enter_low_power_mode)(struct udevice *dev, bool attached, bool pd_capable);
+};
+
+/* API for drivers */
+void tcpm_vbus_change(struct udevice *dev);
+void tcpm_cc_change(struct udevice *dev);
+void tcpm_pd_receive(struct udevice *dev, const struct pd_message *msg);
+void tcpm_pd_transmit_complete(struct udevice *dev,
+			       enum tcpm_transmit_status status);
+void tcpm_pd_hard_reset(struct udevice *dev);
+
+/* API for boards */
+extern const char * const typec_pd_rev_name[];
+extern const char * const typec_orientation_name[];
+extern const char * const typec_role_name[];
+extern const char * const typec_data_role_name[];
+extern const char * const typec_cc_status_name[];
+
+int tcpm_get(int index, struct udevice **devp);
+int tcpm_get_pd_rev(struct udevice *dev);
+int tcpm_get_current(struct udevice *dev);
+int tcpm_get_voltage(struct udevice *dev);
+enum typec_orientation tcpm_get_orientation(struct udevice *dev);
+enum typec_role tcpm_get_pwr_role(struct udevice *dev);
+enum typec_data_role tcpm_get_data_role(struct udevice *dev);
+bool tcpm_is_connected(struct udevice *dev);
+const char *tcpm_get_state(struct udevice *dev);
+
+#endif /* __LINUX_USB_TCPM_H */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 85f4426..b065598 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1172,10 +1172,10 @@
 	void *dst;
 	int rc;
 
-	if (CONFIG_IS_ENABLED(GZIP))
+	if (CONFIG_IS_ENABLED(GZIP) && CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP))
 		if (gzip_parse_header(src, sz_in) >= 0)
 			gzip = 1;
-	if (CONFIG_IS_ENABLED(LZO))
+	if (CONFIG_IS_ENABLED(LZO) && CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO))
 		if (!gzip && lzop_is_valid_header(src))
 			lzo = 1;
 
diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts
index 3ab67b3..685e337 100644
--- a/scripts/Makefile.dts
+++ b/scripts/Makefile.dts
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST)))
+dtb-y += $(patsubst %,%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
 
 ifeq ($(CONFIG_OF_UPSTREAM_BUILD_VENDOR),y)
 ifeq ($(CONFIG_ARM64),y)