imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting. So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.
We have to configure necessary PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index 2a96bd0..a0dad5f 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -104,9 +104,6 @@
clock_init_late();
- /* DDR initialization */
- spl_dram_init();
-
/* This must place after upower init, so access to MDA and MRC are valid */
/* Init XRDC MDA */
xrdc_init_mda();
@@ -114,6 +111,11 @@
/* Init XRDC MRC for VIDEO, DSP domains */
xrdc_init_mrc();
+ xrdc_init_pdac_msc();
+
+ /* DDR initialization */
+ spl_dram_init();
+
/* Call it after PS16 power up */
set_lpav_qos();