commit 7ec2413578b3b72531ed60bb45c8a6cd1a142049
author Simon Glass <sjg@chromium.org> Sun Sep 29 19:49:48 2024 -0600
committer Tom Rini <trini@konsulko.com> Fri Oct 11 11:44:48 2024 -0600
tree edad3a36155bccf380c703c2c81e2c0a9ab210a4
parent 49c24a8b9e75a1cc5074966386f0c7f3952bb100

drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>

drivers/fpga/intel_sdm_mb.c

diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 45caef4..5a65bd9 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -17,7 +17,7 @@
 #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS		60000
 #define RECONFIG_STATUS_INTERVAL_DELAY_US		1000000
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
 
 #define BITSTREAM_CHUNK_SIZE				0xFFFF0
 #define RECONFIG_STATUS_POLL_RETRY_MAX			100

drivers/fpga/zynqpl.c

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 57467b4..3e86d85 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -414,13 +414,13 @@
 	if (bstype != BIT_PARTIAL)
 		zynq_slcr_devcfg_enable();
 
-	if (!IS_ENABLED(CONFIG_SPL_BUILD))
+	if (!IS_ENABLED(CONFIG_XPL_BUILD))
 		puts("INFO:post config was not run, please run manually if needed\n");
 
 	return FPGA_SUCCESS;
 }
 
-#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD)
 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
 		       fpga_fs_info *fsinfo)
 {
@@ -504,7 +504,7 @@
 
 struct xilinx_fpga_op zynq_op = {
 	.load = zynq_load,
-#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD)
 	.loadfs = zynq_loadfs,
 #endif
 };