ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access
The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.
The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c
index cc7679a..0cbcd14 100644
--- a/drivers/ddr/altera/sdram_agilex.c
+++ b/drivers/ddr/altera/sdram_agilex.c
@@ -143,9 +143,6 @@
setbits_le32(plat->hmc + ERRINTEN,
DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
- /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
- writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
-
if (!cpu_has_been_warmreset())
sdram_init_ecc_bits(&bd);
} else {
@@ -158,6 +155,9 @@
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
}
+ /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
+ writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
sdram_size_check(&bd);
priv->info.base = bd.bi_dram[0].start;