spl: introduce SPL_XIP to config
U-Boot and SPL don't necessary share the same location, so we might end
with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.
In case of non XIP boot mode, we rely on such variables as "hart_lottery"
and "available_harts_lock" which we use as atomics.
The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL,
so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.
This adds an option special for SPL to behave it in XIP manner and we don't
use hart_lottery and available_harts_lock, during start proccess.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 78e964d..c042506 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -269,6 +269,13 @@
from a NOR flash memory without copying the code to ram.
Say yes here if U-Boot boots from flash directly.
+config SPL_XIP
+ bool "Enable XIP mode for SPL"
+ help
+ If SPL starts in read-only memory (XIP for example) then we shouldn't
+ rely on lock variables (for example hart_lottery and available_harts_lock),
+ this affects only SPL, other stages should proceed as non-XIP.
+
config SHOW_REGS
bool "Show registers on unhandled exception"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 3ffcbbd..0f323b2 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -19,7 +19,7 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
u32 hart_lottery __section(".data") = 0;
/*
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index b7f21ab..de9d078 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -122,7 +122,7 @@
call_harts_early_init:
jal harts_early_init
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@@ -152,7 +152,7 @@
/* save the boot hart id to global_data */
SREG tp, GD_BOOT_HART(gp)
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
la t0, available_harts_lock
amoswap.w.rl zero, zero, 0(t0)
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 095484a..b3c79e1 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,7 @@
#if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
ulong available_harts;
#endif
};
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f1fe089..c4f48c8 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -16,7 +16,7 @@
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index ba99210..f8b7562 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -45,7 +45,7 @@
continue;
}
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;