diff --git a/CHANGELOG b/CHANGELOG
index 36d7a5c..d9aed9e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,12 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Patch by Shlomo Kut, 29 Mar 2004:
+  Add support for MKS Instruments "Quantum" board
+
+* Fix build problem with Cogent boards;
+  avoid using <asm/byteorder.h> when using the host compiler
+
 * Patch by Ganapathi C, 04 Aug 2004:
   Fix NFS timeout issue
 
diff --git a/MAKEALL b/MAKEALL
index 6d96dcb..643a777 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -34,23 +34,24 @@
 #########################################################################
 
 LIST_8xx="	\
-	Adder87x	GENIETV		MBX860T		RBC823		\
-	AdderII		GTH		MHPC		rmu		\
-	ADS860		hermes		MPC86xADS	RPXClassic	\
-	AMX860		IAD210		MPC885ADS	RPXlite		\
-	c2mon		ICU862_100MHz	MVS1		RPXlite_DW	\
-	CCM		IP860		NETPHONE	RRvision	\
-	cogent_mpc8xx	IVML24		NETTA		SM850		\
-	ELPT860		IVML24_128	NETTA2		SPD823TS	\
-	ESTEEM192E	IVML24_256	NETTA_ISDN	svm_sc8xx	\
-	ETX094		IVMS8		NETVIA		SXNI855T	\
-	FADS823		IVMS8_128	NETVIA_V2	TOP860		\
-	FADS850SAR	IVMS8_256	NX823		TQM823L		\
-	FADS860T	KUP4K		pcu_e		TQM823L_LCD	\
-	FLAGADM		KUP4X		QS823		TQM850L		\
-	FPS850L		LANTEC		QS850		TQM855L		\
-	GEN860T		lwmon		QS860T		TQM860L		\
-	GEN860T_SC	MBX		R360MPI		v37		\
+	Adder87x	GENIETV		MBX860T		R360MPI		\
+	AdderII		GTH		MHPC		RBC823		\
+	ADS860		hermes		MPC86xADS	rmu		\
+	AMX860		IAD210		MPC885ADS	RPXClassic	\
+	c2mon		ICU862_100MHz	MVS1		RPXlite		\
+	CCM		IP860		NETPHONE	RPXlite_DW	\
+	cogent_mpc8xx	IVML24		NETTA		RRvision	\
+	ELPT860		IVML24_128	NETTA2		SM850		\
+	ESTEEM192E	IVML24_256	NETTA_ISDN	SPD823TS	\
+	ETX094		IVMS8		NETVIA		svm_sc8xx	\
+	FADS823		IVMS8_128	NETVIA_V2	SXNI855T	\
+	FADS850SAR	IVMS8_256	NX823		TOP860		\
+	FADS860T	KUP4K		pcu_e		TQM823L		\
+	FLAGADM		KUP4X		QS823		TQM823L_LCD	\
+	FPS850L		LANTEC		QS850		TQM850L		\
+	GEN860T		lwmon		QS860T		TQM855L		\
+	GEN860T_SC	MBX		quantum		TQM860L		\
+							v37		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 963bf58..461fd82 100644
--- a/Makefile
+++ b/Makefile
@@ -553,6 +553,9 @@
 QS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc
 
+quantum_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx quantum
+
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi
 
diff --git a/board/cogent/mb.h b/board/cogent/mb.h
index e37a39c..f6eaf0a 100644
--- a/board/cogent/mb.h
+++ b/board/cogent/mb.h
@@ -54,7 +54,7 @@
  * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
  * will be at byte 7 (the address + 7). For little endian addressing, the
  * register will be at byte 0 (the address + 0). To learn the endianess
- * we must include <asm/byteorder.h>
+ * we must include <endian.h>
  *
  * Take the CMA102 and CMA111 motherboards as examples...
  *
@@ -230,16 +230,20 @@
 
 #ifndef __ASSEMBLY__
 
-#include <asm/byteorder.h>
+#ifdef USE_HOSTCC
+#include <endian.h>		/* avoid using private kernel header files */
+#else
+#include <asm/byteorder.h>	/* use U-Boot provided headers */
+#endif
 
 /* a single CMA10x motherboard i/o register */
 typedef
     struct {
-#if defined(__LITTLE_ENDIAN)
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 	unsigned char value;
 #endif
 	unsigned char filler[7];
-#if defined(__BIG_ENDIAN)
+#if __BYTE_ORDER == __BIG_ENDIAN
 	unsigned char value;
 #endif
     }
@@ -357,7 +361,7 @@
 /* V360EPC PCI Bridge */
 typedef
     struct {
-#if defined(__LITTLE_ENDIAN)
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 	unsigned short v3_pci_vendor;		/* 0x00 */
 	unsigned short v3_pci_device;
 	unsigned short v3_pci_cmd;		/* 0x04 */
@@ -436,7 +440,7 @@
 	unsigned long  reserved8:24;
 	unsigned long  reserved9[7];		/* 0xe4 */
 #endif
-#if defined(__BIG_ENDIAN)
+#if __BYTE_ORDER == __BIG_ENDIAN
 	unsigned short v3_pci_device;		/* 0x00 */
 	unsigned short v3_pci_vendor;
 	unsigned short v3_pci_stat;		/* 0x04 */
diff --git a/board/quantum/Makefile b/board/quantum/Makefile
new file mode 100644
index 0000000..e50f5ff
--- /dev/null
+++ b/board/quantum/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o fpga.o
+
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/quantum/config.mk b/board/quantum/config.mk
new file mode 100644
index 0000000..7cb374e
--- /dev/null
+++ b/board/quantum/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RMU boards
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c
new file mode 100644
index 0000000..75c2658
--- /dev/null
+++ b/board/quantum/fpga.c
@@ -0,0 +1,263 @@
+/*
+ * (C) Copyright 2001-2003
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* The DEBUG define must be before common to enable debugging */
+#undef DEBUG
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include "fpga.h"
+/* ------------------------------------------------------------------------- */
+
+#define MAX_ONES               226
+
+/* MPC850 port D */
+#define PD(bit) (1 << (15 - (bit)))
+# define FPGA_INIT             PD(11)	/* FPGA init pin (ppc input)     */
+# define FPGA_PRG              PD(12)	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              PD(13)	/* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             PD(14)	/* FPGA data pin (ppc output)    */
+# define FPGA_DONE             PD(15)	/* FPGA done pin (ppc input)     */
+
+
+/* DDR 0 - input, 1 - output */
+#define FPGA_INIT_PDDIR          FPGA_PRG | FPGA_CLK | FPGA_DATA	/* just set outputs */
+
+
+#define SET_FPGA(data)         immr->im_ioport.iop_pddat = (data)
+#define GET_FPGA               immr->im_ioport.iop_pddat
+
+#define FPGA_WRITE_1 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);}	/* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);}	/* set data to 1  */
+
+
+int fpga_boot (unsigned char *fpgadata, int size)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	int i, index, len;
+	int count;
+
+#ifdef CFG_FPGA_SPARTAN2
+	int j;
+	unsigned char data;
+#else
+	unsigned char b;
+	int bit;
+#endif
+
+	debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size);
+
+	/* display infos on fpgaimage */
+	printf ("FPGA:");
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf (" %s", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+	printf ("\n");
+
+
+	index = 0;
+
+#ifdef CFG_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	debug ("FPGA: configdata starts at position 0x%x\n", index);
+	debug ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR;
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (GET_FPGA & FPGA_INIT) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(GET_FPGA & FPGA_INIT)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	debug ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CFG_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		if ((i % 1024) == 0)
+			printf ("%6d out of %6d\r", i, size);	/* let them know we are alive */
+#endif
+
+		data = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			if ((data & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			data <<= 1;
+		}
+	}
+	/* add some 0xff to the end of the file */
+	for (i = 0; i < 8; i++) {
+		data = 0xff;
+		for (j = 0; j < 8; j++) {
+			if ((data & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			data <<= 1;
+		}
+	}
+#else
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif
+	debug ("\n\n");
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(GET_FPGA & FPGA_DONE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	debug ("FPGA: Booting successful!\n");
+	return 0;
+}
diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h
new file mode 100644
index 0000000..2ef45e5
--- /dev/null
+++ b/board/quantum/fpga.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Virtex2 FPGA configuration support for the QUANTUM computer
+ */
+int fpga_boot(unsigned char *fpgadata, int size);
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c
new file mode 100644
index 0000000..8a73448
--- /dev/null
+++ b/board/quantum/quantum.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "fpga.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+unsigned long flash_init (void);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 * (Initialization code at 0x36)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char *s = getenv ("serial#");
+
+	puts ("Board QUANTUM, Serial No: ");
+
+	for (; s && *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+	putc ('\n');
+	return (0);		/* success */
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+			   SDRAM_MAX_SIZE);
+	/*
+	 * Final mapping:
+	 */
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	udelay (1000);
+
+	return (size9);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val, size;
+	ulong save[32];		/* to make test non-destructive */
+	unsigned char i = 0;
+
+	memctl->memc_mamr = mamr_value;
+
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
+		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+			addr = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long);
+			     cnt <<= 1) {
+				addr = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
+		}
+	}
+	return (maxsize);
+}
+
+/*
+ * Miscellaneous intialization
+ */
+int misc_init_r (void)
+{
+	char *fpga_data_str = getenv ("fpgadata");
+	char *fpga_size_str = getenv ("fpgasize");
+	void *fpga_data;
+	int fpga_size;
+	int status;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	int flash_size;
+
+	/* Remap FLASH according to real size */
+	flash_size = flash_init ();
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	if (fpga_data_str && fpga_size_str) {
+		fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
+		fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
+
+		status = fpga_boot (fpga_data, fpga_size);
+		if (status != 0) {
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+		}
+	}
+	return 0;
+}
diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds
new file mode 100644
index 0000000..082d8b0
--- /dev/null
+++ b/board/quantum/u-boot.lds
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug
new file mode 100644
index 0000000..f34c2a4
--- /dev/null
+++ b/board/quantum/u-boot.lds.debug
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/include/configs/cogent_common.h b/include/configs/cogent_common.h
index 7eab9ea..cdf5802 100644
--- a/include/configs/cogent_common.h
+++ b/include/configs/cogent_common.h
@@ -204,5 +204,5 @@
 #if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
 #error 2nd dual serial capability defined without serial/parallel capability
 #endif
-#include <board/cogent/mb.h>
+#include "../board/cogent/mb.h"
 #endif	/* _CONFIG_COGENT_COMMON_H */
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
new file mode 100644
index 0000000..d0ee729
--- /dev/null
+++ b/include/configs/quantum.h
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * changes for 16M board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#undef CONFIG_MPC860
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_RPXLITE		1	/* QUANTUM is the RPXlite clone */
+#define CONFIG_RMU		1   /* The QUNATUM is based on our RMU */
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+/* default developmenmt environment */
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passed to Linux in MHz. Needed for old kernels (2.4) crashes for new kernels */
+
+#define CONFIG_ETHADDR 00:0B:17:00:00:00
+
+#define CONFIG_IPADDR  10.10.69.10
+#define CONFIG_SERVERIP 10.10.69.49
+#define CONFIG_NETMASK	255.255.255.0
+#define CONFIG_HOSTNAME QUANTUM
+#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
+
+#define CONFIG_BOOTARGS	 "root=/dev/ram rw"
+
+#define CONFIG_BOOTCOMMAND "bootm ff000000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+    "serial#=12345\0"		\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"	\
+	"ramargs=setenv bootargs root=/dev/ram rw\0" \
+    "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0"
+
+/*
+ * Select the more full-featured memory test (Barr embedded systems)
+ */
+#define CFG_ALT_MEMTEST
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+
+/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
+#define CONFIG_RTC_M48T35A 1
+
+#if 0
+#define CONFIG_WATCHDOG 1		/* watchdog enabled		*/
+#else
+#undef CONFIG_WATCHDOG
+#endif
+
+/*  NVRAM and RTC */
+#define CFG_NVRAM_BASE_ADDR 0xFA000000
+#define CFG_NVRAM_SIZE 2048
+
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+		CFG_CMD_PING	| \
+		CFG_CMD_REGINFO)
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_AUTOBOOT_KEYED	/* Enable password protection */
+#define CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"system"
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00040000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01f00000	/* 256K ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE	0xFF000000
+
+#if 1
+    #define CFG_FLASH_CFI_DRIVER
+#else
+    #undef CFG_FLASH_CFI_DRIVER
+#endif
+
+
+#ifdef CFG_FLASH_CFI_DRIVER
+    #define CFG_FLASH_CFI 1
+    #undef CFG_FLASH_USE_BUFFER_WRITE
+    #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#endif
+
+/*%%% #define CFG_FLASH_BASE		0xFFF00000 */
+#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	0xFFF00000
+/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET	    0x00F40000	/*   Offset   of Environment Sector	absolute address 0xfff40000*/
+#define CFG_ENV_SIZE		0x40000 /* Total Size of Environment Sector	*/
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/* FPGA */
+#define CONFIG_MISC_INIT_R
+#define CFG_FPGA_SPARTAN2
+#define CFG_FPGA_PROG_FEEDBACK
+
+
+/*-----------------------------------------------------------------------
+ * Reset address
+ */
+#define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
+#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
+#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000E00
+
+#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
+#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXLITE mem setting */
+#define CFG_BR3_PRELIM	0xFA400001		/* FPGA */
+#define CFG_OR3_PRELIM	0xFFFF8910
+
+#define CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CFG_OR4_PRELIM	0xFFFE0970
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	20
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CFG_MPTPR	MPTPR_PTP_DIV2
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02	/* Software reboot			*/
+
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+
+#define BCSR0 0xFA400000
+#define BCSR1 0xFA400001
+#define BCSR2 0xFA400002
+#define BCSR3 0xFA400003
+
+#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
+#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN	0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR2_ENPA5HDR	0x08	/* USB Control */
+#define BCSR2_ENUSBCLK	0x10
+#define BCSR2_USBPWREN	0x20
+#define BCSR2_USBSPD	0x40
+#define BCSR2_USBSUSP	0x80
+
+#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
+#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
+#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
+#define BCSR3_D27	0x10	/* Dip Switch settings */
+#define BCSR3_D26	0x20
+#define BCSR3_D25	0x40
+#define BCSR3_D24	0x80
+
+#endif	/* __CONFIG_H */
diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h
index ebd81c0..19b0c86 100644
--- a/include/linux/byteorder/big_endian.h
+++ b/include/linux/byteorder/big_endian.h
@@ -7,6 +7,7 @@
 #ifndef __BIG_ENDIAN_BITFIELD
 #define __BIG_ENDIAN_BITFIELD
 #endif
+#define	__BYTE_ORDER	__BIG_ENDIAN
 
 #include <linux/byteorder/swab.h>
 
diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h
index 1431663..a46f3ec 100644
--- a/include/linux/byteorder/little_endian.h
+++ b/include/linux/byteorder/little_endian.h
@@ -7,6 +7,7 @@
 #ifndef __LITTLE_ENDIAN_BITFIELD
 #define __LITTLE_ENDIAN_BITFIELD
 #endif
+#define	__BYTE_ORDER	__LITTLE_ENDIAN
 
 #include <linux/byteorder/swab.h>