arm: include: sunxi: Remove duplicate newlines
Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 14df3cc..35ca049 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -262,7 +262,6 @@
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
-
#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */
#define MBUS_CLK_GATE (0x1 << 31)
@@ -295,7 +294,6 @@
#define APB2_RESET_TWI_SHIFT (0)
#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
-
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
void clock_set_pll5(unsigned int clk);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index 0264bfe..006f776 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -217,7 +217,6 @@
#define APB1_RESET_TWI_SHIFT 0
#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT)
-
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int clk);
void clock_set_pll6(unsigned int clk);
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index be02655..f0caecc 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -323,7 +323,6 @@
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
-
static inline int ns_to_t(int nanoseconds)
{
const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
index 2a87996..28b6560 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
@@ -146,7 +146,6 @@
u32 perfwr1; /* 0x1d8 */
};
-
#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h
index 41df5fe..a77daec 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h
@@ -40,7 +40,6 @@
u32 mdfstcr; /* 0x14c */
};
-
struct sunxi_mctl_ctl_reg {
u32 mstr; /* 0x00 master register */
u32 stat; /* 0x04 operating mode status register */
@@ -92,7 +91,6 @@
u32 perfwr1; /* 0x26c write CAM register 1 */
};
-
struct sunxi_mctl_phy_reg {
u8 res0[0x04]; /* 0x00 revision id ??? */
u32 pir; /* 0x04 PHY initialisation register */