| commit | 8f0700c08f4285ffaa866933de7178afffec4c0d | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Wed Oct 17 12:16:12 2018 +0200 |
| committer | Michal Simek <michal.simek@xilinx.com> | Wed Nov 07 10:07:31 2018 +0100 |
| tree | 915e01c99bc5346e74251e28e98315412a6df26f | |
| parent | 4443c5caf33ece7c3f512c2f5712b2a18e7fc350 [diff] |
arm: zynq: Setup non zero SPL FIT load address Default setup is 0 which is incorrect place because it points to OCM which is allocated for SPL only in our case. Use address in DDR. Signed-off-by: Michal Simek <michal.simek@xilinx.com>