Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index cce7405..5f86ef9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -25,10 +25,6 @@
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
endif
-ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
-endif
-
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 4b9e209..d939900 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,12 +538,12 @@
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
- u32 type, rcw;
+ u32 type, rcw, svr = gur_in32(&gur->svr);
puts("SoC: ");
cpu_name(buf);
- printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
+ printf(" %s (0x%x)\n", buf, svr);
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
get_sys_info(&sysinfo);
puts("Clock Configuration:");
@@ -564,7 +564,10 @@
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+ if (soc_has_dp_ddr()) {
+ printf(" DP-DDR: %-4s MT/s",
+ strmhz(buf, sysinfo.freq_ddrbus2));
+ }
#endif
puts("\n");
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 81cf470..d580a43 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -97,9 +97,13 @@
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
+ if (soc_has_dp_ddr()) {
+ sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+ } else {
+ sys_info->freq_ddrbus2 = 0;
+ }
#endif
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 9c69ed1..04831ca 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -20,7 +20,7 @@
#ifdef CONFIG_FSL_LSCH3
/* Set Wuo bit for RN-I 20 */
-#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A)
+#ifdef CONFIG_LS2080A
ldr x0, =CCI_AUX_CONTROL_BASE(20)
ldr x1, =0x00000010
bl ccn504_set_aux
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index a76447e..0cb0100 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -18,7 +18,31 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+bool soc_has_dp_ddr(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 svr = gur_in32(&gur->svr);
+
+ /* LS2085A has DP_DDR */
+ if (SVR_SOC_VER(svr) == SVR_LS2085)
+ return true;
+
+ return false;
+}
+
+bool soc_has_aiop(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 svr = gur_in32(&gur->svr);
+
+ /* LS2085A has AIOP */
+ if (SVR_SOC_VER(svr) == SVR_LS2085)
+ return true;
+
+ return false;
+}
+
+#ifdef CONFIG_LS2080A
/*
* This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index f434c44..c1229c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -46,7 +46,7 @@
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
@@ -54,7 +54,7 @@
#endif
board_early_init_f();
timer_init();
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
env_init();
#endif
get_clocks();
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ceefe43..10d17b2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -23,16 +23,11 @@
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#ifdef CONFIG_LS2080A
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#endif
-#ifdef CONFIG_LS2085A
#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_HAS_DP_DDR
-#endif
+#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_FSL_SRDS_1
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index f75faa6..702b9fa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -157,9 +157,11 @@
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
#endif
};
@@ -204,7 +206,7 @@
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
@@ -245,7 +247,8 @@
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
@@ -256,7 +259,8 @@
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
#endif
};
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index d1fbde7..f71c2c1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -9,7 +9,7 @@
#include <config.h>
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
enum srds_prtcl {
NONE = 0,
PCIE1,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 56989e1..831d817 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -94,4 +94,7 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
void erratum_a009635(void);
#endif
+
+bool soc_has_dp_ddr(void);
+bool soc_has_aiop(void);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index a921fb6..44acfd2 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -82,12 +82,12 @@
CSU_CSLX_FTM5,
CSU_CSLX_FTM8,
CSU_CSLX_FTM7,
- CSU_CSLX_COP_DCSR,
CSU_CSLX_EPU,
- CSU_CSLX_GDI,
+ CSU_CSLX_COP_DCSR,
CSU_CSLX_DDI,
+ CSU_CSLX_GDI,
CSU_CSLX_RESERVED1,
- CSU_CSLX_USB3_PHY = 117,
+ CSU_CSLX_USB3_PHY = 116,
CSU_CSLX_RESERVED2,
CSU_CSLX_MAX,
};
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index d576f2e..53cd755 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -44,15 +44,14 @@
#endif
-#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
- defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
- * Similiarly for LS2080 and LS2085
+ * Similiarly for LS2080
*/
#define CONFIG_ESBC_ADDR_64BIT
#endif
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xa0000000;" \
"setenv initrd_high 0xcfffffff;" \
@@ -66,12 +65,11 @@
/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
* Non-XIP Memory (Nand/SD)*/
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\
- defined(CONFIG_LS2085A)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
#define CONFIG_BOOTSCRIPT_COPY_RAM
#endif
/* The address needs to be modified according to NOR and DDR memory map */
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
#define CONFIG_BS_ADDR_FLASH 0x583900000
#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 67b4afe..bf26376 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -176,9 +176,9 @@
} else if (fm_info_get_enet_if(port) ==
PHY_INTERFACE_MODE_SGMII_2500) {
/* 2.5G SGMII interface */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 1000;
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(1000);
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for 2.5G SGMII */
@@ -241,9 +241,9 @@
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
port == FM1_10GEC1) {
/* XFI interface */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for XFI */
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index 975ea2d..c8dac99 100644
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -6,5 +6,3 @@
F: configs/ls2080a_emu_defconfig
F: include/configs/ls2080a_simu.h
F: configs/ls2080a_simu_defconfig
-F: configs/ls2085a_emu_defconfig
-F: configs/ls2085a_simu_defconfig
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index 56c5d96..1827ddc 100644
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ if (soc_has_dp_ddr()) {
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
}
#endif
}
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index ace0d79..00337d7 100644
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -42,7 +42,7 @@
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 558cef1..7d3bfc8 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -6,11 +6,8 @@
F: include/configs/ls2080aqds.h
F: configs/ls2080aqds_defconfig
F: configs/ls2080aqds_nand_defconfig
-F: configs/ls2085aqds_defconfig
-F: configs/ls2085aqds_nand_defconfig
LS2080A_SECURE_BOOT BOARD
M: Saksham Jain <saksham.jain@nxp.freescale.com>
S: Maintained
F: configs/ls2080aqds_SECURE_BOOT_defconfig
-F: configs/ls2085aqds_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index 9fb5e11..fcb0366 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ if (soc_has_dp_ddr()) {
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
}
#endif
}
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index e1a521d..b3bd40a 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -228,7 +228,7 @@
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 0817711d..5562917 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -6,11 +6,8 @@
F: include/configs/ls2080ardb.h
F: configs/ls2080ardb_defconfig
F: configs/ls2080ardb_nand_defconfig
-F: configs/ls2085ardb_defconfig
-F: configs/ls2085ardb_nand_defconfig
LS2080A_SECURE_BOOT BOARD
M: Saksham Jain <saksham.jain@nxp.freescale.com>
S: Maintained
F: configs/ls2080ardb_SECURE_BOOT_defconfig
-F: configs/ls2085ardb_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index 6c19173..a04d21b 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ if (soc_has_dp_ddr()) {
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
}
#endif
}
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 8201048..fb39af6 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -207,7 +207,7 @@
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig
deleted file mode 100644
index 036bb6f..0000000
--- a/configs/ls2085a_emu_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_EMU=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig
deleted file mode 100644
index 0702bab..0000000
--- a/configs/ls2085a_simu_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_SIMU=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2085aqds_SECURE_BOOT_defconfig b/configs/ls2085aqds_SECURE_BOOT_defconfig
deleted file mode 100644
index f13ee41..0000000
--- a/configs/ls2085aqds_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
-CONFIG_RSA=y
diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig
deleted file mode 100644
index a5c8388..0000000
--- a/configs/ls2085aqds_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig
deleted file mode 100644
index d355c9a..0000000
--- a/configs/ls2085aqds_nand_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-CONFIG_SPL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2085ardb_SECURE_BOOT_defconfig b/configs/ls2085ardb_SECURE_BOOT_defconfig
deleted file mode 100644
index aa66508..0000000
--- a/configs/ls2085ardb_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
-CONFIG_RSA=y
diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig
deleted file mode 100644
index fe46dbc..0000000
--- a/configs/ls2085ardb_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig
deleted file mode 100644
index 5fb0cf6..0000000
--- a/configs/ls2085ardb_nand_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-CONFIG_SPL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/doc/device-tree-bindings/serial/8250.txt b/doc/device-tree-bindings/serial/8250.txt
index 91d5ab0..ba8edae 100644
--- a/doc/device-tree-bindings/serial/8250.txt
+++ b/doc/device-tree-bindings/serial/8250.txt
@@ -53,7 +53,7 @@
Represents a single port that is compatible with the DUART found
on many Freescale chips (examples include mpc8349, mpc8548,
- mpc8641d, p4080 and ls2085a).
+ mpc8641d, p4080 and ls2080a).
Example:
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 3fc418a..8bc517d 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -545,12 +545,12 @@
/*
* Modifying CAAM Read/Write Attributes
- * For LS2080A and LS2085A
+ * For LS2080A
* For AXI Write - Cacheable, Write Back, Write allocate
* For AXI Read - Cacheable, Read allocate
- * Only For LS2080a and LS2085a, to solve CAAM coherency issues
+ * Only For LS2080a, to solve CAAM coherency issues
*/
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
#else
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index ea5f4bf..3acf9e8 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -20,6 +20,8 @@
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -72,6 +74,30 @@
uint scr; /* eSDHC control register */
};
+/**
+ * struct fsl_esdhc_priv
+ *
+ * @esdhc_regs: registers of the sdhc controller
+ * @sdhc_clk: Current clk of the sdhc controller
+ * @bus_width: bus width, 1bit, 4bit or 8bit
+ * @cfg: mmc config
+ * @mmc: mmc
+ * Following is used when Driver Model is enabled for MMC
+ * @dev: pointer for the device
+ * @non_removable: 0: removable; 1: non-removable
+ * @cd_gpio: gpio for card detection
+ */
+struct fsl_esdhc_priv {
+ struct fsl_esdhc *esdhc_regs;
+ unsigned int sdhc_clk;
+ unsigned int bus_width;
+ struct mmc_config cfg;
+ struct mmc *mmc;
+ struct udevice *dev;
+ int non_removable;
+ struct gpio_desc cd_gpio;
+};
+
/* Return the XFERTYP flags for a given command and data packet */
static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
@@ -118,8 +144,8 @@
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
uint blocks;
char *buffer;
uint databuf;
@@ -180,8 +206,8 @@
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
int timeout;
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
#endif
@@ -312,8 +338,8 @@
int err = 0;
uint xfertyp;
uint irqstat;
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
@@ -482,9 +508,9 @@
static void set_sysctl(struct mmc *mmc, uint clock)
{
int div, pre_div;
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
- int sdhc_clk = cfg->sdhc_clk;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int sdhc_clk = priv->sdhc_clk;
uint clk;
if (clock < mmc->cfg->f_min)
@@ -527,8 +553,8 @@
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
static void esdhc_clock_control(struct mmc *mmc, bool enable)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
u32 value;
u32 time_out;
@@ -556,8 +582,8 @@
static void esdhc_set_ios(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
/* Select to use peripheral clock */
@@ -580,8 +606,8 @@
static int esdhc_init(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
int timeout = 1000;
/* Reset the entire host controller */
@@ -621,14 +647,23 @@
static int esdhc_getcd(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_priv *priv = mmc->priv;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
int timeout = 1000;
#ifdef CONFIG_ESDHC_DETECT_QUIRK
if (CONFIG_ESDHC_DETECT_QUIRK)
return 1;
#endif
+
+#ifdef CONFIG_DM_MMC
+ if (priv->non_removable)
+ return 1;
+
+ if (dm_gpio_is_valid(&priv->cd_gpio))
+ return dm_gpio_get_value(&priv->cd_gpio);
+#endif
+
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
udelay(1000);
@@ -656,16 +691,29 @@
.getcd = esdhc_getcd,
};
-int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+
+ return 0;
+};
+
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
{
struct fsl_esdhc *regs;
struct mmc *mmc;
u32 caps, voltage_caps;
- if (!cfg)
- return -1;
+ if (!priv)
+ return -EINVAL;
- regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ regs = priv->esdhc_regs;
/* First reset the eSDHC controller */
esdhc_reset(regs);
@@ -676,7 +724,7 @@
#endif
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
- memset(&cfg->cfg, 0, sizeof(cfg->cfg));
+ memset(&priv->cfg, 0, sizeof(priv->cfg));
voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
@@ -698,47 +746,83 @@
if (caps & ESDHC_HOSTCAPBLT_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
- cfg->cfg.name = "FSL_SDHC";
- cfg->cfg.ops = &esdhc_ops;
+ priv->cfg.name = "FSL_SDHC";
+ priv->cfg.ops = &esdhc_ops;
#ifdef CONFIG_SYS_SD_VOLTAGE
- cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
+ priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
#else
- cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
- if ((cfg->cfg.voltages & voltage_caps) == 0) {
+ if ((priv->cfg.voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
return -1;
}
- cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ if (priv->bus_width == 8)
+ priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ else if (priv->bus_width == 4)
+ priv->cfg.host_caps = MMC_MODE_4BIT;
+
+ priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
- cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+ priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
#endif
- if (cfg->max_bus_width > 0) {
- if (cfg->max_bus_width < 8)
- cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
- if (cfg->max_bus_width < 4)
- cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
+ if (priv->bus_width > 0) {
+ if (priv->bus_width < 8)
+ priv->cfg.host_caps &= ~MMC_MODE_8BIT;
+ if (priv->bus_width < 4)
+ priv->cfg.host_caps &= ~MMC_MODE_4BIT;
}
if (caps & ESDHC_HOSTCAPBLT_HSS)
- cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
- cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
+ priv->cfg.host_caps &= ~MMC_MODE_8BIT;
#endif
- cfg->cfg.f_min = 400000;
- cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
+ priv->cfg.f_min = 400000;
+ priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
- cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- mmc = mmc_create(&cfg->cfg, cfg);
+ mmc = mmc_create(&priv->cfg, priv);
if (mmc == NULL)
return -1;
+ priv->mmc = mmc;
+
+ return 0;
+}
+
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+{
+ struct fsl_esdhc_priv *priv;
+ int ret;
+
+ if (!cfg)
+ return -EINVAL;
+
+ priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = fsl_esdhc_cfg_to_priv(cfg, priv);
+ if (ret) {
+ debug("%s xlate failure\n", __func__);
+ free(priv);
+ return ret;
+ }
+
+ ret = fsl_esdhc_init(priv);
+ if (ret) {
+ debug("%s init failure\n", __func__);
+ free(priv);
+ return ret;
+ }
+
return 0;
}
@@ -819,3 +903,92 @@
4 + 1, 1);
}
#endif
+
+#ifdef CONFIG_DM_MMC
+#include <asm/arch/clock.h>
+static int fsl_esdhc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev->of_offset;
+ fdt_addr_t addr;
+ unsigned int val;
+ int ret;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)addr;
+ priv->dev = dev;
+
+ val = fdtdec_get_int(fdt, node, "bus-width", -1);
+ if (val == 8)
+ priv->bus_width = 8;
+ else if (val == 4)
+ priv->bus_width = 4;
+ else
+ priv->bus_width = 1;
+
+ if (fdt_get_property(fdt, node, "non-removable", NULL)) {
+ priv->non_removable = 1;
+ } else {
+ priv->non_removable = 0;
+ gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
+ &priv->cd_gpio, GPIOD_IS_IN);
+ }
+
+ /*
+ * TODO:
+ * Because lack of clk driver, if SDHC clk is not enabled,
+ * need to enable it first before this driver is invoked.
+ *
+ * we use MXC_ESDHC_CLK to get clk freq.
+ * If one would like to make this function work,
+ * the aliases should be provided in dts as this:
+ *
+ * aliases {
+ * mmc0 = &usdhc1;
+ * mmc1 = &usdhc2;
+ * mmc2 = &usdhc3;
+ * mmc3 = &usdhc4;
+ * };
+ * Then if your board only supports mmc2 and mmc3, but we can
+ * correctly get the seq as 2 and 3, then let mxc_get_clock
+ * work as expected.
+ */
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_init(priv);
+ if (ret) {
+ dev_err(dev, "fsl_esdhc_init failure\n");
+ return ret;
+ }
+
+ upriv->mmc = priv->mmc;
+
+ return 0;
+}
+
+static const struct udevice_id fsl_esdhc_ids[] = {
+ { .compatible = "fsl,imx6ul-usdhc", },
+ { .compatible = "fsl,imx6sx-usdhc", },
+ { .compatible = "fsl,imx6sl-usdhc", },
+ { .compatible = "fsl,imx6q-usdhc", },
+ { .compatible = "fsl,imx7d-usdhc", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(fsl_esdhc) = {
+ .name = "fsl-esdhc-mmc",
+ .id = UCLASS_MMC,
+ .of_match = fsl_esdhc_ids,
+ .probe = fsl_esdhc_probe,
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+};
+#endif
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index d2b8b5c..1811b0f 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -356,6 +356,12 @@
}
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+
+__weak bool soc_has_aiop(void)
+{
+ return false;
+}
+
static int load_mc_aiop_img(u64 aiop_fw_addr)
{
u64 mc_ram_addr = mc_get_dram_addr();
@@ -363,6 +369,9 @@
void *aiop_img;
#endif
+ /* Check if AIOP is available */
+ if (!soc_has_aiop())
+ return -ENODEV;
/*
* Load the MC AIOP image in the MC private DRAM block:
*/
@@ -1235,6 +1244,7 @@
aiop_fw_addr = simple_strtoull(argv[3], NULL,
16);
+ /* if SoC doesn't have AIOP, err = -ENODEV */
err = load_mc_aiop_img(aiop_fw_addr);
if (!err)
printf("fsl-mc: AIOP FW applied\n");
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 74c4916..5587aa6 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -7,4 +7,3 @@
obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
obj-$(CONFIG_LS2080A) += ls2080a.o
-obj-$(CONFIG_LS2085A) += ls2080a.o
diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c
index 44afe14..2388438 100644
--- a/drivers/net/vsc9953.c
+++ b/drivers/net/vsc9953.c
@@ -335,7 +335,7 @@
struct vsc9953_analyzer *l2ana_reg;
/* Administrative down */
- if (vsc9953_l2sw.port[port_nr].enabled) {
+ if (!vsc9953_l2sw.port[port_nr].enabled) {
printf("Port %d is administrative down\n", port_nr);
return -1;
}
@@ -2525,6 +2525,9 @@
if (vsc9953_port_init(i))
printf("Failed to initialize l2switch port %d\n", i);
+ if (!vsc9953_l2sw.port[i].enabled)
+ continue;
+
/* Enable VSC9953 GMII Ports Port ID 0 - 7 */
if (VSC9953_INTERNAL_PORT_CHECK(i)) {
out_le32(&l2ana_reg->pfc[i].pfc_cfg,
@@ -2537,6 +2540,11 @@
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
VSC9953_MAC_FC_CFG);
}
+
+ l2dev_gmii_reg = (struct vsc9953_dev_gmii *)
+ (VSC9953_OFFSET + VSC9953_DEV_GMII_OFFSET +
+ T1040_SWITCH_GMII_DEV_OFFSET * i);
+
out_le32(&l2dev_gmii_reg->port_mode.clock_cfg,
VSC9953_CLOCK_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg,
@@ -2559,10 +2567,6 @@
/* WAIT FOR 2 us*/
udelay(2);
- l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(
- (char *)l2dev_gmii_reg
- + T1040_SWITCH_GMII_DEV_OFFSET);
-
/* Initialize Lynx PHY Wrappers */
phy_addr = 0;
if (vsc9953_l2sw.port[i].enet_if ==
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index fd243b1..e900c50 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -212,7 +212,19 @@
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifdef CONFIG_NAND_BOOT
+/* Store Fman ucode at offeset 0x160000(11 blocks). */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2040 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
#define CONFIG_ENV_SPI_BUS 0
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 7b99d36..7c19122 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -162,7 +162,7 @@
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 13ce349..57e2a29 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -171,10 +171,9 @@
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
-#ifdef CONFIG_LS2085A
+/* For LS2085A */
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
-#endif
/*
* Carve out a DDR region which will not be used by u-boot/Linux
@@ -198,10 +197,6 @@
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
#endif
-#ifdef CONFIG_LS2085A
-#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
-#endif
-
#define CONFIG_SYS_PCI_64BIT
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
index 534ebb6..f4ace85 100644
--- a/include/configs/ls2080a_emu.h
+++ b/include/configs/ls2080a_emu.h
@@ -9,15 +9,8 @@
#include "ls2080a_common.h"
-#ifdef CONFIG_LS2080A
#define CONFIG_IDENT_STRING " LS2080A-EMU"
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU"
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_IDENT_STRING " LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-EMU"
-#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 2c2ce7b..0dbe95f 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -9,15 +9,8 @@
#include "ls2080a_common.h"
-#ifdef CONFIG_LS2080A
#define CONFIG_IDENT_STRING " LS2080A-SIMU"
#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU"
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_IDENT_STRING " LS2085A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2085A-SIMU"
-#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 073048f..fa760a5 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -168,11 +168,7 @@
#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
struct fsl_esdhc_cfg {
-#ifdef CONFIG_FSL_LAYERSCAPE
- u64 esdhc_base;
-#else
- u32 esdhc_base;
-#endif
+ phys_addr_t esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
struct mmc_config cfg;
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index e922e32..c5e42e6 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -55,7 +55,7 @@
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#elif defined(CONFIG_LS2080A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0