Merge tag 'efi-2020-07-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-07-rc6
Corrections for variable definitions are provided:
* Correct size of secure boot related UEFI variables.
* Do not use int for storing an enum.
* Replace fdt_addr by fdt_size where needed.
diff --git a/arch/arm/dts/imx6q-tbs2910.dts b/arch/arm/dts/imx6q-tbs2910.dts
index cc5df37..7d0a067 100644
--- a/arch/arm/dts/imx6q-tbs2910.dts
+++ b/arch/arm/dts/imx6q-tbs2910.dts
@@ -107,7 +107,18 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@4 {
+ reg = <4>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
};
&hdmi {
diff --git a/cmd/booti.c b/cmd/booti.c
index ae37975..af0603b 100644
--- a/cmd/booti.c
+++ b/cmd/booti.c
@@ -141,7 +141,7 @@
"\tspecifying the size of a RAW initrd.\n"
"\tCurrently only booting from gz, bz2, lzma and lz4 compression\n"
"\ttypes are supported. In order to boot from any of these compressed\n"
- "\timages, user have to set kernel_comp_addr_r and kernel_comp_size enviornment\n"
+ "\timages, user have to set kernel_comp_addr_r and kernel_comp_size environment\n"
"\tvariables beforehand.\n"
#if defined(CONFIG_OF_LIBFDT)
"\tSince booting a Linux kernel requires a flat device-tree, a\n"
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 1c252e0..1529a3e 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -8,6 +8,7 @@
#include <blk.h>
#include <command.h>
#include <console.h>
+#include <memalign.h>
#include <mmc.h>
#include <part.h>
#include <sparse_format.h>
@@ -56,7 +57,8 @@
if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) {
bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0;
bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR);
- u8 wp, ext_csd[MMC_MAX_BLOCK_LEN];
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+ u8 wp;
int ret;
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
index f7c2c9f..739eefa 100644
--- a/doc/board/sifive/fu540.rst
+++ b/doc/board/sifive/fu540.rst
@@ -27,7 +27,7 @@
--------
1. Add the RISC-V toolchain to your PATH.
-2. Setup ARCH & cross compilation enviornment variable:
+2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
@@ -217,7 +217,7 @@
=>setenv kernel_comp_addr_r 0x90000000
=>setenv kernel_comp_size 0x500000
-By this time, correct kernel image is loaded and required enviornment variables
+By this time, correct kernel image is loaded and required environment variables
are set. You can proceed to load the ramdisk and device tree from the tftp server
as well.
diff --git a/doc/device-tree-bindings/net/phy/atheros.txt b/doc/device-tree-bindings/net/phy/atheros.txt
index 97e97b8..a72c6b0 100644
--- a/doc/device-tree-bindings/net/phy/atheros.txt
+++ b/doc/device-tree-bindings/net/phy/atheros.txt
@@ -23,7 +23,7 @@
ethernet-phy@0 {
reg = <0>;
- qca-clk-out-frequency = <125000000>;
+ qca,clk-out-frequency = <125000000>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index f42e018..5b61eeb 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -907,19 +907,9 @@
ctrl = readl(®s->autoc12err);
if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
(ctrl & MIX_CTRL_SMPCLK_SEL)) {
- /*
- * need to wait some time, make sure sd/mmc fininsh
- * send out tuning data, otherwise, the sd/mmc can't
- * response to any command when the card still out
- * put the tuning data.
- */
- mdelay(1);
ret = 0;
break;
}
-
- /* Add 1ms delay for SD and eMMC */
- mdelay(1);
}
writel(irqstaten, ®s->irqstaten);
@@ -1267,6 +1257,18 @@
val |= priv->tuning_start_tap;
val &= ~ESDHC_TUNING_STEP_MASK;
val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+
+ /* Disable the CMD CRC check for tuning, if not, need to
+ * add some delay after every tuning command, because
+ * hardware standard tuning logic will directly go to next
+ * step once it detect the CMD CRC error, will not wait for
+ * the card side to finally send out the tuning data, trigger
+ * the buffer read ready interrupt immediately. If usdhc send
+ * the next tuning command some eMMC card will stuck, can't
+ * response, block the tuning procedure or the first command
+ * after the whole tuning procedure always can't get any response.
+ */
+ val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
writel(val, ®s->tuning_ctrl);
}
}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 620bb93..725a367 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -669,12 +669,15 @@
static int mmc_send_op_cond(struct mmc *mmc)
{
int err, i;
+ int timeout = 1000;
+ uint start;
/* Some cards seem to need this */
mmc_go_idle(mmc);
+ start = get_timer(0);
/* Asking to the card its capabilities */
- for (i = 0; i < 2; i++) {
+ for (i = 0; ; i++) {
err = mmc_send_op_cond_iter(mmc, i != 0);
if (err)
return err;
@@ -682,6 +685,10 @@
/* exit if not busy (flag seems to be inverted) */
if (mmc->ocr & OCR_BUSY)
break;
+
+ if (get_timer(start) > timeout)
+ return -ETIMEDOUT;
+ udelay(100);
}
mmc->op_cond_pending = 1;
return 0;
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 92cc843..f4eb655 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -567,6 +567,7 @@
#endif
u32 ctrl;
struct sdhci_host *host = mmc->priv;
+ bool no_hispd_bit = false;
if (host->ops && host->ops->set_control_reg)
host->ops->set_control_reg(host);
@@ -594,14 +595,26 @@
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
- if (mmc->clock > 26000000)
- ctrl |= SDHCI_CTRL_HISPD;
- else
- ctrl &= ~SDHCI_CTRL_HISPD;
-
if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
- (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
+ (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
ctrl &= ~SDHCI_CTRL_HISPD;
+ no_hispd_bit = true;
+ }
+
+ if (!no_hispd_bit) {
+ if (mmc->selected_mode == MMC_HS ||
+ mmc->selected_mode == SD_HS ||
+ mmc->selected_mode == MMC_DDR_52 ||
+ mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == UHS_SDR25 ||
+ mmc->selected_mode == UHS_SDR50 ||
+ mmc->selected_mode == UHS_SDR104 ||
+ mmc->selected_mode == UHS_DDR50)
+ ctrl |= SDHCI_CTRL_HISPD;
+ else
+ ctrl &= ~SDHCI_CTRL_HISPD;
+ }
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 0357aba..fc64d93 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -466,6 +466,9 @@
c.identify.cns = cpu_to_le32(cns);
+ invalidate_dcache_range(dma_addr,
+ dma_addr + sizeof(struct nvme_id_ctrl));
+
ret = nvme_submit_admin_cmd(dev, &c, NULL);
if (!ret)
invalidate_dcache_range(dma_addr,
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 33c6d52..279a66d 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -203,7 +203,8 @@
#define ESDHC_STD_TUNING_EN BIT(24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
-#define ESDHC_TUNING_START_TAP_MASK 0xff
+#define ESDHC_TUNING_START_TAP_MASK 0x7f
+#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE BIT(7)
#define ESDHC_TUNING_STEP_MASK 0x00070000
#define ESDHC_TUNING_STEP_SHIFT 16
diff --git a/include/linux/psci.h b/include/linux/psci.h
index 9433df8..841dbc8 100644
--- a/include/linux/psci.h
+++ b/include/linux/psci.h
@@ -91,8 +91,8 @@
unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3);
#else
-unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
- unsigned long a2, unsigned long a3)
+static inline unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3)
{
return PSCI_RET_DISABLED;
}
diff --git a/include/zfs_common.h b/include/zfs_common.h
index 027ba91..cb83e59 100644
--- a/include/zfs_common.h
+++ b/include/zfs_common.h
@@ -22,6 +22,8 @@
#ifndef __ZFS_COMMON__
#define __ZFS_COMMON__
+#include <part.h>
+
#define SECTOR_SIZE 0x200
#define SECTOR_BITS 9