commit 7c1781b1db19c6d74b63e85146081aa67982b1f3
author Alexey Brodkin <Alexey.Brodkin@synopsys.com> Fri Mar 21 16:57:47 2014 +0400
committer Tom Rini <trini@ti.com> Fri Mar 28 15:06:30 2014 -0400
tree 980ceceb167839653780e2b2ff31283734970145
parent 498fb8344014d60fc6b6b18ee227b5e66113a5bb

axs101: flush DMA buffer descriptors before DMA transactons starts

CPU sets DMA buffer descriptors with data required for inetrnal DMA such as:
 * Ownership of BD
 * Buffer size
 * Pointer to data buffer in memory

Then we need to make sure DMA engine of NAND controller gets proper data.
For this we flush buffer rescriptor.

Then we're  ready for DMA transaction.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>

board/synopsys/axs101/nand.c

diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c
index 8672803..c7f90c4 100644
--- a/board/synopsys/axs101/nand.c
+++ b/board/synopsys/axs101/nand.c
@@ -107,6 +107,10 @@
 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
 	writel(0, &bd->buffer_ptr1);
 
+	/* Flush modified buffer descriptor */
+	flush_dcache_range((unsigned long)bd,
+			   (unsigned long)bd + sizeof(struct nand_bd));
+
 	/* Issue "write" command */
 	NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
 
@@ -137,6 +141,10 @@
 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
 	writel(0, &bd->buffer_ptr1);
 
+	/* Flush modified buffer descriptor */
+	flush_dcache_range((unsigned long)bd,
+			   (unsigned long)bd + sizeof(struct nand_bd));
+
 	/* Issue "read" command */
 	NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));