tree d594585e8814f6f20d5d70a3f34545e4794ed887
parent 99825797d1d1f23f5c369c68264690299e7a2f8f
author Shaveta Leekha <shaveta@freescale.com> 1401266935 +0530
committer York Sun <yorksun@freescale.com> 1402001107 -0700

powerpc/serdes: Add the workaround for erratum A-007186

SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.

This workaround overwrite the SerDes registers with new values,
to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.

This workaround is valid for B4, T4 and T2 platforms, so
added in their config.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
[York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs]
Reviewed-by: York Sun <yorksun@freescale.com>