tree 142468c8d25f58f06e357b947298461c28a04dfa
parent 6558d278c6561e265fdb08b3b9566b67de46e15f
author Rajeshwari Shinde <rajeshwari.s@samsung.com> 1341345777 +0000
committer Albert ARIBAUD <albert.u.boot@aribaud.net> 1346504303 +0200

EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>