tree e42231be4b5524faf75ebe717c7d7a0ffd9a39ab
parent 8a7d6633b4896b37456207293ed181d05403d7ee
author Robert Hancock <hancock@sedsystems.ca> 1560872835 -0600
committer Michal Simek <michal.simek@xilinx.com> 1564474806 +0200

fpga: virtex2: Add additional clock cycles after DONE assertion

Some Xilinx FPGA configuration options can result in the startup
sequence extending past the end of the FPGA bitstream. Continue applying
CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure
the startup sequence is complete, as recommended by Xilinx.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>