// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx Versal NET Mini QSPI Configuration
 *
 * (C) Copyright 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 * Ashok Reddy Soma <ashok.reddy.soma@amd.com>
 */

/dts-v1/;

/ {
	compatible = "xlnx,versal-net-mini";
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Xilinx Versal NET MINI QSPI";

	aliases {
		serial0 = &dcc;
		spi0 = &qspi;
	};

	chosen {
		stdout-path = "serial0:115200";
	};

	memory@bbf00000 {
		device_type = "memory";
		reg = <0 0xbbf00000 0 0x100000>;
	};

	clk150: clk150 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <150000000>;
	};

	dcc: dcc {
		compatible = "arm,dcc";
		status = "okay";
		bootph-all;
	};

	amba: axi {
		bootph-all;
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		qspi: spi@f1030000 {
			compatible = "xlnx,versal-qspi-1.0";
			status = "okay";
			clock-names = "ref_clk", "pclk";
			num-cs = <1>;
			reg = <0 0xf1030000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk150>, <&clk150>;

			flash0: flash@0 {
				compatible = "n25q512a", "micron,m25p80",
					     "jedec,spi-nor";
				reg = <0>;
				spi-tx-bus-width = <4>;
				spi-rx-bus-width = <4>;
				spi-max-frequency = <20000000>;
			};
		};
	};
};