tree 35fb86dea8c991d3a6c1ab32eb03ebb4d3e8815f
parent 5e872330992d43d1540fe2feee408e72b6725a8e
author Stefan Roese <sr@denx.de> 1416138420 +0100
committer Marek Vasut <marex@denx.de> 1417870367 +0100

arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>