tree b6e82b205f1dc1a2d4a1eac37ec136cbe22822fa
parent b513d9d07be08f292944b8af394d61101469fb07
author York Sun <yorksun@freescale.com> 1345191757 +0000
committer Andy Fleming <afleming@freescale.com> 1345742215 -0500

powerpc/mpc8xxx: Add fine timing support for DDR3

When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>