clk: at91: sam9x60: Register the required clocks for USB
Register into DM the clocks required to properly enable USB functionality
within the bootloader.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index 6b5486c..14c2ffc 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -76,6 +76,8 @@
ID_QSPI = 18,
ID_MCK_PRES = 19,
+ ID_USBCK = 20,
+ ID_UHPCK = 21,
ID_MAX,
};
@@ -99,6 +101,7 @@
[ID_PLL_A_DIV] = "plla_divpmcck",
[ID_MCK_PRES] = "mck_pres",
[ID_MCK_DIV] = "mck_div",
+ [ID_USBCK] = "usbck",
};
/* Fractional PLL output range. */
@@ -171,6 +174,13 @@
.pid_mask = GENMASK(6, 0),
};
+/* USB clock layout */
+static const struct clk_usbck_layout usbck_layout = {
+ .offset = 0x38,
+ .usbs_mask = GENMASK(1, 0),
+ .usbdiv_mask = GENMASK(11, 8),
+};
+
/**
* PLL clocks description
* @n: clock name
@@ -266,6 +276,7 @@
u8 cid;
} sam9x60_systemck[] = {
{ .n = "ddrck", .p = "mck_div", .id = 2, .cid = ID_DDR, },
+ { .n = "uhpck", .p = "usbck", .id = 6, .cid = ID_UHPCK },
{ .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, },
{ .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, },
{ .n = "qspick", .p = "mck_div", .id = 19, .cid = ID_QSPI, },
@@ -543,6 +554,28 @@
}
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c);
+ /* Register usbck. */
+ p[0] = clk_names[ID_PLL_A_DIV];
+ p[1] = clk_names[ID_PLL_U_DIV];
+ p[2] = clk_names[ID_MAIN_XTAL];
+ m[0] = 0;
+ m[1] = 1;
+ m[2] = 2;
+ cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
+ cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
+ cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_XTAL);
+ prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
+ 3, fail);
+ prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, 3, fail);
+ c = sam9x60_clk_register_usb(base, clk_names[ID_USBCK], p, 3,
+ &usbck_layout, tmpclkmux, tmpmux,
+ ID_USBCK);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_USBCK), c);
+
/* Register programmable clocks. */
p[0] = clk_names[ID_MD_SLCK];
p[1] = clk_names[ID_TD_SLCK];