| commit | 2e0071b92fd3629d8cbed4d5c9037d8d6776fd66 | [log] [tgz] |
|---|---|---|
| author | Benoît Thébaudeau <benoit@wsystem.com> | Wed May 03 11:59:06 2017 +0200 |
| committer | Stefano Babic <sbabic@denx.de> | Wed May 31 10:14:41 2017 +0200 |
| tree | 941e43aba76e6868955a8a57d4186cbf077f758d | |
| parent | 9d694246cbab64b30505c8bdfeb061d785e0161d [diff] |
mx25pdk: Set the eSDHC PER clock to 48 MHz The maximum SD clock frequency in High Speed mode is 50 MHz. This change makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1) instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2). Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>