commit 78df5779904c3ba5c33204ef359588e55af758ae
author Patrice Chotard <patrice.chotard@st.com> Wed Feb 07 10:44:48 2018 +0100
committer Tom Rini <trini@konsulko.com> Tue Mar 13 21:45:37 2018 -0400
tree 47340e60fb8b3636fa2ac08ad38f4e9e4971c9a1
parent 5301635a9639fd8c3be9e67fa469bfe14d8cdd40

clk: clk_stm32h7: Fix prescaler for Domain 3

d1cfgr register was used to calculate the domain 3
prescaler value instead of d3cfgr.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

drivers/clk/clk_stm32h7.c

diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index 92db714..9ee2e2e 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -635,7 +635,7 @@
 	struct stm32_rcc_regs *regs = priv->rcc_base;
 	ulong sysclk = 0;
 	u32 gate_offset;
-	u32 d1cfgr;
+	u32 d1cfgr, d3cfgr;
 	/* prescaler table lookups for clock computation */
 	u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
 	u8 source, idx;
@@ -712,9 +712,10 @@
 		break;
 
 	case RCC_APB4ENR:
-		if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
+		d3cfgr = readl(&regs->d3cfgr);
+		if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
 			/* get D3 domain APB4 prescaler */
-			idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
+			idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
 			      RCC_D3CFGR_D3PPRE_SHIFT;
 			sysclk = sysclk / prescaler_table[idx];
 		}