tree 37710debed41f1ad9386610ea67c4a199bb4b5ce
parent 96e75a89ba62f151f953c90401e4872aff46e484
author Leo Yu-Chi Liang <ycliang@andestech.com> 1703571455 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> 1703669347 +0800

andes: cpu: Enable cache and TLB ECC support

Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>