diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 79ea91f..efde9cc 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -178,42 +178,58 @@
 #endif
 }
 
+
 /*
- * We initialize L2 as cache here.
+ * Initialize L2 as cache.
+ *
+ * The newer 8548, etc, parts have twice as much cache, but
+ * use the same bit-encoding as the older 8555, etc, parts.
+ *
+ * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
  */
-int cpu_init_r (void)
+
+int cpu_init_r(void)
 {
 #if defined(CONFIG_L2_CACHE)
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
-	volatile uint temp;
+	volatile uint cache_ctl;
+	uint svr, ver;
+
+	svr = get_svr();
+	ver = SVR_VER(svr);
 
 	asm("msync;isync");
-	temp = l2cache->l2ctl;
-	temp &= 0x30000000;
-	switch ( temp ) {
+	cache_ctl = l2cache->l2ctl;
+
+	switch (cache_ctl & 0x30000000) {
 	case 0x20000000:
-		printf ("L2 cache 256KB:");
+		if (ver == SVR_8548 || ver == SVR_8548_E) {
+			printf ("L2 cache 512KB:");
+		} else {
+			printf ("L2 cache 256KB:");
+		}
 		break;
 	case 0x00000000:
 	case 0x10000000:
 	case 0x30000000:
 	default:
-		printf ("L2 cache unknown size. Check the silicon!\n");
+		printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
 		return -1;
 	}
 
 	asm("msync;isync");
 	l2cache->l2ctl = 0x68000000; /* invalidate */
-	temp = l2cache->l2ctl;
+	cache_ctl = l2cache->l2ctl;
 	asm("msync;isync");
+
 	l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
-	temp = l2cache->l2ctl;
+	cache_ctl = l2cache->l2ctl;
 	asm("msync;isync");
 
-	printf("enabled\n");
+	printf(" enabled\n");
 #else
-	printf("L2:    disabled.\n");
+	printf("L2 cache: disabled\n");
 #endif
 
 	return 0;