diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 425b3f9..ffb7aad 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -151,6 +151,19 @@
 	return fixup_usb_boot();
 }
 #endif
+
+static void setup_am654_navss_northbridge(void)
+{
+	/*
+	 * NB0 is bridge to SRAM and NB1 is bridge to DDR.
+	 * To ensure that SRAM transfers are not stalled due to
+	 * delays during DDR refreshes, SRAM traffic should be higher
+	 * priority (threadmap=2) than DDR traffic (threadmap=0).
+	 */
+	writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP);
+	writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP);
+}
+
 void board_init_f(ulong dummy)
 {
 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
@@ -168,6 +181,8 @@
 	/* Make all control module registers accessible */
 	ctrl_mmr_unlock();
 
+	setup_am654_navss_northbridge();
+
 #ifdef CONFIG_CPU_V7R
 	disable_linefill_optimization();
 	setup_k3_mpu_regions();
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h
index 1908a13..f533e22 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -52,4 +52,10 @@
 /* MCU SCRATCHPAD usage */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
 
+/* NAVSS Northbridge config */
+#define	NAVSS0_NBSS_NB0_CFG_BASE			0x03802000
+#define	NAVSS0_NBSS_NB1_CFG_BASE			0x03803000
+
+#define	NAVSS_NBSS_THREADMAP				0x10
+
 #endif /* __ASM_ARCH_AM6_HARDWARE_H */