| commit | 767675f9c6d64983edaf816cfc5efc5010c1ea5f | [log] [tgz] |
|---|---|---|
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | Wed Mar 21 15:59:01 2018 +0300 |
| committer | Alexey Brodkin <abrodkin@synopsys.com> | Wed Mar 21 17:06:54 2018 +0300 |
| tree | 765031cfd5fec7bff551f623508e1f20aab0e45f | |
| parent | 0dec96cc3d62c832e0867c54a860eac764063ebb [diff] |
ARC: Cache: Fix SLC operations when SLC is bypassed for data If L1 D$ is disabled SLC is bypassed for data and all load/store requests are sent directly to main memory. If L1 I$ is disabled SLC is NOT bypassed for instructions and all instruction requests are fetched through SLC. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>