tree 3beb627bd527d95316667ab941e1c00894889c33
parent 65e0eb1907749eab255b4cc11cf5ba5381689298
author Stephen Warren <swarren@nvidia.com> 1390592767 -0700
committer Tom Warren <twarren@nvidia.com> 1391446006 -0700

ARM: tegra: misc cleanups triggered by Tegra124 review

Use a named constant for the PLL lock bit in enable_cpu_clocks().

Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>