tree 17e9764522803d82ccfcf66cfadaabc74d9f9e56
parent 31de3d84988f71855327b883a84b8707f549a46a
author Marek Vasut <marek.vasut+renesas@gmail.com> 1527786362 +0200
committer Marek Vasut <marek.vasut+renesas@gmail.com> 1527838933 +0200

clk: renesas: Pass clock rate around as 64bit number internally

The PLL rate could be in the GHz range, which could overflow a 32bit
data type. Since the hardware is 64bit anyway, pass the clock rates
as 64bit number internally to avoid this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>