* Patches by David Müller, 12 Jun 2003:
- rewrite of the S3C24X0 register definitions stuff
- "driver" for the built-in S3C24X0 RTC
* Patches by Yuli Barcohen, 12 Jun 2003:
- Add MII support and Ethernet PHY initialization for MPC8260ADS board
- Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
configuration word supplied by FPGA on some MPC8260ADS boards
* Patch by Pantelis Antoniou, 10 Jun 2003:
Unify status LED interface
diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c
index 195fb01..dd944fb 100644
--- a/cpu/arm920t/interrupts.c
+++ b/cpu/arm920t/interrupts.c
@@ -43,7 +43,12 @@
int timer_load_val = 0;
/* macro to read the 16 bit timer */
-#define READ_TIMER (rTCNTO4 & 0xffff)
+static inline ulong READ_TIMER(void)
+{
+ S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
+ return (timers->TCNTO4 & 0xffff);
+}
#ifdef CONFIG_USE_IRQ
/* enable IRQ interrupts */
@@ -184,9 +189,11 @@
int interrupt_init (void)
{
+ S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
- rTCFG0 = 0x0f00;
+ timers->TCFG0 = 0x0f00;
if (timer_load_val == 0)
{
/*
@@ -197,11 +204,11 @@
timer_load_val = get_PCLK()/(2 * 16 * 100);
}
/* load value for 10 ms timeout */
- lastdec = rTCNTB4 = timer_load_val;
+ lastdec = timers->TCNTB4 = timer_load_val;
/* auto load, manual update of Timer 4 */
- rTCON = (rTCON & ~0x0700000) | 0x600000;
+ timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
/* auto load, start Timer 4 */
- rTCON = (rTCON & ~0x0700000) | 0x500000;
+ timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
timestamp = 0;
return (0);
@@ -243,13 +250,13 @@
void reset_timer_masked (void)
{
/* reset time */
- lastdec = READ_TIMER;
+ lastdec = READ_TIMER();
timestamp = 0;
}
ulong get_timer_masked (void)
{
- ulong now = READ_TIMER;
+ ulong now = READ_TIMER();
if (lastdec >= now) {
/* normal mode */
diff --git a/cpu/arm920t/serial.c b/cpu/arm920t/serial.c
index c32e73b..10cfade 100644
--- a/cpu/arm920t/serial.c
+++ b/cpu/arm920t/serial.c
@@ -25,57 +25,51 @@
#include <s3c2410.h>
#endif
+#ifdef CONFIG_SERIAL1
+#define UART_NR S3C24X0_UART0
+
+#elif CONFIG_SERIAL2
+# if defined(CONFIG_TRAB)
+# #error "TRAB supports only CONFIG_SERIAL1"
+# endif
+#define UART_NR S3C24X0_UART1
+
+#elif CONFIG_SERIAL3
+# if defined(CONFIG_TRAB)
+# #error "TRAB supports only CONFIG_SERIAL1"
+# endif
+#define UART_NR S3C24X0_UART2
+
+#else
+#error "Bad: you didn't configure serial ..."
+#endif
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
-
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
int i;
unsigned int reg = 0;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
-#ifdef CONFIG_SERIAL1
/* FIFO enable, Tx/Rx FIFO clear */
- rUFCON0 = 0x07;
- rUMCON0 = 0x0;
+ uart->UFCON = 0x07;
+ uart->UMCON = 0x0;
/* Normal,No parity,1 stop,8 bit */
- rULCON0 = 0x3;
+ uart->ULCON = 0x3;
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
- rUCON0 = 0x245;
- rUBRDIV0 = reg;
+ uart->UCON = 0x245;
+ uart->UBRDIV = reg;
#ifdef CONFIG_HWFLOW
- rUMCON0 = 0x1; /* RTS up */
+ uart->UMCON = 0x1; /* RTS up */
#endif
for (i = 0; i < 100; i++);
-#elif CONFIG_SERIAL2
-# if defined(CONFIG_TRAB)
-# #error "TRAB supports only CONFIG_SERIAL1"
-# endif
- /* FIFO enable, Tx/Rx FIFO clear */
- rUFCON1 = 0x06;
- rUMCON1 = 0x0;
- /* Normal,No parity,1 stop,8 bit */
- rULCON1 = 0x3;
- /*
- * tx=level,rx=edge,disable timeout int.,enable rx error int.,
- * normal,interrupt or polling
- */
- rUCON1 = 0x245;
- rUBRDIV1 = reg;
-
-#ifdef CONFIG_HWFLOW
- rUMCON1 = 0x1; /* RTS up */
-#endif
- for (i = 0; i < 100; i++);
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
}
/*
@@ -97,15 +91,12 @@
*/
int serial_getc (void)
{
-#ifdef CONFIG_SERIAL1
- while (!(rUTRSTAT0 & 0x1));
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+ /* wait for character to arrive */
+ while (!(uart->UTRSTAT & 0x1));
- return rURXH0 & 0xff;
-#elif CONFIG_SERIAL2
- while (!(rUTRSTAT1 & 0x1));
-
- return rURXH1 & 0xff;
-#endif
+ return uart->URXH & 0xff;
}
#ifdef CONFIG_HWFLOW
@@ -146,33 +137,22 @@
*/
void serial_putc (const char c)
{
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
return;
#endif
-#ifdef CONFIG_SERIAL1
- /* wait for room in the tx FIFO on SERIAL1 */
- while (!(rUTRSTAT0 & 0x2));
+ /* wait for room in the tx FIFO */
+ while (!(uart->UTRSTAT & 0x2));
#ifdef CONFIG_HWFLOW
/* Wait for CTS up */
- while(hwflow && !(rUMSTAT0 & 0x1))
+ while(hwflow && !(uart->UMSTAT & 0x1))
;
#endif
- rUTXH0 = c;
-#elif CONFIG_SERIAL2
- /* wait for room in the tx FIFO on SERIAL2 */
- while (!(rUTRSTAT1 & 0x2));
-
-#ifdef CONFIG_HWFLOW
- /* Wait for CTS up */
- while(hwflow && !(rUMSTAT1 & 0x1))
- ;
-#endif
- rUTXH1 = c;
-#endif
+ uart->UTXH = c;
/* If \n, also do \r */
if (c == '\n')
@@ -184,11 +164,9 @@
*/
int serial_tstc (void)
{
-#ifdef CONFIG_SERIAL1
- return rUTRSTAT0 & 0x1;
-#elif CONFIG_SERIAL2
- return rUTRSTAT1 & 0x1;
-#endif
+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+ return uart->UTRSTAT & 0x1;
}
void
diff --git a/cpu/arm920t/speed.c b/cpu/arm920t/speed.c
index 4942727..1f43543 100644
--- a/cpu/arm920t/speed.c
+++ b/cpu/arm920t/speed.c
@@ -51,12 +51,13 @@
static ulong get_PLLCLK(int pllreg)
{
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
ulong r, m, p, s;
if (pllreg == MPLL)
- r = rMPLLCON;
+ r = clk_power->MPLLCON;
else if (pllreg == UPLL)
- r = rUPLLCON;
+ r = clk_power->UPLLCON;
else
hang();
@@ -76,17 +77,17 @@
/* return HCLK frequency */
ulong get_HCLK(void)
{
- ulong clkdiv = rCLKDIVN;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- return((clkdiv & 0x2) ? get_FCLK()/2 : get_FCLK());
+ return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
- ulong clkdiv = rCLKDIVN;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- return((clkdiv & 0x1) ? get_HCLK()/2 : get_HCLK());
+ return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
}
/* return UCLK frequency */