commit 74a7e0532832a7437fdc7efa56afc8a938653564
author Shiraz Hashim <shiraz.hashim@st.com> Mon May 07 13:06:59 2012 +0530
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Sat Jul 07 14:07:42 2012 +0200
tree 9441156596340e8797fd535fc30a5cead8e7decf
parent 9b15c93ec1bee83ee717d5c9080443132389300f

SPEAr: explicitly select clk src for UART

UART in u-boot intends to run on 48MHz clock supplied by USB PLL.
Explicitly select the intended clock source.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

arch/arm/cpu/arm926ejs/spear/cpu.c

diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 9e074bc..e299de3 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -30,7 +30,7 @@
 {
 	struct misc_regs *const misc_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 periph1_clken;
+	u32 periph1_clken, periph_clk_cfg;
 
 	periph1_clken = readl(&misc_p->periph1_clken);
 
@@ -42,6 +42,11 @@
 
 #if defined(CONFIG_PL011_SERIAL)
 	periph1_clken |= MISC_UART0ENB;
+
+	periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
 #endif
 #if defined(CONFIG_DESIGNWARE_ETH)
 	periph1_clken |= MISC_ETHENB;