| commit | 749d537a737cddd15f6c4a30ed0bc9172a298f3c | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Thu Nov 29 10:31:02 2018 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Thu Nov 29 10:31:02 2018 +0100 |
| tree | f3d40f8eb70814b549f5d445fb1f602d8d9e9744 | |
| parent | 3cf07bf8b2de01f1bec59d7238f63d8bd07dfa24 [diff] |
ARM: zynq: Wire SPL configuration for cse nor/nand targets These symlinks are here only for testing purpose where SPL is used for soc configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>