diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 47002f8..4d714ad 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -210,7 +210,7 @@
  * claimed. This way, the dummy CS is restored to its inactive value when
  * transfers are issued and the desired CS is preserved in its active value
  * all the time. This hack is also used in the upstream linux driver and
- * allows keeping CS active between trasnfers even if the HW doesn't give
+ * allows keeping CS active between transfers even if the HW doesn't give
  * this possibility.
  */
 static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index ab0a681..973f455 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -392,7 +392,7 @@
 
 	plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
 
-	/* All other paramters are embedded in the child node */
+	/* All other parameters are embedded in the child node */
 	subnode = dev_read_first_subnode(bus);
 	if (!ofnode_valid(subnode)) {
 		printf("Error: subnode with SPI flash config missing!\n");
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 62444e4..8e5cc55 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -491,7 +491,7 @@
 
 	dm_spi_bus = dev_get_uclass_priv(bus);
 
-	/* cpu speical pin muxing configure */
+	/* cpu special pin muxing configure */
 	cpu_dspi_port_conf();
 
 	/* get input clk frequency */
@@ -600,7 +600,7 @@
 	plat->speed_hz = fdtdec_get_int(blob,
 			node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
 
-	debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
+	debug("DSPI: regs=%pa, max-frequency=%d, endianness=%s, num-cs=%d\n",
 	      &plat->regs_addr, plat->speed_hz,
 	      plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
 	      plat->num_chipselect);
diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c
index 5ea6277..3decb37 100644
--- a/drivers/spi/mtk_snfi_spi.c
+++ b/drivers/spi/mtk_snfi_spi.c
@@ -153,7 +153,7 @@
 
 	/*
 	 * The output data will always be copied to the beginning of
-	 * the GPRAM. Uses word write for better performace.
+	 * the GPRAM. Uses word write for better performance.
 	 *
 	 * Trailing bytes in the last word are not cared.
 	 */
@@ -180,7 +180,7 @@
 
 	/*
 	 * Read aligned data from GPRAM to buffer first.
-	 * Uses word read for better performace.
+	 * Uses word read for better performance.
 	 */
 	i = 0;
 	while (pos < end) {
diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index b1dce04..52882e8 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -84,7 +84,7 @@
  * The XFER_RDY flag is checked every time before accessing SPI_DOUT
  * and SPI_DIN register.
  *
- * The number of transfers to be triggerred is decided by @bytelen.
+ * The number of transfers to be triggered is decided by @bytelen.
  *
  * Return:	0 - cool
  *		-ETIMEDOUT - XFER_RDY flag timeout
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index ea38a0f..1cbb5d4 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -142,7 +142,7 @@
 			}
 		}
 
-		/* Disable the channel to prevent furher receiving */
+		/* Disable the channel to prevent further receiving */
 		if (i == (len - 1))
 			omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
 
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index cb80be7..66b20fc 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -485,7 +485,7 @@
 		/*
 		 * In case that there's a transmit-component, we need to wait
 		 * until the control goes idle before we can disable the SPI
-		 * control logic (as this will implictly flush the FIFOs).
+		 * control logic (as this will implicitly flush the FIFOs).
 		 */
 		if (out) {
 			ret = rkspi_wait_till_not_busy(regs);
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index a3c9633..4b6ea9f 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -270,7 +270,7 @@
 		flashes[cs].ahb_decoded_sz = priv->info->min_decoded_sz;
 
 	/*
-	 * If commnad mode or normal mode is used, the start address of a
+	 * If command mode or normal mode is used, the start address of a
 	 * decoded range should be multiple of its related flash size.
 	 * Namely, the total decoded size from flash 0 to flash N should
 	 * be multiple of the size of flash (N + 1).
@@ -404,7 +404,7 @@
 		flashes[cs].ahb_decoded_sz = 0;
 
 	/*
-	 * If commnad mode or normal mode is used, the start address of a
+	 * If command mode or normal mode is used, the start address of a
 	 * decoded range should be multiple of its related flash size.
 	 * Namely, the total decoded size from flash 0 to flash N should
 	 * be multiple of the size of flash (N + 1).
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index cdea540..7b64532 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -233,7 +233,7 @@
 }
 
 /*
- * Function to check wheather Input or Output FIFO
+ * Function to check whether Input or Output FIFO
  * has data to be serviced
  */
 static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
index 0a00df0..ea372a0 100644
--- a/drivers/spi/spi-sifive.c
+++ b/drivers/spi/spi-sifive.c
@@ -350,7 +350,7 @@
 	if (speed > spi->freq)
 		speed = spi->freq;
 
-	/* Cofigure max speed */
+	/* Configure max speed */
 	scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
 					& SIFIVE_SPI_SCKDIV_DIV_MASK;
 	writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);