commit 739cd6fb9afd376de1d6825b0835397cae359ea7
author Yu Chien Peter Lin <peterlin@andestech.com> Tue Oct 25 23:03:50 2022 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> Thu Nov 03 13:27:56 2022 +0800
tree 74a91e18cd008f381c12d615587912630530bed3
parent 12a195515fc31bc0c61ba40584bd78ce015b631c

riscv: Rename Andes PLIC to PLICSW

As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

arch/riscv/lib/Makefile

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 06020fc..d6a8ae9 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -13,7 +13,7 @@
 obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
-obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
 else
 obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o

arch/riscv/lib/andes_plicsw.c

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plicsw.c
similarity index 76%
rename from arch/riscv/lib/andes_plic.c
rename to arch/riscv/lib/andes_plicsw.c
index 1eabcac..324eb44 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -37,8 +37,8 @@
 	unsigned int en;
 
 	en = ENABLE_HART_IPI << hart;
-	writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
-	writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart));
+	writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
+	writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
 
 	return 0;
 }
@@ -46,14 +46,14 @@
 int riscv_init_ipi(void)
 {
 	int ret;
-	long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+	long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW);
 	ofnode node;
 	struct udevice *dev;
 	u32 reg;
 
 	if (IS_ERR(base))
 		return PTR_ERR(base);
-	gd->arch.plic = base;
+	gd->arch.plicsw = base;
 
 	ret = uclass_find_first_device(UCLASS_CPU, &dev);
 	if (ret)
@@ -88,7 +88,7 @@
 {
 	unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 
-	writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
+	writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
 				gd->arch.boot_hart));
 
 	return 0;
@@ -98,8 +98,8 @@
 {
 	u32 source_id;
 
-	source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
-	writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+	source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
+	writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
 
 	return 0;
 }
@@ -108,21 +108,21 @@
 {
 	unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 
-	*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+	*pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
 						     gd->arch.boot_hart));
 	*pending = !!(*pending & ipi);
 
 	return 0;
 }
 
-static const struct udevice_id andes_plic_ids[] = {
-	{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
+static const struct udevice_id andes_plicsw_ids[] = {
+	{ .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW },
 	{ }
 };
 
-U_BOOT_DRIVER(andes_plic) = {
-	.name		= "andes_plic",
+U_BOOT_DRIVER(andes_plicsw) = {
+	.name		= "andes_plicsw",
 	.id		= UCLASS_SYSCON,
-	.of_match	= andes_plic_ids,
+	.of_match	= andes_plicsw_ids,
 	.flags		= DM_FLAG_PRE_RELOC,
 };