tree 8a91be7ed4a303cc512eebbdffd026f45a946025
parent b9e8e3b21ba2451c541cdd7f43239c112f47909f
author Romain Perier <romain.perier@collabora.com> 1496395183 +0200
committer Simon Glass <sjg@chromium.org> 1496892648 -0600

rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE

RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit
0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and
introduces random delays and data lose.

This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
with the right shift.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>