tree dd50d27edd90cb80c97a45c97f842a08fb0c00a8
parent 1facc0f36c0c419715e6d9b9400afb88e0776672
author Jernej Skrabec <jernej.skrabec@siol.net> 1584035160 +0000
committer Andre Przywara <andre.przywara@arm.com> 1610407174 +0000

sunxi: dram: h6: Improve DDR3 config detection

It turns out that in rare cases, current analytical approach to detect
correct DRAM bus width and rank on H6 doesn't work. On some TV boxes
with DDR3, incorrect DRAM configuration triggers write leveling error
which immediately stops initialization process. Exact reason why this
error appears isn't known. However, if correct configuration is used,
initalization works without problem.

In order to fix this issue, simply try another configuration when any
kind of error appears during initialization, not just those related to
rank and bus width.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Tested-by: Thomas Graichen <thomas.graichen@googlemail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>