tree f7c79c497e2159cea8306c7a0d343039b31e455a
parent cb1337c4f066d7939f0e9221e7055bf312813eca
author Ye Li <ye.li@nxp.com> 1526301869 -0300
committer Stefano Babic <sbabic@denx.de> 1529331685 +0200

imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platforms

According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode,
it is not set.
Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
including mx7d, mx6ul/ull and mx7ulp.

Signed-off-by: Ye Li <ye.li@nxp.com>
[fabio: adapted to U-Boot mainline codebase and make checkpatch happy]
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>