commit 732225a667ecb92d740b121f3ad46bf431eafc76
author Mayuresh Chitale <mchitale@ventanamicro.com> Thu Nov 16 22:13:36 2023 +0530
committer Michal Simek <michal.simek@amd.com> Wed Dec 13 08:58:06 2023 +0100
tree 08b9400777fae5191086c8936d1cf364a39a3327
parent 73f425fdc716ef03b904a4c400032a60b9ec752a

drivers: xilinx_spi: Probe fifo_depth at runtime

If the fifo-size DT parameter is not provided then probe the
controller's fifo depth at runtime. This is ported from a patch
in the Linux Xilinx SPI driver.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1422029330-10971-5-git-send-email-ricardo.ribalda@gmail.com
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20231116164336.140171-4-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

drivers/spi/xilinx_spi.c

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index b63cda2..94ddf49 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -109,6 +109,27 @@
 	u8 startup;
 };
 
+static int xilinx_spi_find_buffer_size(struct xilinx_spi_regs *regs)
+{
+	u8 sr;
+	int n_words = 0;
+
+	/*
+	 * Before the buffer_size detection reset the core
+	 * to make sure to start with a clean state.
+	 */
+	writel(SPISSR_RESET_VALUE, &regs->srr);
+
+	/* Fill the Tx FIFO with as many words as possible */
+	do {
+		writel(0, &regs->spidtr);
+		sr = readl(&regs->spisr);
+		n_words++;
+	} while (!(sr & SPISR_TX_FULL));
+
+	return n_words;
+}
+
 static int xilinx_spi_probe(struct udevice *bus)
 {
 	struct xilinx_spi_priv *priv = dev_get_priv(bus);
@@ -116,6 +137,8 @@
 
 	regs = priv->regs = dev_read_addr_ptr(bus);
 	priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
+	if (!priv->fifo_depth)
+		priv->fifo_depth = xilinx_spi_find_buffer_size(regs);
 
 	writel(SPISSR_RESET_VALUE, &regs->srr);