ARM: dts: sun8i: Sync r40 dtsi from Linux
Sync sun8i-r40.dtsi changes from Linux with
Merge: a406778618d0 088345fc3553
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Tue Apr 24 14:15:02 2018 +1000
Merge branch 'akpm/master'
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index 48ec2e8..0aa76a2 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -43,6 +43,8 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
/ {
#address-cells = <1>;
@@ -114,6 +116,39 @@
#size-cells = <1>;
ranges;
+ nmi_intc: interrupt-controller@1c00030 {
+ compatible = "allwinner,sun7i-a20-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c00030 0x0c>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun8i-r40-mmc",
+ "allwinner,sun50i-a64-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ccu: clock@1c20000 {
+ compatible = "allwinner,sun8i-r40-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
@@ -132,6 +167,14 @@
bias-pull-up;
};
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2",
+ "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
uart0_pb_pins: uart0_pb_pins {
pins = "PB22", "PB23";
function = "uart0";