commit 72e94989dd2a964f3cc8ccf69706c6082639024a
author Jagan Teki <jagan@amarulasolutions.com> Sun Aug 05 00:40:11 2018 +0530
committer Jagan Teki <jagan@amarulasolutions.com> Fri Sep 28 22:09:24 2018 +0530
tree fbf5ba73c82d359e5bb83ad25f12a0960a840f7c
parent cb80dd17e5638d0758762ae2857c576a4189cb23

ARM: dts: sun8i: Update A23/A33/r16 dts(i) files from Linux-v4.18-rc3

Update all A23/A33/r16 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.

A23:
commit bc3bd041fe766219a44688b182c260064007f0cc
Author: Miquel Raynal <miquel.raynal@bootlin.com>
Date:   Tue Apr 24 17:55:02 2018 +0200

    ARM: dts: sun8i: a23/a33: declare NAND pins

A33:
commit 88fe315d2c0a397ef42d7639addab0e021ae911d
Author: Maxime Ripard <maxime.ripard@bootlin.com>
Date:   Wed Apr 4 11:57:15 2018 +0200

    ARM: dts: sun8i: a33: Add the DSI-related nodes

r16:
commit 9621d0bd1b0d61167e1853ac68cf4869c31bcc96
Author: Miquel Raynal <miquel.raynal@bootlin.com>
Date:   Tue Apr 24 17:55:03 2018 +0200

    ARM: dts: nes: add Nintendo NES/SuperNES Classic Edition support

Note:
- Drop pinctrl from sun8i-r16-nintendo-nes-classic-edition.dts since
  sun8i-a23-a33.dtsi is added with Linux sync.
- Don't sync non U-Boot supported dts files
   sun8i-a23-ippo-q8h-v1.2.dts
   sun8i-a23-ippo-q8h-v5.dts
   sun8i-a33-et-q8-v1.6.dts
   sun8i-a33-ippo-q8h-v1.2.dts
   sun8i-r16-nintendo-nes-classic.dts
   sun8i-r16-nintendo-super-nes-classic.dts

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

arch/arm/dts/sun8i-a33-sinlinx-sina33.dts

diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
index b1bc88c..541acb4 100644
--- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
 	model = "Sinlinx SinA33";
@@ -80,7 +79,7 @@
 	};
 };
 
-&de {
+&codec {
 	status = "okay";
 };
 
@@ -88,6 +87,28 @@
 	cpu-supply = <&reg_dcdc3>;
 };
 
+&cpu0_opp_table {
+	opp-1104000000 {
+		opp-hz = /bits/ 64 <1104000000>;
+		opp-microvolt = <1320000>;
+		clock-latency-ns = <244144>; /* 8 32k periods */
+	};
+
+	opp-1200000000 {
+		opp-hz = /bits/ 64 <1200000000>;
+		opp-microvolt = <1320000>;
+		clock-latency-ns = <244144>; /* 8 32k periods */
+	};
+};
+
+&de {
+	status = "okay";
+};
+
+&dai {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -123,8 +144,7 @@
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
 	vmmc-supply = <&reg_dcdc1>;
 	bus-width = <4>;
-	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-	cd-inverted;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
 	status = "okay";
 };
 
@@ -140,9 +160,9 @@
 
 &mmc2_8bit_pins {
 	/* Increase drive strength for DDR modes */
-	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+	drive-strength = <40>;
 	/* eMMC is missing pull-ups */
-	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	bias-pull-up;
 };
 
 &ohci0 {
@@ -151,10 +171,9 @@
 
 &pio {
 	mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
-		allwinner,pins = "PB4";
-		allwinner,function = "gpio_in";
-		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+		pins = "PB4";
+		function = "gpio_in";
+		bias-pull-up;
 	};
 };
 
@@ -170,7 +189,15 @@
 	};
 };
 
+#include "axp223.dtsi"
+
-#include "axp22x.dtsi"
+&ac_power_supply {
+	status = "okay";
+};
+
+&battery_power_supply {
+	status = "okay";
+};
 
 &reg_aldo1 {
 	regulator-always-on;
@@ -232,6 +259,10 @@
 	regulator-name = "vcc-rtc";
 };
 
+&sound {
+	status = "okay";
+};
+
 &tcon0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&lcd_rgb666_pins>;