commit 72cc53897fd104911dff82aefc3624757ebcecd0
author Simon Glass <sjg@chromium.org> Thu Oct 20 18:22:39 2022 -0600
committer Tom Rini <trini@konsulko.com> Mon Oct 31 11:01:31 2022 -0400
tree 472bf7e47978335a73c5d6025d3b83b534f7192b
parent 4078fec1ee6a908821051e849763ac63d0e9c62a

Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE

The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>

arch/x86/cpu/apollolake/spl.c

diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
index f2d2573..6078d5a 100644
--- a/arch/x86/cpu/apollolake/spl.c
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -118,7 +118,7 @@
 
 	spl_image->size = CONFIG_SYS_MONITOR_LEN;  /* We don't know SPL size */
 	spl_image->entry_point = spl_phase() == PHASE_TPL ?
-		CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
+		CONFIG_SPL_TEXT_BASE : CONFIG_TEXT_BASE;
 	spl_image->load_addr = spl_image->entry_point;
 	spl_image->os = IH_OS_U_BOOT;
 	spl_image->name = "U-Boot";

arch/x86/cpu/quark/quark.c

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index e016fae..0a1fbb3 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -49,7 +49,7 @@
 
 	/* variable range MTRR#0: ROM area */
 	mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
-	base = CONFIG_SYS_TEXT_BASE & mask;
+	base = CONFIG_TEXT_BASE & mask;
 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
 		       base | MTRR_TYPE_WRBACK);
 	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),

arch/x86/cpu/start.S

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 897fd92..0ef27cc 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -237,15 +237,15 @@
 	/* checksum */
 	.long	-0x1BADB002 - (1 << 16)
 	/* header addr */
-	.long	multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE
+	.long	multiboot_header - _x86boot_start + CONFIG_TEXT_BASE
 	/* load addr */
-	.long	CONFIG_SYS_TEXT_BASE
+	.long	CONFIG_TEXT_BASE
 	/* load end addr */
 	.long	0
 	/* bss end addr */
 	.long	0
 	/* entry addr */
-	.long	CONFIG_SYS_TEXT_BASE
+	.long	CONFIG_TEXT_BASE
 
 #ifdef CONFIG_X86_LOAD_FROM_32_BIT
 	/*

arch/x86/cpu/u-boot-64.lds

diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds
index 53c5604..d0398ff 100644
--- a/arch/x86/cpu/u-boot-64.lds
+++ b/arch/x86/cpu/u-boot-64.lds
@@ -15,8 +15,8 @@
 	/DISCARD/ : { *(__u_boot_list_2_cmd_*) }
 #endif
 
-#ifdef CONFIG_SYS_TEXT_BASE
-	. = CONFIG_SYS_TEXT_BASE;	/* Location of bootcode in flash */
+#ifdef CONFIG_TEXT_BASE
+	. = CONFIG_TEXT_BASE;	/* Location of bootcode in flash */
 #endif
 	__text_start = .;
 

arch/x86/cpu/u-boot.lds

diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index 7c87209..a31f422 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -15,7 +15,7 @@
 	/DISCARD/ : { *(__u_boot_list_2_cmd_*) }
 #endif
 
-	. = CONFIG_SYS_TEXT_BASE;	/* Location of bootcode in flash */
+	. = CONFIG_TEXT_BASE;	/* Location of bootcode in flash */
 	__text_start = .;
 
 	.text.start : { *(.text.start); }