| commit | 7264aaedf7ec033cb042fcb61e21fd0b52aa0cc2 | [log] [tgz] |
|---|---|---|
| author | Patrice Chotard <patrice.chotard@st.com> | Wed Apr 11 17:07:45 2018 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Tue May 08 09:07:34 2018 -0400 |
| tree | ea0eb1eb7e28a3dba811bed5f1532a3acc2e296a | |
| parent | b58adfe438f315341dd60051a18b5e6a64ba44b3 [diff] [blame] |
clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI output P can be used as 48MHz clock source for USB and SDMMC. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Tested By: Bruno Herrera <bruherrera@gmail.com>
diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index 748c2eb..71da3c1 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h
@@ -40,7 +40,8 @@ }; enum soc_family { - STM32F4, + STM32F42X, + STM32F469, STM32F7, };