commit 7259dc50088fc041e436357b52b96009927c541e
author Michael Walle <michael@walle.cc> Wed Mar 17 15:01:37 2021 +0100
committer Peng Fan <peng.fan@nxp.com> Tue Apr 06 18:36:04 2021 +0800
tree 3acce1e9caed60d740445948f654d35f6445e731
parent 148dc613817a232ef28fb9464fef54b26e47f923

mmc: fsl_esdhc: add pulse width detection workaround

HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
workaroung for the pulse width detection. Apply this workaround in
u-boot, too.

This will make HS400 mode work reliably on the LS1028A SoC.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

drivers/mmc/Kconfig

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index b0ff92b..4925675 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -816,3 +816,6 @@
 
 config SYS_FSL_ERRATUM_A011334
 	bool
+
+config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
+	bool

drivers/mmc/fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 09ea1a9..7501fdb 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -71,7 +71,8 @@
 	uint	sdtimingctl;	/* SD timing control register */
 	char    reserved8[20];	/* reserved */
 	uint	dllcfg0;	/* DLL config 0 register */
-	char	reserved9[12];	/* reserved */
+	uint	dllcfg1;	/* DLL config 1 register */
+	char	reserved9[8];	/* reserved */
 	uint	dllstat0;	/* DLL status 0 register */
 	char    reserved10[664];/* reserved */
 	uint    esdhcctl;	/* eSDHC control register */
@@ -767,6 +768,9 @@
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
+	if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
+		esdhc_clrbits32(&regs->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
+
 	return 0;
 }