Enable L2 cache parity/ECC error checking
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 48e6a05..d5b17de 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -337,7 +337,7 @@
while ((in_be32(&l2cache->l2csr0)
& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
;
- out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+ out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE);
}
i++;
} while (!(cluster & TP_CLUSTER_EOC));
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 5542d0a..87168e2 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -734,7 +734,7 @@
isync
and. r1, r0, r4
bne 1b
- lis r4, L2CSR0_L2E@h
+ lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
sync
stw r4, 0(r3) /* enable L2 */
delete_ccsr_l2_tlb: