diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 0db6199..4825611 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -78,12 +78,12 @@
 	mfsdr(SDR0_ULTRA1, reg);
 	mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
 
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000010);
-	mtdcr(uicpr, 0xFE7FFFF0);	/* set int polarities */
-	mtdcr(uictr, 0x00000010);	/* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000010);
+	mtdcr(UIC0PR, 0xFE7FFFF0);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000010);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 2ffd720..38186a5 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -392,21 +392,21 @@
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	/*--------------------------------------------------------------------
 	 * Setup the GPIO pins
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index d0aebec..49eadb9 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -29,12 +29,12 @@
 
 int board_early_init_f(void)
 {
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000010);
-	mtdcr(uicpr, 0xFFFF7FF0);	/* set int polarities */
-	mtdcr(uictr, 0x00000010);	/* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000010);
+	mtdcr(UIC0PR, 0xFFFF7FF0);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000010);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/*
 	 * Configure CPC0_PCI to enable PerWE as output
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 3a03f30..f359d23 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -116,37 +116,37 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic3sr, 0xffffffff);	/* clear all */
-	mtdcr(uic3er, 0x00000000);	/* disable all */
-	mtdcr(uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic3pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic3tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic3sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
 
 #if !defined(CONFIG_ARCHES)
 	/* SDR Setting - enable NDFC */
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index 2439b03..0543bad 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -71,21 +71,21 @@
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	return 0;
 }
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 1a45056..bcef707 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -183,42 +183,42 @@
 	 * Set critical interrupt values.  Set interrupt polarities.  Set interrupt
 	 * trigger levels.  Make bit 0 High  priority.  Clear all interrupts again.
 	 *------------------------------------------------------------------------*/
-	mtdcr (uic3sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic3er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic3cr, 0x00000000);	/* Set Critical / Non Critical interrupts: */
-	mtdcr (uic3pr, 0xffffffff);	/* Set Interrupt Polarities*/
-	mtdcr (uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic3vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic3sr, 0x00000000);	/* clear all  interrupts*/
-	mtdcr (uic3sr, 0xffffffff);	/* clear all  interrupts*/
+	mtdcr (UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC3CR, 0x00000000);	/* Set Critical / Non Critical interrupts: */
+	mtdcr (UIC3PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr (UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC3SR, 0x00000000);	/* clear all  interrupts*/
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all  interrupts*/
 
 
-	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic2er, 0x00000000);	/* disable all interrupts*/
-	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical interrupts*/
-	mtdcr (uic2pr, 0xebebebff);	/* Set Interrupt Polarities*/
-	mtdcr (uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (UIC2PR, 0xebebebff);	/* Set Interrupt Polarities*/
+	mtdcr (UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts*/
-	mtdcr (uic1er, 0x00000000);	/* disable all interrupts*/
-	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical interrupts*/
-	mtdcr (uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (uic1tr, 0x001f8040);	/* Set Interrupt Trigger Levels*/
-	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts*/
-	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts*/
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts*/
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels*/
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts*/
 
-	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic0er, 0x00000000);	/* disable all interrupts excepted cascade    to be checked */
-	mtdcr (uic0cr, 0x00104001);	/* Set Critical / Non Critical interrupts*/
-	mtdcr (uic0pr, 0xffffffff);	/* Set Interrupt Polarities*/
-	mtdcr (uic0tr, 0x010f0004);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts*/
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all interrupts excepted cascade    to be checked */
+	mtdcr (UIC0CR, 0x00104001);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (UIC0PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr (UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts*/
 
 	mfsdr(SDR0_MFR, mfr);
 	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 7e84a61..5ebe692 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -158,33 +158,33 @@
 	 | interrupts again.
 	 +-------------------------------------------------------------------*/
 
-	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic2er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (uic2pr, 0xf7ffffff);	/* Set Interrupt Polarities */
-	mtdcr (uic2tr, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC2PR, 0xf7ffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC2TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic1er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (uic1pr, 0xfffac785);	/* Set Interrupt Polarities */
-	mtdcr (uic1tr, 0x001d0040);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC1PR, 0xfffac785);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic0er, 0x0000000a);	/* Disable all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x0000000a);	/* Disable all interrupts */
 					/* Except cascade UIC0 and UIC1 */
-	mtdcr (uic0cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (uic0pr, 0xffbfefef);	/* Set Interrupt Polarities */
-	mtdcr (uic0tr, 0x00007000);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC0CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC0PR, 0xffbfefef);	/* Set Interrupt Polarities */
+	mtdcr (UIC0TR, 0x00007000);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
 
 	/*
 	 * Note: Some cores are still in reset when the chip starts, so
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 71ad89f..5f76672 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -49,23 +49,23 @@
 	mtebc( PB2AP,  0x03800000 );
 	mtebc( PB2CR,  0xff838000 );	/* ebc0_b2cr, 2MB at 0xff800000 CS2 */
 
-	mtdcr( uic1sr, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( uic1er, 0x00000000 );	/* disable all interrupts */
-	mtdcr( uic1cr, 0x00000000 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( uic1pr, 0x7fff83ff );	/* Set Interrupt Polarities */
-	mtdcr( uic1tr, 0x001f8000 );	/* Set Interrupt Trigger Levels */
-	mtdcr( uic1vr, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( uic1sr, 0x00000000 );	/* clear all interrupts */
-	mtdcr( uic1sr, 0xffffffff );
+	mtdcr( UIC1SR, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( UIC1ER, 0x00000000 );	/* disable all interrupts */
+	mtdcr( UIC1CR, 0x00000000 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( UIC1PR, 0x7fff83ff );	/* Set Interrupt Polarities */
+	mtdcr( UIC1TR, 0x001f8000 );	/* Set Interrupt Trigger Levels */
+	mtdcr( UIC1VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( UIC1SR, 0x00000000 );	/* clear all interrupts */
+	mtdcr( UIC1SR, 0xffffffff );
 
-	mtdcr( uic0sr, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( uic0er, 0x00000000 );	/* disable all interrupts excepted cascade */
-	mtdcr( uic0cr, 0x00000001 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( uic0pr, 0xffffffff );	/* Set Interrupt Polarities */
-	mtdcr( uic0tr, 0x01000004 );	/* Set Interrupt Trigger Levels */
-	mtdcr( uic0vr, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( uic0sr, 0x00000000 );	/* clear all interrupts */
-	mtdcr( uic0sr, 0xffffffff );
+	mtdcr( UIC0SR, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( UIC0ER, 0x00000000 );	/* disable all interrupts excepted cascade */
+	mtdcr( UIC0CR, 0x00000001 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( UIC0PR, 0xffffffff );	/* Set Interrupt Polarities */
+	mtdcr( UIC0TR, 0x01000004 );	/* Set Interrupt Trigger Levels */
+	mtdcr( UIC0VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( UIC0SR, 0x00000000 );	/* clear all interrupts */
+	mtdcr( UIC0SR, 0xffffffff );
 
 	mfsdr(SDR0_MFR, mfr);
 	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 9fc0ec6..fb0e7b7 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -159,33 +159,33 @@
 	 | interrupts again.
 	 +-------------------------------------------------------------------*/
 
-	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic2er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (uic2pr, 0xf7ffffff);	/* Set Interrupt Polarities */
-	mtdcr (uic2tr, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC2PR, 0xf7ffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC2TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic1er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (uic1pr, 0xfffac785);	/* Set Interrupt Polarities */
-	mtdcr (uic1tr, 0x001d0040);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC1PR, 0xfffac785);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic0er, 0x0000000a);	/* Disable all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x0000000a);	/* Disable all interrupts */
 					/* Except cascade UIC0 and UIC1 */
-	mtdcr (uic0cr, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (uic0pr, 0xffbfefef);	/* Set Interrupt Polarities */
-	mtdcr (uic0tr, 0x00007000);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC0CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
+	mtdcr (UIC0PR, 0xffbfefef);	/* Set Interrupt Polarities */
+	mtdcr (UIC0TR, 0x00007000);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
 
 	/*
 	 * Note: Some cores are still in reset when the chip starts, so
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 5e32e8a..8513f43 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -159,36 +159,36 @@
 	 * UIC2		UIC1
 	 * UIC3		UIC2
 	 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
-	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic1pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (UIC1PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (UIC1TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
-	mtdcr (uic2er, 0x00000000);	/* disable all */
-	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
-	mtdcr (uic3er, 0x00000000);	/* disable all */
-	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
-	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic0sr, 0xfc000000); /* clear all */
-	mtdcr (uic0er, 0x00000000); /* disable all */
-	mtdcr (uic0cr, 0x00000000); /* all non-critical */
-	mtdcr (uic0pr, 0xfc000000); /* */
-	mtdcr (uic0tr, 0x00000000); /* */
-	mtdcr (uic0vr, 0x00000001); /* */
+	mtdcr (UIC0SR, 0xfc000000); /* clear all */
+	mtdcr (UIC0ER, 0x00000000); /* disable all */
+	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000); /* */
+	mtdcr (UIC0TR, 0x00000000); /* */
+	mtdcr (UIC0VR, 0x00000001); /* */
 	mfsdr (SDR0_MFR, mfr);
 	mfr &= ~SDR0_MFR_ECS_MASK;
 /*	mtsdr(SDR0_MFR, mfr); */
diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
index 49078eb..bc8cb0c 100644
--- a/board/amcc/redwood/redwood.c
+++ b/board/amcc/redwood/redwood.c
@@ -416,41 +416,41 @@
 	 * interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 	 * interrupts again.
 	 */
-	mtdcr(uic3sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(uic3er, 0x00000000);	/* disable all interrupts */
-	mtdcr(uic3cr, 0x00000000);	/* Set Critical / Non Critical
+	mtdcr(UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC3CR, 0x00000000);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr(uic3pr, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr(uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
-	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic3sr, 0xffffffff);	/* clear all  interrupts */
+	mtdcr(UIC3PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all  interrupts */
 
-	mtdcr(uic2sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(uic2er, 0x00000000);	/* disable all interrupts */
-	mtdcr(uic2cr, 0x00000000);	/* Set Critical / Non Critical
+	mtdcr(UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC2CR, 0x00000000);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr(uic2pr, 0xebebebff);	/* Set Interrupt Polarities */
-	mtdcr(uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr(UIC2PR, 0xebebebff);	/* Set Interrupt Polarities */
+	mtdcr(UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr(uic1sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(uic1er, 0x00000000);	/* disable all interrupts */
-	mtdcr(uic1cr, 0x00000000);	/* Set Critical / Non Critical
+	mtdcr(UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC1CR, 0x00000000);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr(uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr(uic1tr, 0x001fc0ff);	/* Set Interrupt Trigger Levels */
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr(UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC1TR, 0x001fc0ff);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr(uic0sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(uic0er, 0x00000000);	/* disable all interrupts excepted
+	mtdcr(UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all interrupts excepted
 					 * cascade to be checked */
-	mtdcr(uic0cr, 0x00104001);	/* Set Critical / Non Critical
+	mtdcr(UIC0CR, 0x00104001);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr(uic0pr, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr(uic0tr, 0x000f003c);	/* Set Interrupt Trigger Levels */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr(UIC0PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC0TR, 0x000f003c);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all interrupts */
 
 }
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 5913455..17f831c 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -52,29 +52,29 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
 	/* 50MHz tmrclk */
 	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index 4e5796e..be381d6 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -40,13 +40,13 @@
 {
 	lcd_init();
 
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);
-	mtdcr(uicpr, 0xFFFF7F00);	/* set int polarities */
-	mtdcr(uictr, 0x00000000);	/* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7F00);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
 
 	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);	/* memory bank 3 (CPLD_LCM) initialization */
 	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 086778a..4a0573e 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -132,36 +132,36 @@
 	 * UIC2		UIC1
 	 * UIC3		UIC2
 	 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
-	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic1pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (UIC1PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (UIC1TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
-	mtdcr (uic2er, 0x00000000);	/* disable all */
-	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
-	mtdcr (uic3er, 0x00000000);	/* disable all */
-	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
-	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic0sr, 0xfc000000);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic0pr, 0xfc000000);	/* */
-	mtdcr (uic0tr, 0x00000000);	/* */
-	mtdcr (uic0vr, 0x00000001);	/* */
+	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all */
+	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000);	/* */
+	mtdcr (UIC0TR, 0x00000000);	/* */
+	mtdcr (UIC0VR, 0x00000001);	/* */
 
 	/* Enable two GPIO 10~11 and TraceA signal */
 	mfsdr(SDR0_PFC0,reg);
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index 28dcb66..4f29932 100644
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -47,13 +47,13 @@
 	  |
 	  +-------------------------------------------------------------------------*/
 
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
-	mtdcr(uicpr, 0xFFFFFFE0);	/* set int polarities */
-	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFFE0);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/* set UART1 control to select CTS/RTS */
 #define FPGA_BRDC       0xF0300004
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 2a654fa..731d441 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -82,21 +82,21 @@
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	/*--------------------------------------------------------------------
 	 * Setup other serial configuration
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 245004c..033bdd2 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -485,50 +485,50 @@
 	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 	 | interrupts again.
 	 +-------------------------------------------------------------------*/
-	mtdcr (uic3sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic3er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic3cr, 0x00000000);	/* Set Critical / Non Critical
+	mtdcr (UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC3CR, 0x00000000);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr (uic3pr, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic3vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+	mtdcr (UIC3PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
 					 * priority */
-	mtdcr (uic3sr, 0x00000000);	/* clear all  interrupts */
-	mtdcr (uic3sr, 0xffffffff);	/* clear all  interrupts */
+	mtdcr (UIC3SR, 0x00000000);	/* clear all  interrupts */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all  interrupts */
 
-	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic2er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical
+	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr (uic2pr, 0xebebebff);	/* Set Interrupt Polarities */
-	mtdcr (uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+	mtdcr (UIC2PR, 0xebebebff);	/* Set Interrupt Polarities */
+	mtdcr (UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
 					 * priority */
-	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic1er, 0x00000000);	/* disable all interrupts */
-	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical
+	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
+	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr (uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (uic1tr, 0x001f8040);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+	mtdcr (UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
 					 * priority */
-	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
 
-	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (uic0er, 0x00000000);	/* disable all interrupts excepted
+	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all interrupts excepted
 					 * cascade to be checked */
-	mtdcr (uic0cr, 0x00104001);	/* Set Critical / Non Critical
+	mtdcr (UIC0CR, 0x00104001);	/* Set Critical / Non Critical
 					 * interrupts */
-	mtdcr (uic0pr, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (uic0tr, 0x010f0004);	/* Set Interrupt Trigger Levels */
-	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest
+	mtdcr (UIC0PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
 					 * priority */
-	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts */
+	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
+	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
 
 	mfsdr(SDR0_MFR, mfr);
 	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 5d1c417..7913071 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -113,13 +113,13 @@
 {
 	/* Running from ROM: global data is still READONLY */
 	init_sdram ();
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
-	mtdcr (uicpr, 0xFFFFFFE0);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFFE0);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	return 0;
 }
 
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index cb24cd4..740e3ac 100644
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -87,13 +87,13 @@
    |
    +-------------------------------------------------------------------------*/
 
-	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
-	mtdcr (uicer, 0x00000000);   /* disable all ints */
-	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
-	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
 
 	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
 
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index fa0fa19..0c7760a 100644
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -55,13 +55,13 @@
    |
    +-------------------------------------------------------------------------*/
 
-	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
-	mtdcr (uicer, 0x00000000);   /* disable all ints */
-	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
-	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
 
 	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
 
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
index 56751e1..06de6e0 100644
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -53,13 +53,13 @@
 	 * IRQ 30 (EXT IRQ 5)
 	 * IRQ 31 (EXT IRQ 6)
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/eric/eric.c b/board/eric/eric.c
index bc2a907..cfcfa52 100644
--- a/board/eric/eric.c
+++ b/board/eric/eric.c
@@ -62,13 +62,13 @@
    |
    +-------------------------------------------------------------------------*/
 
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all SMI to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF88);	/* set int polarities; IRQ3 to 1 */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels, UART0 is EDGE */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all SMI to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF88);	/* set int polarities; IRQ3 to 1 */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels, UART0 is EDGE */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	mtdcr (CPC0_CR0, 0x00002000);	/* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
 
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index 46622a2..409a054 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -155,13 +155,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
index 9d1b6d2..a632cb4 100644
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@@ -130,13 +130,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF81);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
 
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
index 8da08fa..5f0e67c 100644
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@@ -66,13 +66,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
index 418d3e2..5a3f61d 100644
--- a/board/esd/canbt/canbt.c
+++ b/board/esd/canbt/canbt.c
@@ -134,13 +134,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF81);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 7a92401..391fbf4 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -45,13 +45,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index 00c7024..6d9814f 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -58,14 +58,14 @@
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) unused
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
 
-	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 4c9ed2f..c29c876 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -179,22 +179,22 @@
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
 #if defined(CONFIG_CPCI405_6U)
 	if (cpci405_version() == 3) {
-		mtdcr(uicpr, 0xFFFFFF99);	/* set int polarities */
+		mtdcr(UIC0PR, 0xFFFFFF99);	/* set int polarities */
 	} else {
-		mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
+		mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
 	}
 #else
-	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
+	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
 #endif
-	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,
 					 * INT0 highest priority */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
index 6e97392..ee90e2c 100644
--- a/board/esd/cpciiser4/cpciiser4.c
+++ b/board/esd/cpciiser4/cpciiser4.c
@@ -129,14 +129,14 @@
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	/*  mtdcr(uicpr, 0xFFFFFF81);   /  set int polarities */
-	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	/*  mtdcr(UIC0PR, 0xFFFFFF81);   /  set int polarities */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
index fc0d091..228a570 100644
--- a/board/esd/dp405/dp405.c
+++ b/board/esd/dp405/dp405.c
@@ -43,13 +43,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index 28a50c7..f475d11 100644
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -124,13 +124,13 @@
 	 * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFFB1);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFFB1);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 100 us
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 376de98..056f455 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -87,37 +87,37 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
 	/*
 	 * UIC1:
 	 *  bit30: ext. Irq 1: PLD : int 32+30
 	 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xfffffffd);
-	mtdcr(uic1tr, 0x00000000);
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xfffffffd);
+	mtdcr(UIC1TR, 0x00000000);
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	/*
 	 * UIC2
 	 *  bit3: ext. Irq 2: DCF77 : int 64+3
 	 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
 	/* select Ethernet pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index b72b716..132531b 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -363,13 +363,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
index acb23da..2a2c434 100644
--- a/board/esd/hub405/hub405.c
+++ b/board/esd/hub405/hub405.c
@@ -86,13 +86,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
index 709bcdd..ab909e5 100644
--- a/board/esd/ocrtc/ocrtc.c
+++ b/board/esd/ocrtc/ocrtc.c
@@ -45,13 +45,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF81);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/*
 	 * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index 04bc569..34a1632 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -155,13 +155,13 @@
 	 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
-	mtdcr(uicer, 0x00000000);        /* disable all ints */
-	mtdcr(uiccr, 0x00000000);        /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF80);        /* set int polarities */
-	mtdcr(uictr, 0x10000000);        /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);       /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);        /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);        /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);        /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);        /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);       /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 
 	/*
 	 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
@@ -271,7 +271,7 @@
 				pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
 			}
 		}
-		mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+		mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 
 		*magic = 0;      /* clear pci reconfig magic again */
 	}
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index a3c1cec..f14ef7a 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -78,13 +78,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest prio */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 5ff87e7..e7415e4 100644
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -48,13 +48,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr(uicer, 0x00000000); /* disable all ints */
-	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
-	mtdcr(uictr, 0x10000000); /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
 	/*
 	 * EBC Configuration Register:
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 419311a..3725ece 100644
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -114,13 +114,13 @@
 	 * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0, INT0 highest prio */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0, INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register:
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 119cbf2..f0f9bff 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -148,29 +148,29 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ef);
-	mtdcr(uic0tr, 0x00000000);
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ef);
+	mtdcr(UIC0TR, 0x00000000);
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffc7f5);
-	mtdcr(uic1tr, 0x00000000);
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffc7f5);
+	mtdcr(UIC1TR, 0x00000000);
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0x27ffffff);
-	mtdcr(uic2tr, 0x00000000);
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0x27ffffff);
+	mtdcr(UIC2TR, 0x00000000);
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
 	/* select Ethernet pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index 7477f56..3f81665 100644
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -88,13 +88,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFFB5);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFFB5);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
index de9c7b9..fb48022 100644
--- a/board/esd/vom405/vom405.c
+++ b/board/esd/vom405/vom405.c
@@ -45,13 +45,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
index e86f1d0..f2591d5 100644
--- a/board/esd/wuh405/wuh405.c
+++ b/board/esd/wuh405/wuh405.c
@@ -64,13 +64,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c
index 0f84127..ce6469d 100644
--- a/board/exbitgen/exbitgen.c
+++ b/board/exbitgen/exbitgen.c
@@ -37,13 +37,13 @@
    |
    +-------------------------------------------------------------------------*/
 
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF90);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF90);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/* Perform reset of PHY connected to PPC via register in CPLD */
 	out8 (PHY_CTRL_ADDR, 0x2e);	/* activate nRESET,FDX,F100,ANEN, enable output */
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index ae258e1..8afffdc 100644
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -38,20 +38,20 @@
 int board_early_init_f (void)
 {
 #if 0 /* test-only */
-	mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-	mtdcr (uicer, 0x00000000);      /* disable all ints */
-	mtdcr (uiccr, 0x00000010);
-	mtdcr (uicpr, 0xFFFF7FF0);      /* set int polarities */
-	mtdcr (uictr, 0x00000010);      /* set int trigger levels */
-	mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);      /* disable all ints */
+	mtdcr (UIC0CR, 0x00000010);
+	mtdcr (UIC0PR, 0xFFFF7FF0);      /* set int polarities */
+	mtdcr (UIC0TR, 0x00000010);      /* set int trigger levels */
+	mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 #else
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFFF0);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFFF0);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 #endif
 
 #if 1 /* test-only */
diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c
index 5246bc8..ff5f183 100644
--- a/board/gdsys/dlvision/dlvision.c
+++ b/board/gdsys/dlvision/dlvision.c
@@ -36,13 +36,13 @@
 
 int board_early_init_f(void)
 {
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr(uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest prio */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index 27c159b..7cc1bf2 100644
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -83,21 +83,21 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	/*
 	 * Setup other serial configuration
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 0de1be8..2cd2e6d 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -44,37 +44,37 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic3sr, 0xffffffff);	/* clear all */
-	mtdcr(uic3er, 0x00000000);	/* disable all */
-	mtdcr(uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic3pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic3tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic3sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
 
 	/*
 	 * Configure PFC (Pin Function Control) registers
diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c
index 628ce3d..a56c2cc 100644
--- a/board/gdsys/neo/neo.c
+++ b/board/gdsys/neo/neo.c
@@ -31,13 +31,13 @@
 
 int board_early_init_f(void)
 {
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr(uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest prio */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
diff --git a/board/jse/jse.c b/board/jse/jse.c
index 6dc9a01..1849ca4 100644
--- a/board/jse/jse.c
+++ b/board/jse/jse.c
@@ -48,12 +48,12 @@
    |       IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
    |       IRQ 31 (EXT IRQ 6) (unused)
    +-------------------------------------------------------------------------*/
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF87);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF87);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/* Configure the interface to the SystemACE MCU port.
 	   The SystemACE is fast, but there is no reason to have
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 3d4d149..40a097c 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -87,29 +87,29 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
 	/*
 	 * Take sim card reader and CF controller out of reset.  Also enable PHY
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index a9c2a6f..f4090f4 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -44,29 +44,29 @@
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
-	mtdcr(uic0er, 0x00000000);  /* disable all */
-	mtdcr(uic0cr, 0x00000000);  /* we have not critical interrupts at the moment */
-	mtdcr(uic0pr, 0xFFBFF1EF);  /* Adjustment of the polarity */
-	mtdcr(uic0tr, 0x00000900);  /* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(uic0sr, 0xffffffff);  /* clear all */
+	mtdcr(UIC0SR, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
+	mtdcr(UIC0ER, 0x00000000);  /* disable all */
+	mtdcr(UIC0CR, 0x00000000);  /* we have not critical interrupts at the moment */
+	mtdcr(UIC0PR, 0xFFBFF1EF);  /* Adjustment of the polarity */
+	mtdcr(UIC0TR, 0x00000900);  /* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(UIC0SR, 0xffffffff);  /* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);  /* clear all */
-	mtdcr(uic1er, 0x00000000);  /* disable all */
-	mtdcr(uic1cr, 0x00000000);  /* all non-critical */
-	mtdcr(uic1pr, 0xFFFFC6A5);  /* Adjustment of the polarity */
-	mtdcr(uic1tr, 0x60000040);  /* per ref-board manual */
-	mtdcr(uic1vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(uic1sr, 0xffffffff);  /* clear all */
+	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
+	mtdcr(UIC1ER, 0x00000000);  /* disable all */
+	mtdcr(UIC1CR, 0x00000000);  /* all non-critical */
+	mtdcr(UIC1PR, 0xFFFFC6A5);  /* Adjustment of the polarity */
+	mtdcr(UIC1TR, 0x60000040);  /* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);  /* clear all */
-	mtdcr(uic2er, 0x00000000);  /* disable all */
-	mtdcr(uic2cr, 0x00000000);  /* all non-critical */
-	mtdcr(uic2pr, 0x27C00000);  /* Adjustment of the polarity */
-	mtdcr(uic2tr, 0x3C000000);  /* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(uic2sr, 0xffffffff);  /* clear all */
+	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
+	mtdcr(UIC2ER, 0x00000000);  /* disable all */
+	mtdcr(UIC2CR, 0x00000000);  /* all non-critical */
+	mtdcr(UIC2PR, 0x27C00000);  /* Adjustment of the polarity */
+	mtdcr(UIC2TR, 0x3C000000);  /* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
 
 	/* Trace Pins are disabled. SDR0_PFC0 Register */
 	mtsdr(SDR0_PFC0, 0x0);
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index d8279e8..b87df01 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -489,13 +489,13 @@
    |       caused the interrupt.
    |
    +-------------------------------------------------------------------------*/
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
-	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	return 0;
 }
 
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index e00d1d0..c2d6c6f 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -552,13 +552,13 @@
    |       caused the interrupt.
    |
    +-------------------------------------------------------------------------*/
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
-	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
index 40bec8e..ba3e9c3 100644
--- a/board/netstal/hcu4/hcu4.c
+++ b/board/netstal/hcu4/hcu4.c
@@ -58,12 +58,12 @@
 	 *      IRQ 17-24 RESERVED/UNUSED
 	 *      IRQ 31 (EXT IRQ 6) (unused)
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr(uicer, 0x00000000); /* disable all ints */
-	mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
-	mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
-	mtdcr(uictr, 0x00000000); /* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+	mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
 	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
 	mtdcr(CPC0_ECR, 0x60606000);
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 836c034..4522612 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -129,29 +129,29 @@
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 	mtsdr(SDR0_PFC0, 0x00003E00);	/* Pin function:  */
 	mtsdr(SDR0_PFC1, 0x00848000);	/* Pin function: UART0 has 4 pins */
 
diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c
index 9054282..945d79a 100644
--- a/board/netstal/mcu25/mcu25.c
+++ b/board/netstal/mcu25/mcu25.c
@@ -64,12 +64,12 @@
 	 *      IRQ 17-24 RESERVED/UNUSED
 	 *      IRQ 31 (EXT IRQ 6) (unused)
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr(uicer, 0x00000000); /* disable all ints */
-	mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
-	mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
-	mtdcr(uictr, 0x00000000); /* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+	mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
 	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
 	mtdcr(CPC0_ECR, 0x60606000);
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index f966d02..ac059a9 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -155,21 +155,21 @@
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000001);	/* UIC1 crit is critical */
-	mtdcr(uic0pr, 0xfffffe1f);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(UIC0PR, 0xfffffe1f);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	/*--------------------------------------------------------------------
 	 * Setup other serial configuration
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index be79b42..cdb91ac 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -60,36 +60,36 @@
 	 * UIC2		UIC1
 	 * UIC3		UIC2
 	 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
-	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic1pr, 0xfffffe03);	/* per manual */
-	mtdcr (uic1tr, 0x01c00000);	/* per manual */
-	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (UIC1PR, 0xfffffe03);	/* per manual */
+	mtdcr (UIC1TR, 0x01c00000);	/* per manual */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
-	mtdcr (uic2er, 0x00000000);	/* disable all */
-	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
-	mtdcr (uic3er, 0x00000000);	/* disable all */
-	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
-	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic0sr, 0xfc000000); /* clear all */
-	mtdcr (uic0er, 0x00000000); /* disable all */
-	mtdcr (uic0cr, 0x00000000); /* all non-critical */
-	mtdcr (uic0pr, 0xfc000000); /* */
-	mtdcr (uic0tr, 0x00000000); /* */
-	mtdcr (uic0vr, 0x00000001); /* */
+	mtdcr (UIC0SR, 0xfc000000); /* clear all */
+	mtdcr (UIC0ER, 0x00000000); /* disable all */
+	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000); /* */
+	mtdcr (UIC0TR, 0x00000000); /* */
+	mtdcr (UIC0VR, 0x00000001); /* */
 
 	/* Setup shutdown/SSD empty interrupt as inputs */
 	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 18054e4..20fd4dc 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -101,21 +101,21 @@
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000001);	/* UIC1 crit is critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	return 0;
 }
diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c
index ffc47de..f878c49 100644
--- a/board/quad100hd/quad100hd.c
+++ b/board/quad100hd/quad100hd.c
@@ -40,13 +40,13 @@
 int board_early_init_f(void)
 {
 	/* taken from PPCBoot */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);
-	mtdcr(uicpr, 0xFFFF7FFE);	/* set int polarities */
-	mtdcr(uictr, 0x00000000);	/* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7FFE);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
 
 	mtdcr(CPC0_SRR, 0x00040000);   /* Hold PCI bridge in reset */
 
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index b80c206..92b15aa 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -212,36 +212,36 @@
 	 * UIC2		UIC1
 	 * UIC3		UIC2
 	 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
-	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non- critical */
-	mtdcr (uic1pr, 0xfffffe03);	/* polarity */
-	mtdcr (uic1tr, 0x01c00000);	/* trigger edge vs level */
-	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000000);	/* all non- critical */
+	mtdcr (UIC1PR, 0xfffffe03);	/* polarity */
+	mtdcr (UIC1TR, 0x01c00000);	/* trigger edge vs level */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
-	mtdcr (uic2er, 0x00000000);	/* disable all */
-	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffc8ff);	/* polarity */
-	mtdcr (uic2tr, 0x00ff0000);	/* trigger edge vs level */
-	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffc8ff);	/* polarity */
+	mtdcr (UIC2TR, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
-	mtdcr (uic3er, 0x00000000);	/* disable all */
-	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic3pr, 0xffff83ff);	/* polarity */
-	mtdcr (uic3tr, 0x00ff8c0f);	/* trigger edge vs level */
-	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffff83ff);	/* polarity */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic0sr, 0xfc000000);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic0pr, 0xfc000000);
-	mtdcr (uic0tr, 0x00000000);
-	mtdcr (uic0vr, 0x00000001);
+	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all */
+	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000);
+	mtdcr (UIC0TR, 0x00000000);
+	mtdcr (UIC0VR, 0x00000001);
 
 	fpga_init();
 
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index ad3f9bc..0c8e6df 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -202,36 +202,36 @@
 	 * UIC2		UIC1
 	 * UIC3		UIC2
 	 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
-	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non- critical */
-	mtdcr (uic1pr, 0xfffffe03);	/* polarity */
-	mtdcr (uic1tr, 0x01c00000);	/* trigger edge vs level */
-	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC1ER, 0x00000000);	/* disable all */
+	mtdcr (UIC1CR, 0x00000000);	/* all non- critical */
+	mtdcr (UIC1PR, 0xfffffe03);	/* polarity */
+	mtdcr (UIC1TR, 0x01c00000);	/* trigger edge vs level */
+	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
-	mtdcr (uic2er, 0x00000000);	/* disable all */
-	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffc8ff);	/* polarity */
-	mtdcr (uic2tr, 0x00ff0000);	/* trigger edge vs level */
-	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC2ER, 0x00000000);	/* disable all */
+	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC2PR, 0xffffc8ff);	/* polarity */
+	mtdcr (UIC2TR, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
-	mtdcr (uic3er, 0x00000000);	/* disable all */
-	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic3pr, 0xffff83ff);	/* polarity */
-	mtdcr (uic3tr, 0x00ff8c0f);	/* trigger edge vs level */
-	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr (UIC3ER, 0x00000000);	/* disable all */
+	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC3PR, 0xffff83ff);	/* polarity */
+	mtdcr (UIC3TR, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
 
-	mtdcr (uic0sr, 0xfc000000);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic0pr, 0xfc000000);
-	mtdcr (uic0tr, 0x00000000);
-	mtdcr (uic0vr, 0x00000001);
+	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all */
+	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr (UIC0PR, 0xfc000000);
+	mtdcr (UIC0TR, 0x00000000);
+	mtdcr (UIC0VR, 0x00000001);
 
 	fpga_init();
 
diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c
index 66842ea..74e6204 100644
--- a/board/sbc405/sbc405.c
+++ b/board/sbc405/sbc405.c
@@ -41,13 +41,13 @@
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index 5ae7b12..e7772c5 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -294,22 +294,22 @@
 
 	writeb (cpldConfig_1, CPLD_CONTROL_1);	/* disable everything in CPLD */
 
-	mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
-	mtdcr (uicer, 0x00000000);    /* disable all ints */
-	mtdcr (uiccr, 0x00000000);    /* set all to be non-critical */
+	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);    /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);    /* set all to be non-critical */
 
 	if (IS_CAMERON) {
 		sc3_cameron_init();
 		mtdcr (0x0B6, 0x18000000);
-		mtdcr (uicpr, 0xFFFFFFF0);
-		mtdcr (uictr, 0x10001030);
+		mtdcr (UIC0PR, 0xFFFFFFF0);
+		mtdcr (UIC0TR, 0x10001030);
 	} else {
 		mtdcr (0x0B6, 0x0000000);
-		mtdcr (uicpr, 0xFFFFFFE0);
-		mtdcr (uictr, 0x10000020);
+		mtdcr (UIC0PR, 0xFFFFFFE0);
+		mtdcr (UIC0TR, 0x10000020);
 	}
-	mtdcr (uicvcr, 0x00000001);   /* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
+	mtdcr (UIC0VCR, 0x00000001);   /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
 
 	/* setup other implementation specific details */
 	mtdcr (CPC0_ECR, 0x60606000);
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
index 6479bee..00a9f98 100644
--- a/board/w7o/w7o.c
+++ b/board/w7o/w7o.c
@@ -64,16 +64,16 @@
 	 * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
 
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,
 					   INT0 highest priority */
 
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 #elif defined(CONFIG_W7OLMC)
 	/*
@@ -95,16 +95,16 @@
 	 * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
 	 */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
 
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,
 					   INT0 highest priority */
 
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 #else  /* Unknown */
 #    error "Unknown W7O board configuration"
diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
index 58041fc..011fb94 100644
--- a/board/xes/xpedite1000/xpedite1000.c
+++ b/board/xes/xpedite1000/xpedite1000.c
@@ -74,36 +74,36 @@
 	 * UIC2		UIC1
 	 * UIC3		UIC2
 	 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000003);	/* SMI & UIC1 crit are critical */
-	mtdcr(uic1pr, 0xfffffe00);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x01c00000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr(UIC1PR, 0xfffffe00);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x01c00000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffc0ff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00ff8000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00ff8000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic3sr, 0xffffffff);	/* clear all */
-	mtdcr(uic3er, 0x00000000);	/* disable all */
-	mtdcr(uic3cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic3pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic3tr, 0x00ff8c0f);	/* per ref-board manual */
-	mtdcr(uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic3sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
 
-	mtdcr(uic0sr, 0xfc000000);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic0pr, 0xfc000000);	/* */
-	mtdcr(uic0tr, 0x00000000);	/* */
-	mtdcr(uic0vr, 0x00000001);	/* */
+	mtdcr(UIC0SR, 0xfc000000);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC0PR, 0xfc000000);	/* */
+	mtdcr(UIC0TR, 0x00000000);	/* */
+	mtdcr(UIC0VR, 0x00000001);	/* */
 
 	LED0_ON();
 
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index fc9dfa0..01273a1 100644
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -50,13 +50,13 @@
 
 int board_early_init_f(void)
 {
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);
-	mtdcr(uicpr, 0xFFFF7F00);	/* set int polarities */
-	mtdcr(uictr, 0x00000000);	/* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7F00);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
 
 	/*
 	 * Configure CPC0_PCI to enable PerWE as output