arm64: zynqmp: versal: Consistently use enum tcm_mode
Turn anonymous enum TCM_LOCK/TCM_SPLIT into enum tcm_mode {}, set
TCM_LOCK as 0 and TCM_SPLIT as 1 to match LOCK and SPLIT macros in
mach-zynqmp/mp.c, and unify all the functions and their parameters
on this one single enum tcm_mode {} instead of a mix of bool and u8.
No functional change intended.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20250206213039.42756-1-marex@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 921ca49..7423b8d 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -24,7 +24,7 @@
#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
-static void set_r5_halt_mode(u8 halt, u8 mode)
+static void set_r5_halt_mode(u8 halt, enum tcm_mode mode)
{
u32 tmp;
@@ -45,7 +45,7 @@
}
}
-static void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(enum tcm_mode mode)
{
u32 tmp;
@@ -63,7 +63,7 @@
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
-static void release_r5_reset(u8 mode)
+static void release_r5_reset(enum tcm_mode mode)
{
u32 tmp;
@@ -87,9 +87,9 @@
writel(tmp, &crlapb_base->cpu_r5_ctrl);
}
-void initialize_tcm(bool mode)
+void initialize_tcm(enum tcm_mode mode)
{
- if (!mode) {
+ if (mode == TCM_LOCK) {
set_r5_tcm_mode(TCM_LOCK);
set_r5_halt_mode(HALT, TCM_LOCK);
enable_clock_r5();
@@ -102,7 +102,7 @@
}
}
-void tcm_init(u8 mode)
+void tcm_init(enum tcm_mode mode)
{
puts("WARNING: Initializing TCM overwrites TCM content\n");
initialize_tcm(mode);