net: mscc: refactor mscc_miim
Because all MSCC SoC use the same MDIO bus, put the implementation in
one common file(mscc_miim) and make all the other MSCC network drivers to
use these functions.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c
index 995c623..d20ec49 100644
--- a/drivers/net/mscc_eswitch/servalt_switch.c
+++ b/drivers/net/mscc_eswitch/servalt_switch.c
@@ -16,18 +16,7 @@
#include <wait_bit.h>
#include "mscc_xfer.h"
-
-#define GCB_MIIM_MII_STATUS 0x0
-#define GCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#define GCB_MIIM_MII_CMD_VLD BIT(31)
-#define GCB_MIIM_DATA 0xC
-#define GCB_MIIM_DATA_ERROR (0x3 << 16)
+#include "mscc_miim.h"
#define PHY_CFG 0x0
#define PHY_CFG_ENA 0x3
@@ -134,13 +123,6 @@
struct servalt_phy_port_t ports[MAX_PORT];
};
-struct mscc_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static const unsigned long servalt_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x8,
[MSCC_QS_XTR_FLUSH] = 0x18,
@@ -152,85 +134,6 @@
static struct mscc_miim_dev miim[SERVALT_MIIM_BUS_COUNT];
static int miim_count = -1;
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
- return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
- GCB_MIIM_STAT_BUSY, false, 250, false);
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
-out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
- GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
-
-out:
- return ret;
-}
-
-static struct mii_dev *servalt_mdiobus_init(phys_addr_t miim_base,
- unsigned long miim_size)
-{
- struct mii_dev *bus;
-
- bus = mdio_alloc();
- if (!bus)
- return NULL;
-
- ++miim_count;
- sprintf(bus->name, "miim-bus%d", miim_count);
-
- miim[miim_count].regs = ioremap(miim_base, miim_size);
- miim[miim_count].miim_base = miim_base;
- miim[miim_count].miim_size = miim_size;
- bus->priv = &miim[miim_count];
- bus->read = mscc_miim_read;
- bus->write = mscc_miim_write;
-
- if (mdio_register(bus))
- return NULL;
-
- miim[miim_count].bus = bus;
- return bus;
-}
-
static void mscc_phy_reset(void)
{
writel(0, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG);
@@ -564,7 +467,8 @@
/* If the bus is new then create a new bus */
if (!get_mdiobus(addr_base, addr_size))
priv->bus[miim_count] =
- servalt_mdiobus_init(addr_base, addr_size);
+ mscc_mdiobus_init(miim, &miim_count, addr_base,
+ addr_size);
/* Connect mdio bus with the port */
bus = get_mdiobus(addr_base, addr_size);