diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 0c1bdc7..95930ad 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -44,7 +44,7 @@
 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
+#if defined(CONFIG_M68K)
 	unsigned long	bi_mbar_base;	/* base of internal registers */
 #endif
 #if defined(CONFIG_MPC83xx)
@@ -62,10 +62,7 @@
 	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
 	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
 #endif
-#if defined(CONFIG_MPC512X)
-	unsigned long	bi_ipsfreq;	/* IPS Bus Freq, in MHz */
-#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
+#if defined(CONFIG_M68K)
 	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
 	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
 #endif
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
deleted file mode 100644
index 2ba6b08..0000000
--- a/include/configs/TQM5200.h
+++ /dev/null
@@ -1,623 +0,0 @@
-/*
- * (C) Copyright 2003-2014
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU		*/
-#define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
-#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000	boot low (standard configuration with room for
- *		max 64 MByte Flash ROM)
- * 0xFFF00000	boot high (for a backup copy of U-Boot)
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFC000000
-#endif
-
-/* On a Cameron or on a FO300 board or ...				*/
-#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
-	&& !defined(CONFIG_FO300)
-#define CONFIG_STK52XX		1	/* ... on a STK52XX board		*/
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_BOOTCOUNT_LIMIT	1
-
-#ifdef CONFIG_FO300
-#define CONFIG_SYS_DEVICE_NULLDEV		1	/* enable null device */
-#define CONFIG_USB_BIN_FIXUP		1	/* for a buggy USB device */
-#if 0
-#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED	1	/* silent console on PSC1 when S1 */
-							/* switch is closed */
-#endif
-
-#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED		/* silent console on PSC1 when S1 */
-							/* switch is open */
-#endif	/* CONFIG_FO300 */
-
-#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
-#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
-#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
-#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
-#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
-#define CONFIG_BOARD_EARLY_INIT_R
-#endif /* CONFIG_STK52XX */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
-/* #define CONFIG_PCI_SCAN_SHOW	1 */
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_EEPRO100		1
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#define CONFIG_NS8382X		1
-#endif	/* CONFIG_STK52XX */
-
-/*
- * Video console
- */
-#ifndef CONFIG_TQM5200S		/* No graphics controller on TQM5200S */
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_LOGO
-
-#ifndef CONFIG_FO300
-#else
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#define CONFIG_SPLASH_SCREEN
-#endif /* #ifndef CONFIG_TQM5200S */
-
-/* Partitions */
-
-/* USB */
-#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
-    defined(CONFIG_STK52XX)
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-#endif
-
-#ifndef CONFIG_CAM5200
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
-				 CONFIG_SYS_POST_CPU)
-#endif
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-#endif
-
-#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
-	defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
-#endif
-
-#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
-	defined(CONFIG_STK52XX)
-    #define CONFIG_CFG_USB
-    #define CONFIG_CFG_FAT
-#endif
-
-#define	CONFIG_TIMESTAMP		/* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
-#   define CONFIG_SYS_LOWBOOT		1	/* Boot low */
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
-# define ENV_UPDT							\
-	"update=protect off FFF00000 +${filesize};"			\
-		"erase FFF00000 +${filesize};"				\
-		"cp.b 200000 FFF00000 ${filesize};"			\
-		"protect on FFF00000 +${filesize}\0"
-#else	/* default lowboot configuration */
-#   define ENV_UPDT							\
-	"update=protect off FC000000 +${filesize};"			\
-		"erase FC000000 +${filesize};"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 +${filesize}\0"
-#endif
-
-#if defined(CONFIG_TQM5200)
-#define CUSTOM_ENV_SETTINGS						\
-	"hostname=tqm5200\0"						\
-	"bootfile=/tftpboot/tqm5200/uImage\0"				\
-	"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0"			\
-	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
-#elif defined(CONFIG_CAM5200)
-#define CUSTOM_ENV_SETTINGS						\
-	"bootfile=cam5200/uImage\0"					\
-	"u-boot=cam5200/u-boot.bin\0"					\
-	"setup=tftp 200000 cam5200/setup.img; source 200000\0"
-#endif
-
-#if defined(CONFIG_TQM5200_B)
-#define ENV_FLASH_LAYOUT						\
-	"fdt_addr=FC100000\0"						\
-	"kernel_addr=FC140000\0"					\
-	"ramdisk_addr=FC600000\0"
-#elif defined(CONFIG_CHARON)
-#define ENV_FLASH_LAYOUT						\
-	"fdt_addr=FDFC0000\0"						\
-	"kernel_addr=FC0A0000\0"					\
-	"ramdisk_addr=FC200000\0"
-#else	/* !CONFIG_TQM5200_B */
-#define ENV_FLASH_LAYOUT						\
-	"fdt_addr=FC0A0000\0"						\
-	"kernel_addr=FC0C0000\0"					\
-	"ramdisk_addr=FC300000\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"console=ttyPSC0\0"						\
-	ENV_FLASH_LAYOUT						\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=600000\0"						\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=${console},${baudrate}\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"flash_self_old=sete console ttyS0; "				\
-		"run ramargs addip addcons addmtd; "			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_self=run ramargs addip addcons;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;"	\
-		"bootm ${kernel_addr}\0"				\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
-		"sete console ttyS0; run nfsargs addip addcons;bootm\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addcons addmtd; "			\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	CUSTOM_ENV_SETTINGS						\
-	"load=tftp 200000 ${u-boot}\0"					\
-	ENV_UPDT							\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
- * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-
-#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks
-					   (= chip selects) */
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned int /* main flash device with */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0		0x555
-#define CONFIG_SYS_FLASH_ADDR1		0x2AA
-#define CONFIG_SYS_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-#else
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_FLASH_CFI_MTD		/* with MTD support */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-
-#if defined (CONFIG_CAM5200)
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-#elif defined(CONFIG_TQM5200_B)
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00080000)
-#else
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define MTDIDS_DEFAULT		"nor0=fc000000.flash"
-
-#if defined(CONFIG_STK52XX)
-# if defined(CONFIG_TQM5200_B)
-#  if defined(CONFIG_SYS_LOWBOOT)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:1m(firmware),"	\
-						"256k(dtb),"		\
-						"2304k(kernel),"	\
-						"2560k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
-#  else	/* highboot */
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:2560k(kernel),"\
-						"3584k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"15m(big-fs),"		\
-						"1m(firmware)"
-#  endif /* CONFIG_SYS_LOWBOOT */
-# else	/* !CONFIG_TQM5200_B */
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
-						"128k(dtb),"		\
-						"2304k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"8m(misc),"		\
-						"15m(big-fs)"
-# endif /* CONFIG_TQM5200_B */
-#elif defined (CONFIG_CAM5200)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:768k(firmware),"\
-						"1792k(kernel),"	\
-						"5632k(rootfs),"	\
-						"24m(home)"
-#elif defined (CONFIG_CHARON)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
-						"1408k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"24320k(big-fs),"	\
-						"256k(dts)"
-#elif defined (CONFIG_FO300)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
-						"1408k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
-#else
-# error "Unknown Carrier Board"
-#endif	/* CONFIG_STK52XX */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x4000	/* 16 k - keep small for fast booting */
-#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#else
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#endif /* CONFIG_TQM5200_B */
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#if defined (CONFIG_CAM5200)
-# define CONFIG_SYS_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#elif defined(CONFIG_TQM5200_B)
-# define CONFIG_SYS_MONITOR_LEN	(512 << 10)	/* Reserve 512 kB for Monitor	*/
-#else
-# define CONFIG_SYS_MONITOR_LEN	(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#endif
-
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- *
- * use CS1: Bit 0 (mask: 0x80000000):
- *	   1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	  00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- *		SPI on PSC3 according to PSC3 setting. Use for CAM5200.
- *	  01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- *		Use for REV200 STK52XX boards and FO300 boards. Do not use
- *		with REV100 modules (because, there I2C1 is used as I2C bus).
- * use ATA: Bits 6-7 (mask 0x03000000):
- *	  00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
- *		Use for CAM5200 board.
- *	  01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
- * use PSC6: Bits 9-11 (mask 0x00700000):
- *	 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
- *		UART, CODEC or IrDA.
- *		GPIO on PSC6_3 is used in post_hotkeys_pressed() to
- *		enable extended POST tests.
- *		Use for MINI-FAP and TQM5200_IB boards.
- *	 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
- *		Extended POST test is not available.
- *		Use for STK52xx, FO300 and CAM5200 boards.
- *		WARNING: When the extended POST is enabled, these bits will
- *			 be overridden by this code as GPIOs!
- * use PCI_DIS: Bit 16 (mask 0x00008000):
- *	   1 -> disable PCI controller (on CAM5200 board).
- * use USB: Bits 18-19 (mask 0x00003000):
- *	  10 -> two UARTs (on FO300 and CAM5200).
- * use PSC3: Bits 20-23 (mask: 0x00000f00):
- *	0000 -> All PSC3 pins are GPIOs.
- *	1100 -> UART/SPI (on FO300 board).
- *	0100 -> UART (on CAM5200 board).
- * use PSC2: Bits 25:27 (mask: 0x00000030):
- *	 000 -> All PSC2 pins are GPIOs.
- *	 100 -> UART (on CAM5200 board).
- *	 001 -> CAN1/2 on PSC2 pins.
- *		Use for REV100 STK52xx boards
- *	 01x -> Use AC97 (on FO300 board).
- * use PSC1: Bits 29-31 (mask: 0x00000007):
- *	 100 -> UART (on all boards).
- */
-#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
-#if defined (CONFIG_MINIFAP)
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x91000004
-#elif defined (CONFIG_STK52XX)
-# if defined (CONFIG_STK52XX_REV100)
-#  define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
-# else /* STK52xx REV200 and above */
-#  if defined (CONFIG_TQM5200_REV100)
-#   error TQM5200 REV100 not supported on STK52XX REV200 or above
-#  else/* TQM5200 REV200 and above */
-#   define CONFIG_SYS_GPS_PORT_CONFIG	0x91500404
-#  endif
-# endif
-#elif defined (CONFIG_FO300)
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x91502c24
-#elif defined (CONFIG_CAM5200)
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x8050A444
-#else  /* TMQ5200 Inbetriebnahme-Board */
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x81000004
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START		0xE5000000
-#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
-#define CONFIG_SYS_CS2_CFG		0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE		0xE0000000
-#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
-#define CONFIG_SYS_CS1_CFG		0x8F48FF70
-#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
-
-#if defined(CONFIG_CAM5200)
-#define CONFIG_SYS_CS4_START		0xB0000000
-#define CONFIG_SYS_CS4_SIZE		0x00010000
-#define CONFIG_SYS_CS4_CFG		0x01019C10
-
-#define CONFIG_SYS_CS5_START		0xD0000000
-#define CONFIG_SYS_CS5_SIZE		0x01208000
-#define CONFIG_SYS_CS5_CFG		0x1414BF10
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE		4
-
-/* Support ATAPI devices */
-#define CONFIG_ATAPI			1
-
-/*-----------------------------------------------------------------------
- * Open firmware flat tree support
- *-----------------------------------------------------------------------
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
deleted file mode 100644
index 82b9ff4..0000000
--- a/include/configs/a3m071.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * Copyright 2012-2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_A3M071			/* A3M071 board */
-
-#define	CONFIG_SYS_TEXT_BASE	0x01000000	/* boot low for 32 MiB boards */
-
-#define CONFIG_SPL_TARGET	"u-boot-img.bin"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SYS_LOWBOOT		/* Enable lowboot	*/
-
-#ifdef CONFIG_A4M2K
-#define CONFIG_HOSTNAME		a4m2k
-#else
-#define CONFIG_HOSTNAME		a3m071
-#endif
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	    /* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE		\
-	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_BOOTP_MAY_FAIL
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_NET_RETRY_COUNT 3
-#define CONFIG_NETCONSOLE
-#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS	/* needed for UBI */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT          "nor0=fc000000.flash"
-#define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:512k(u-boot),"	\
-						"128k(env1),"	\
-						"128k(env2),"	\
-						"128k(hwinfo),"	\
-						"1M(nvramsim),"	\
-						"128k(dtb),"	\
-						"5M(kernel),"	\
-						"128k(sysinfo),"	\
-						"7552k(root),"	\
-						"4M(app),"	\
-						"5376k(data),"	\
-						"8M(install)"
-
-#define CONFIG_LZO			/* needed for UBI */
-#define CONFIG_RBTREE			/* needed for UBI */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBIFS
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-/* define for 66MHz speed - undef for 33MHz PCI clock speed */
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#else
-#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#endif
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE	8192
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x80000)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_FLASH_VERIFY
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR			0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#ifdef CONFIG_A4M2K
-#define CONFIG_PHY_ADDR			0x01
-#else
-#define CONFIG_PHY_ADDR			0x00
-#endif
-
-/*
- * GPIO configuration
- */
-
-/*
- * GPIO-config depends on failsave-level
- * failsave 0 means just MPX-config, no digiboard, no fpga
- *          1 means digiboard ok
- *          2 means fpga ok
- */
-
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C805
-#else
-/* for failsave-level 0 - full failsave */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C005
-/* for failsave-level 1 - only digiboard ok */
-#define CONFIG_SYS_GPS_PORT_CONFIG_1	0x1005C065
-/* for failsave-level 2 - all ok */
-#define CONFIG_SYS_GPS_PORT_CONFIG_2	0x1005C065
-#endif
-
-#define CONFIG_WDOG_GPIO_PIN		GPIO_WKUP_7
-#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_HW_WATCHDOG		/* Use external HW-Watchdog	*/
-#endif
-
-/*
- * Configuration matrix
- *                        MSB                            LSB
- * failsave 0  0x1005C005  00010000000001011100000000000101  ( full failsave )
- * failsave 1  0x1005C065  00010000000001011100000001100101  ( digib.-ver ok )
- * failsave 2  0x1005C065  00010000000001011100000001100101  ( all ok )
- *                         || ||| ||  |   ||| |   |   |   |
- *                         || ||| ||  |   ||| |   |   |   |  bit rev name
- *                         ++-+++-++--+---+++-+---+---+---+-  0   31 CS1
- *                          +-+++-++--+---+++-+---+---+---+-  1   30 LPTZ
- *                            ||| ||  |   ||| |   |   |   |   2   29 ALTs
- *                            +++-++--+---+++-+---+---+---+-  3   28 ALTs
- *                             ++-++--+---+++-+---+---+---+-  4   27 CS7
- *                              +-++--+---+++-+---+---+---+-  5   26 CS6
- *                                ||  |   ||| |   |   |   |   6   25 ATA
- *                                ++--+---+++-+---+---+---+-  7   24 ATA
- *                                 +--+---+++-+---+---+---+-  8   23 IR_USB_CLK
- *                                    |   ||| |   |   |   |   9   22 IRDA
- *                                    |   ||| |   |   |   |  10   21 IRDA
- *                                    +---+++-+---+---+---+- 11   20 IRDA
- *                                        ||| |   |   |   |  12   19 Ether
- *                                        ||| |   |   |   |  13   18 Ether
- *                                        ||| |   |   |   |  14   17 Ether
- *                                        +++-+---+---+---+- 15   16 Ether
- *                                         ++-+---+---+---+- 16   15 PCI_DIS
- *                                          +-+---+---+---+- 17   14 USB_SE
- *                                            |   |   |   |  18   13 USB
- *                                            +---+---+---+- 19   12 USB
- *                                                |   |   |  20   11 PSC3
- *                                                |   |   |  21   10 PSC3
- *                                                |   |   |  22    9 PSC3
- *                                                +---+---+- 23    8 PSC3
- *                                                    |   |  24    7 -
- *                                                    |   |  25    6 PSC2
- *                                                    |   |  26    5 PSC2
- *                                                    +---+- 27    4 PSC2
- *                                                        |  28    3 -
- *                                                        |  29    2 PSC1
- *                                                        |  30    1 PSC1
- *                                                        +- 31    0 PSC1
- */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_CMDLINE_EDITING
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000
-#define CONFIG_SYS_MEMTEST_END		0x00f00000
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#ifdef CONFIG_A4M2K
-/* external MRAM */
-#define CONFIG_SYS_CS1_START		0xf1000000
-#define CONFIG_SYS_CS1_SIZE		(512 << 10)	/* 512KiB MRAM */
-#endif
-
-#define CONFIG_SYS_CS2_START		0xe0000000
-#define CONFIG_SYS_CS2_SIZE		0x00100000
-
-/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
-#define CONFIG_SYS_CS3_START		0xE9000000
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_CS3_SIZE		0x00100000
-#else
-#define CONFIG_SYS_CS3_SIZE		0x00080000
-#endif
-/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
-#define CONFIG_SYS_CS3_CFG		0x0032B900
-
-#ifndef CONFIG_A4M2K
-/* Diagnosis Interface - see ticket #63 */
-#define CONFIG_SYS_CS4_START		0xEA000000
-#define CONFIG_SYS_CS4_SIZE		0x00000001
-/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0002B900 */
-#define CONFIG_SYS_CS4_CFG		0x0002B900
-#endif
-
-/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
-#define CONFIG_SYS_CS5_START		0xE8000000
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_CS5_SIZE		0x00100000
-#else
-#define CONFIG_SYS_CS5_SIZE		0x00010000
-#endif
-/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
-#define CONFIG_SYS_CS5_CFG		0x0032B900
-
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for pci_clk  = 66 MHz */
-#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
-#define CONFIG_SYS_CS1_CFG		0x0008FD00
-#define CONFIG_SYS_CS2_CFG		0x0006F90C
-#else	/* for pci_clk = 33 MHz */
-#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
-#define CONFIG_SYS_CS1_CFG		0x0001FB00
-#define CONFIG_SYS_CS2_CFG		0x0002F90C
-#endif
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
-/* R  7  R  6  R  5  R  4  R  3  R  2  R  1  R  0  */
-/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
-#define CONFIG_SYS_CS_DEADCYCLE		0x33030000
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*
- * Environment Configuration
- */
-
-#undef  CONFIG_BOOTARGS
-
-#define CONFIG_SYS_AUTOLOAD	"n"
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
-	"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_SYS_FDT_BASE	0xfc1e0000
-#define CONFIG_SYS_FDT_SIZE	(16<<10)
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"verify=no\0"							\
-	"loadaddr=200000\0"						\
-	"kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0"		\
-	"kernel_addr_r=1000000\0"					\
-	"fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0"		\
-	"fdt_addr_r=1800000\0"						\
-	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
-	"fdtfile=" __stringify(CONFIG_HOSTNAME) "/"			\
-		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
-	"rootpath=/opt/eldk-5.2.1/powerpc/"				\
-		"core-image-minimal-mtdutils-dropbear-generic\0"	\
-	"consoledev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"mtdargs=setenv bootargs root=/dev/mtdblock8 "			\
-		"rootfstype=squashfs,jffs2\0"				\
-	"addhost=setenv bootargs ${bootargs} "				\
-		"hostname=${hostname}\0"				\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consoledev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_mtd=run mtdargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME)		\
-		"/u-boot-img.bin\0"					\
-	"update=protect off fc000000 fc07ffff;"				\
-		"era fc000000 fc07ffff;"				\
-		"cp.b ${loadaddr} fc000000 ${filesize}\0"		\
-	"upd=run load;run update\0"					\
-	"upd_fdt=tftp 1800000 a3m071/a3m071.dtb;"			\
-		"run mtdargs addip addtty addmtd addhost;"		\
-		"fdt addr 1800000;fdt boardsetup;fdt chosen;"		\
-		"erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000"	\
-	"upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;"		\
-		"erase fc200000 fc6fffff;"				\
-		"cp.b 1000000 fc200000 ${filesize}"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"mtdids=" MTDIDS_DEFAULT "\0"					\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_mtd"
-
-/*
- * SPL related defines
- */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE	0xfc000000
-
-/* Place BSS for SPL near end of SDRAM */
-#define CONFIG_SPL_BSS_START_ADDR	((128 - 1) << 20)
-#define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)
-
-/* Place patched DT blob (fdt) at this address */
-#define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000
-
-/* Settings for real U-Boot to be loaded from NOR flash */
-#ifndef __ASSEMBLY__
-extern char __spl_flash_end[];
-#endif
-#define CONFIG_SYS_UBOOT_BASE		__spl_flash_end
-#define CONFIG_SYS_SPL_MAX_LEN		(32 << 10)
-#define CONFIG_SYS_UBOOT_START		0x1000100
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
deleted file mode 100644
index 5ab063e..0000000
--- a/include/configs/a4m072.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_A4M072		1	/* ... on A4M072 board */
-#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
-
-#define CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-/* define to enable silent console */
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-#endif
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-#undef CONFIG_EEPRO100
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
-#define CONFIG_SYS_LOWBOOT		1
-#define CONFIG_SYS_LOWBOOT32		1
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_SYS_AUTOLOAD	"n"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_PREBOOT				"run try_update"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0"		\
-	"cf1=diskboot 200000 0:1\0"					\
-	"bootcmd_cf1=run bcf1\0"					\
-	"bcf=setenv bootargs root=/dev/hda3\0"				\
-	"bootcmd_nfs=run bnfs\0"					\
-	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
-		"panic=1\0"						\
-	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"		\
-			"run norargs addip; run bk\0"			\
-	"bnfs=nfs 200000 ${rootpath}/boot/uImage;"			\
-			"run nfsargs addip ; run bk\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-				"nfsroot=${serverip}:${rootpath}\0"	\
-	"try_update=usb start;sleep 2;usb start;sleep 1;"		\
-			"fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"	\
-			"source 2F0000\0"				\
-	"env_addr=FE060000\0"						\
-	"kernel_addr=FE100000\0"					\
-	"rootfs_addr=FE200000\0"					\
-	"add_mtd=setenv bootargs ${bootargs} mtdparts="			\
-		"phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"	\
-	"bcf1=run cf1; run bcf; run addip; run bk\0"			\
-	"add_consolespec=setenv bootargs ${bootargs} "			\
-				"console=/dev/null quiet\0"		\
-	"addip=if test -n ${ethaddr};"					\
-		"then if test -n ${ipaddr};"				\
-			"then setenv bootargs ${bootargs} "		\
-				"ip=${ipaddr}:${serverip}:${gatewayip}:"\
-				"${netmask}:${hostname}:${netdev}:off;"	\
-			"fi;"						\
-		"else;"							\
-			"setenv bootargs ${bootargs} no_ethaddr;"	\
-		"fi\0"							\
-	"hostname=CPUP0\0"						\
-	"netdev=eth0\0"							\
-	"bootcmd=run bootcmd_nor\0" 					\
-	""
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#error "CONFIG_SYS_LOWBOOT not defined?"
-#else	/* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_SYS_LOWBOOT32)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif
-#endif	/* CONFIG_SYS_LOWBOOT */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS0_START}
-#define CONFIG_SYS_FLASH_BANKS_SIZES	{CONFIG_SYS_CS0_SIZE}
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x1f
-#define CONFIG_PHY_TYPE		0x79c874		/* AMD Phy Controller */
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x18000004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-/* Flash at CSBoot, CS0 */
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-/* External SRAM at CS1 */
-#define CONFIG_SYS_CS1_START		0x62000000
-#define CONFIG_SYS_CS1_SIZE		0x00400000
-#define CONFIG_SYS_CS1_CFG		0x00009930
-#define CONFIG_SYS_SRAM_BASE		CONFIG_SYS_CS1_START
-#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_CS1_SIZE
-/* LED display at CS7 */
-#define CONFIG_SYS_CS7_START		0x6a000000
-#define CONFIG_SYS_CS7_SIZE		(64*1024)
-#define CONFIG_SYS_CS7_CFG		0x0000bf30
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333003
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000 /* 0x4000 for SE mode */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers                                                */
-#define CONFIG_SYS_ATA_STRIDE          4
-
-#define CONFIG_ATAPI                   1
-
-/*-----------------------------------------------------------------------
- * Open firmware flat tree support
- *-----------------------------------------------------------------------
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-/* Support for the 7-segment display */
-#define CONFIG_SYS_DISP_CHR_RAM	     CONFIG_SYS_CS7_START
-#define CONFIG_SHOW_ACTIVITY		/* used for display realization */
-
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
deleted file mode 100644
index 4eb8f39..0000000
--- a/include/configs/ac14xx.h
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2010 DAVE Srl <www.dave.eu>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * ifm AC14xx (MPC5121e based) board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_AC14XX 1
-
-/*
- * Memory map for the ifm AC14xx board:
- *
- * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
- * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
- * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
- * 0xE000_0000-0xEFFF_FFFF	several LPB attached hardware (CSx)
- * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_SYS_MPC512X_CLKIN	25000000	/* in Hz */
-#define SCFR1_IPS_DIV			2
-#define SCFR1_LPC_DIV			2
-#define SCFR1_NFC_DIV			2
-#define SCFR1_DIU_DIV			240
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR			0x80000000
-#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR + 0x2100)
-
-/* more aggressive 'mtest' over a wider address range */
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x0FE00000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-/*
- * DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-
-/*
- * NOTE: although this board uses DDR1 only, the common source brings defaults
- * for DDR2 init sequences, that's why we have to keep those here as well
- */
-
-/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
-#define CONFIG_SYS_IOCTRL_MUX_DDR	((0 << 6) | (3 << 3) | (3 << 0))
-
-#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
-			| (1 << 31)	/* RST_B */ \
-			| (1 << 30)	/* CKE */ \
-			| (1 << 29)	/* CLK_ON */ \
-			| (0 << 28)	/* CMD_MODE */ \
-			| (5 << 25)	/* DRAM_ROW_SELECT */ \
-			| (5 << 21)	/* DRAM_BANK_SELECT */ \
-			| (0 << 18)	/* SELF_REF_EN */ \
-			| (0 << 17)	/* 16BIT_MODE */ \
-			| (4 << 13)	/* RDLY */ \
-			| (1 << 12)	/* HALF_DQS_DLY */ \
-			| (0 << 11)	/* QUART_DQS_DLY */ \
-			| (1 <<  8)	/* WDLY */ \
-			| (0 <<  7)	/* EARLY_ODT */ \
-			| (0 <<  6)	/* ON_DIE_TERMINATE */ \
-			| (0 <<  5)	/* FIFO_OV_CLEAR */ \
-			| (0 <<  4)	/* FIFO_UV_CLEAR */ \
-			| (0 <<  1)	/* FIFO_OV_EN */ \
-			| (0 <<  0)	/* FIFO_UV_EN */ \
-			)
-
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x04E03124
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x30CA1147
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x32B10864
-
-/* register address only, i.e. template without values */
-#define CONFIG_SYS_MICRON_BMODE		0x01000000
-#define CONFIG_SYS_MICRON_EMODE		0x01010000
-#define CONFIG_SYS_MICRON_EMODE2	0x01020000
-#define CONFIG_SYS_MICRON_EMODE3	0x01030000
-/*
- * values for mode registers (without mode register address)
- */
-/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
-#define CONFIG_SYS_MICRON_BMODE_PARAM	0x00000062
-#define CONFIG_SYS_MICRON_BMODE_RSTDLL	0x00000100
-/* DLL enable, reduced drive strength */
-#define CONFIG_SYS_MICRON_EMODE_PARAM	0x00000002
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_MICRON_EMR	       ((1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(0 << 10) |	/* A10->DQS# */ \
-					(0 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(0 <<  2) |	/* Rtt0 */ \
-					(1 <<  1) |	/* ODS */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-#define CONFIG_SYS_MICRON_EMR2		0x01020000
-#define CONFIG_SYS_MICRON_EMR3		0x01030000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_MICRON_EMR_OCD      ((1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(1 << 10) |	/* A10->DQS# */ \
-					(7 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(1 <<  2) |	/* Rtt0 */ \
-					(0 <<  1) |	/* ODS */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-
-/*
- * Backward compatible definitions,
- * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
- */
-#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
-#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
-#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
-#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ \
-	CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
-	}
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * SRAM support
- */
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-/*
- * CS related parameters
- */
-/* CS0 Flash */
-#define CONFIG_SYS_CS0_CFG		0x00031110
-#define CONFIG_SYS_CS0_START		0xFC000000
-#define CONFIG_SYS_CS0_SIZE		0x04000000
-/* CS1 FRAM */
-#define CONFIG_SYS_CS1_CFG		0x00011000
-#define CONFIG_SYS_CS1_START		0xE0000000
-#define CONFIG_SYS_CS1_SIZE		0x00010000
-/* CS2 AS-i 1 */
-#define CONFIG_SYS_CS2_CFG		0x00009100
-#define CONFIG_SYS_CS2_START		0xE0100000
-#define CONFIG_SYS_CS2_SIZE		0x00080000
-/* CS3 netX */
-#define CONFIG_SYS_CS3_CFG		0x000A1140
-#define CONFIG_SYS_CS3_START		0xE0300000
-#define CONFIG_SYS_CS3_SIZE		0x00020000
-/* CS5 safety */
-#define CONFIG_SYS_CS5_CFG		0x0011F000
-#define CONFIG_SYS_CS5_START		0xE0400000
-#define CONFIG_SYS_CS5_SIZE		0x00010000
-/* CS6 AS-i 2 */
-#define CONFIG_SYS_CS6_CFG		0x00009100
-#define CONFIG_SYS_CS6_START		0xE0200000
-#define CONFIG_SYS_CS6_SIZE		0x00080000
-
-/* Don't use alternative CS timing for any CS */
-#define CONFIG_SYS_CS_ALETIMING		0x00000000
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x00000020
-#define CONFIG_SYS_CS_HOLDCYCLE		0x00000020
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
-
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX		1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-
-#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |		\
-			 CLOCK_SCCR1_LPC_EN |		\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
-			 CLOCK_SCCR1_PSC_EN(7) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |	\
-			 CLOCK_SCCR1_DDR_EN |		\
-			 CLOCK_SCCR1_FEC_EN |		\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
-
-#define CONFIG_CMDLINE_EDITING		1	/* command line history */
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC		1
-#define CONFIG_PHY_ADDR			0x1F
-#define CONFIG_MII			1	/* MII PHY management */
-#define CONFIG_FEC_AN_TIMEOUT		1
-#define CONFIG_HAS_ETH0
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH		1
-/* This has to be a multiple of the flash sector size */
-#define CONFIG_ENV_ADDR			0xFFF40000
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_SECT_SIZE		0x20000
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
-					 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO		1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
-
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-				 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS	32
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
-#endif
-
-#define CONFIG_SYS_HID0_INIT		0x000000000
-#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
-					 HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS		1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_TIMESTAMP
-
-/* default load addr for tftp and bootm */
-#define CONFIG_LOADADDR		400000
-
-
-/* the builtin environment and standard greeting */
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
-	"muster_nr=-00\0"						\
-	"fromram=run ramargs addip addtty; "				\
-		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
-		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
-		"tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; "	\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
-	"fromnfs=run nfsargs addip addtty; "				\
-		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
-		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"fromflash=run nfsargs addip addtty; "				\
-		"bootm fc020000 - fc000000\0"				\
-	"mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0"		\
-	"recovery=run mtdargsrec addip addtty; "			\
-		"bootm ffd20000 - ffee0000\0"				\
-	"production=run ramargs addip addtty; "				\
-		"bootm fc020000 fc400000 fc000000\0"			\
-	"mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0"		\
-	"prodmtd=run mtdargs addip addtty; "				\
-		"bootm fc020000 - fc000000\0"				\
-	""
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=a00000\0"						\
-	"ramdisk_addr_r=b00000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FC020000\0"					\
-	"fdt_addr=FC000000\0"						\
-	"ramdisk_addr=FC400000\0"					\
-	"verify=n\0"							\
-	"ramdiskfile=ac14xx/uRamdisk\0"					\
-	"u-boot=ac14xx/u-boot.bin\0"					\
-	"bootfile=ac14xx/uImage\0"					\
-	"fdtfile=ac14xx/ac14xx.dtb\0"					\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"hostname=ac14xx\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}${muster_nr}\0"	\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run production"
-
-#define CONFIG_ARP_TIMEOUT	200UL
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/aria.h b/include/configs/aria.h
deleted file mode 100644
index 3612e03..0000000
--- a/include/configs/aria.h
+++ /dev/null
@@ -1,589 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009, DAVE Srl <www.dave.eu>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Aria board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ARIA 1
-
-/*
- * Memory map for the ARIA board:
- *
- * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
- * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
- * 0x3010_0000-0x3011_FFFF	On Board SRAM (128 KB) - CS6
- * 0x3020_0000-0x3021_FFFF	FPGA (128 KB) - CS2
- * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
- * 0x8400_0000-0x82FF_FFFF	PCI I/O space (16 MB)
- * 0xA000_0000-0xAFFF_FFFF	PCI memory space (256 MB)
- * 0xB000_0000-0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
- * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-/* video */
-
-/* CONFIG_PCI is defined at config time */
-
-#define CONFIG_SYS_MPC512X_CLKIN	33000000	/* in Hz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR			0x80000000
-#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
-
-/* DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG     (	(1 << 31) |	/* RST_B */ \
-					(1 << 30) |	/* CKE */ \
-					(1 << 29) |	/* CLK_ON */ \
-					(0 << 28) |	/* CMD_MODE */ \
-					(4 << 25) |	/* DRAM_ROW_SELECT */ \
-					(3 << 21) |	/* DRAM_BANK_SELECT */ \
-					(0 << 18) |	/* SELF_REF_EN */ \
-					(0 << 17) |	/* 16BIT_MODE */ \
-					(2 << 13) |	/* RDLY */ \
-					(0 << 12) |	/* HALF_DQS_DLY */ \
-					(1 << 11) |	/* QUART_DQS_DLY */ \
-					(2 <<  8) |	/* WDLY */ \
-					(0 <<  7) |	/* EARLY_ODT */ \
-					(1 <<  6) |	/* ON_DIE_TERMINATE */ \
-					(0 <<  5) |	/* FIFO_OV_CLEAR */ \
-					(0 <<  4) |	/* FIFO_UV_CLEAR */ \
-					(0 <<  1) |	/* FIFO_OV_EN */ \
-					(0 <<  0) 	/* FIFO_UV_EN */ \
-				     )
-
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x030C3D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x55D81189
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34790863
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_MICRON_EMR	     (	(1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(0 << 10) |	/* A10->DQS# */ \
-					(0 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(0 <<  2) |	/* Rtt0 */ \
-					(1 <<  1) |	/* ODS */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-#define CONFIG_SYS_MICRON_EMR2		0x01020000
-#define CONFIG_SYS_MICRON_EMR3		0x01030000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_MICRON_EMR_OCD    (	(1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(1 << 10) |	/* A10->DQS# */ \
-					(7 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(1 <<  2) |	/* Rtt0 */ \
-					(0 <<  1) |	/* ODS (Output Drive Strength) */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-
-/*
- * Backward compatible definitions,
- * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
- */
-#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
-#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
-#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
-#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE		0x08000000	/* max flash size */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* max sectors */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND FLASH support
- * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
- */
-#define CONFIG_CMD_NAND					/* enable NAND support */
-#define CONFIG_JFFS2_NAND				/* with JFFS2 on it */
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH		1
-#define CONFIG_FSL_NFC_WRITE_SIZE	2048
-#define CONFIG_FSL_NFC_SPARE_SIZE	64
-#define CONFIG_FSL_NFC_CHIPS		CONFIG_SYS_MAX_NAND_DEVICE
-
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-/* Make two SRAM regions contiguous */
-#define CONFIG_SYS_ARIA_SRAM_BASE	(CONFIG_SYS_SRAM_BASE + \
-					 CONFIG_SYS_SRAM_SIZE)
-#define CONFIG_SYS_ARIA_SRAM_SIZE	0x00100000	/* reserve 1MB-window */
-#define CONFIG_SYS_CS6_START		CONFIG_SYS_ARIA_SRAM_BASE
-#define CONFIG_SYS_CS6_SIZE		CONFIG_SYS_ARIA_SRAM_SIZE
-
-#define CONFIG_SYS_ARIA_FPGA_BASE	(CONFIG_SYS_ARIA_SRAM_BASE + \
-					 CONFIG_SYS_ARIA_SRAM_SIZE)
-#define CONFIG_SYS_ARIA_FPGA_SIZE	0x20000		/* 128 KB */
-
-#define CONFIG_SYS_CS2_START		CONFIG_SYS_ARIA_FPGA_BASE
-#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_ARIA_FPGA_SIZE
-
-#define CONFIG_SYS_CS0_CFG		0x05059150
-#define CONFIG_SYS_CS2_CFG		(	(5 << 24) | \
-						(5 << 16) | \
-						(1 << 15) | \
-						(0 << 14) | \
-						(0 << 13) | \
-						(1 << 12) | \
-						(0 << 10) | \
-						(3 <<  8) | /* 32 bit */ \
-						(0 <<  7) | \
-						(1 <<  6) | \
-						(1 <<  4) | \
-						(0 <<  3) | \
-						(0 <<  2) | \
-						(0 <<  1) | \
-						(0 <<  0)   \
-					)
-#define CONFIG_SYS_CS6_CFG		0x05059150
-
-/* Use alternative CS timing for CS0 and CS2 */
-#define CONFIG_SYS_CS_ALETIMING	0x00000005
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
-
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/* FPGA */
-#define CONFIG_ARIA_FPGA		1
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX		1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
-
-#define CONFIG_CMDLINE_EDITING		1	/* command line history */
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_SYS_PCI_MEM_BASE		0xA0000000
-#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + \
-					 CONFIG_SYS_PCI_MEM_SIZE)
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
-#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC		1
-#define CONFIG_PHY_ADDR			0x17
-#define CONFIG_MII			1	/* MII PHY management */
-#define CONFIG_FEC_AN_TIMEOUT		1
-#define CONFIG_HAS_ETH0
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the flash sector size */
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + \
-					 CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_SECT_SIZE		0x20000	/* one sector (256K) */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
-					 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO		1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
-
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=f8000000.flash,nand0=mpc5121.nand"
-
-/*
- * NOR flash layout:
- *
- * F8000000 - FEAFFFFF	107 MiB		User Data
- * FEB00000 - FFAFFFFF	 16 MiB		Root File System
- * FFB00000 - FFFEFFFF	  4 MiB		Linux Kernel
- * FFF00000 - FFFBFFFF	768 KiB		U-Boot (up to 512 KiB) and 2 x * env
- * FFFC0000 - FFFFFFFF	256 KiB		Device Tree
- *
- * NAND flash layout: one big partition
- */
-#define MTDPARTS_DEFAULT	"mtdparts=f8000000.flash:107m(user),"	\
-						"16m(rootfs),"		\
-						"4m(kernel),"		\
-						"768k(u-boot),"		\
-						"256k(dtb);"		\
-					"mpc5121.nand:-(data)"
-
-/*
- * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
- * is set to 0xFFFF, watchdog timeouts after about 64s. For details
- * refer to chapter 36 of the MPC5121e Reference Manual.
- */
-/* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
- /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-				 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS	32
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
-#endif
-
-#define CONFIG_SYS_HID0_INIT		0x000000000
-#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
-					 HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS		1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME			aria
-#define CONFIG_BOOTFILE			"aria/uImage"
-#define CONFIG_ROOTPATH			"/opt/eldk/ppc_6xx"
-
-#define CONFIG_LOADADDR			400000	/* default load addr */
-
-#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=880000\0"						\
-	"ramdisk_addr_r=900000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFB00000\0"					\
-	"fdt_addr=FFFC0000\0"						\
-	"ramdisk_addr=FEB00000\0"					\
-	"ramdiskfile=aria/uRamdisk\0"				\
-	"u-boot=aria/u-boot.bin\0"					\
-	"fdtfile=aria/aria.dtb\0"					\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
-
-/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
-
-/* Interval between registers	*/
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#define ATA_BASE_ADDR			get_pata_base()
-
-/*
- * Control register bit definitions
- */
-#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
-#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
-#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
-#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
-#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
-#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
-#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
-#define FSL_ATA_CTRL_IORDY_EN		0x01000000
-
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PATA_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
deleted file mode 100644
index b7c74b4..0000000
--- a/include/configs/canmb.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_CANMB		1	/* ... on canmb board - we need this for FEC.C */
-
-/*
- * allowed and functional CONFIG_SYS_TEXT_BASE values:
- * 0xfe000000	low boot at 0x00000100 (default board setting)
- * 0x00100000	RAM load and test
- */
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-/*
- * MUST be low boot - HIGHBOOT is not supported anymore
- */
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
-#   define CONFIG_SYS_LOWBOOT		1
-#   define CONFIG_SYS_LOWBOOT16	1
-#else
-#   error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/canmb/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration, expect one 16 Megabyte Bank at most
- */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		(2*128*1024)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE       (128*1024)
-
-/*
- * Memory map
- *
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
- */
-#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define	CONFIG_PHY_ADDR		0x0
-/*
- * GPIO configuration:
- * PSC1,2,3 predefined as UART
- * PCI disabled
- * Ethernet 100 with MD
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047D01
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/charon.h b/include/configs/charon.h
deleted file mode 100644
index 913b707..0000000
--- a/include/configs/charon.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_CHARON_H
-#define __CONFIG_CHARON_H
-
-#define CONFIG_CHARON
-#define CONFIG_HOSTNAME		charon
-
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x81550414
-
-/* include common defines/options for TQM52xx boards */
-#include "TQM5200.h"
-
-/* defines special on charon board */
-#undef CONFIG_RTC_MPC5200
-
-#undef CUSTOM_ENV_SETTINGS
-#define CUSTOM_ENV_SETTINGS					\
-	"bootfile=/tftpboot/charon/uImage\0"			\
-	"fdt_file=/tftpboot/charon/charon.dtb\0"		\
-	"u-boot=/tftpboot/charon/u-boot.bin\0"			\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
-
-/* additional features on charon board */
-#define CONFIG_RESET_PHY_R
-
-/*
- * I2C configuration
- */
-#define CONFIG_I2C_MULTI_BUS
-
-#define CONFIG_SYS_TFP410_ADDR	0x38
-#define CONFIG_SYS_TFP410_BUS	0
-
-/*
- * FPGA configuration
- */
-#define CONFIG_SYS_CS3_START		0xE8000000
-#define CONFIG_SYS_CS3_SIZE		0x80000	/* 512 KByte */
-
-/*
- * CS3 Config Register Init:
- * 	CS3 Enabled
- * 	AddrBus: 8bits
- *  	DataBus: 4bytes
- *  	Multiplexed: Yes
- *  	MuxBank: 00
- */
-#define CONFIG_SYS_CS3_CFG		0x00009310
-
-#endif /* __CONFIG_CHARON_H */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
deleted file mode 100644
index 3777a0d..0000000
--- a/include/configs/cm5200.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_CM5200		1	/* ... on CM5200 platform */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfc000000
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_ENV_OVERWRITE	1	/* allow overwriting of ethaddr */
-/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
-#define CONFIG_MISC_INIT_R	1
-#define CONFIG_MAC_OFFSET	0x35	/* MAC address offset in I2C EEPROM */
-
-/*
- * POST support
- */
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU)
-#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
-/* List of I2C addresses to be verified by POST */
-#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_SLAVE,	\
-					 CONFIG_SYS_I2C_IO,	\
-					 CONFIG_SYS_I2C_EEPROM}
-
-/* display image timestamps */
-#define CONFIG_TIMESTAMP	1
-
-/*
- * Autobooting
- */
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
-	"echo"
-#undef CONFIG_BOOTARGS
-
-/*
- * Default environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"netmask=255.255.0.0\0"						\
-	"ipaddr=192.168.160.33\0"					\
-	"serverip=192.168.1.1\0"					\
-	"gatewayip=192.168.1.1\0"					\
-	"console=ttyPSC0\0"						\
-	"u-boot_addr=100000\0"						\
-	"kernel_addr=200000\0"						\
-	"kernel_addr_flash=fc0c0000\0"					\
-	"fdt_addr=400000\0"						\
-	"fdt_addr_flash=fc0a0000\0"					\
-	"ramdisk_addr=500000\0"						\
-	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
-	"u-boot=/tftpboot/cm5200/u-boot.bin\0"				\
-	"bootfile_fdt=/tftpboot/cm5200/uImage\0"			\
-	"fdt_file=/tftpboot/cm5200/cm5200.dtb\0"			\
-	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
-	"update=prot off fc000000 +${filesize}; "			\
-		"era fc000000 +${filesize}; "				\
-		"cp.b ${u-boot_addr} fc000000 ${filesize}; "		\
-		"prot on fc000000 +${filesize}\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"		\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addinit=setenv bootargs ${bootargs} init=/linuxrc\0"		\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=${console},${baudrate}\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
-		"${netmask}:${hostname}:${netdev}:off panic=1\0"	\
-	"flash_flash=run flashargs addinit addip addcons;"		\
-		"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"	\
-	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "		\
-		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "	\
-		"addcons; bootm ${kernel_addr} - ${fdt_addr}\0"		\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_flash"
-
-/*
- * Low level configuration
- */
-
-/*
- * Clock configuration
- */
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* SYS_XTAL_IN = 33MHz */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	1	/* IPB = 133MHz */
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_LOWBOOT		1
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_BOARD_TYPES	1	/* we use board_type */
-
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* 256 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-/* we need these despite using CFI */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
-#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#undef CONFIG_SYS_LOWBOOT
-#endif
-
-/*
- * Chip selects configuration
- */
-/* Boot Chipselect */
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00087D31	/* for pci_clk = 33 MHz */
-/* use board_early_init_r to enable flash write in CS_BOOT */
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/* Flash memory addressing */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* No burst, dead cycle = 1 for CS0 (Flash) */
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x00000001
-
-/*
- * SDRAM configuration
- * settings for k4s561632E-xx75, assuming XLB = 132 MHz
- */
-#define SDRAM_MODE	0x00CD0000	/* CASL 3, burst length 8 */
-#define SDRAM_CONTROL	0x514F0000
-#define SDRAM_CONFIG1	0xE2333900
-#define SDRAM_CONFIG2	0x8EE70000
-
-/*
- * MTD configuration
- */
-#define CONFIG_CMD_MTDPARTS	1
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=cm5200-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cm5200-0:"			\
-					"384k(uboot),128k(env),"	\
-					"128k(redund_env),128k(dtb),"	\
-					"2m(kernel),27904k(rootfs),"	\
-					"-(config)"
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-
-/*
- * USB configuration
- */
-#define CONFIG_USB_OHCI		1
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-/* Partitions (for USB) */
-
-/*
- * Invoke our last_stage_init function - needed by fwupdate
- */
-#define CONFIG_LAST_STAGE_INIT	1
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-/* Configuration of redundant environment */
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Pin multiplexing configuration
- */
-
-/*
- * CS1/GPIO_WKUP_6: GPIO (default)
- * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
- * IRDA/PSC6: UART
- * Ether: Ethernet 100Mbit with MD
- * PCI_DIS: PCI controller disabled
- * USB: USB
- * PSC3: SPI with UART3
- * PSC2: UART
- * PSC1: UART
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x10559C44
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		1	/* undef to save memory */
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_ALT_MEMTEST		1
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_XLB_PIPELINING	1	/* enable transaction pipeling */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Flat Device Tree support
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
deleted file mode 100644
index 6710507..0000000
--- a/include/configs/digsy_mtc.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2005-2007
- * Modified for InterControl digsyMTC MPC5200 board by
- * Frank Bodammer, GCD Hard- & Software GmbH,
- *                 frank.bodammer@gcd-solutions.de
- *
- * (C) Copyright 2009 Semihalf
- * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000	boot high (standard configuration)
- * 0xFE000000	boot low
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4  */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCI_BOOTDELAY	250
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_BZIP2
-
-/*
- * Video
- */
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_VIDEO_CORALP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
-
-/* Coral-PA clock frequency, geo and other both 133MHz */
-#define CONFIG_SYS_MB862xx_CCF	0x00050000
-/* Video SDRAM parameters */
-#define CONFIG_SYS_MB862xx_MMR	0x11d7fa72
-#endif
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
-#define CONFIG_SYS_LOWBOOT	1
-#endif
-
-/*
- * Autobooting
- */
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"fw_image=digsyMPC.img\0"					\
-	"mtcb_start=mtc led diag orange; run mtcb_1\0"			\
-	"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "		\
-		"do mtc led $x; done\0"					\
-	"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "	\
-		"else run mtcb_fw; fi\0"				\
-	"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "		\
-		"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"	\
-	"mtcb_update=mtc led user1 orange;"				\
-		"while mtc key; do ; done; run mtcb_2;\0"		\
-	"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"	\
-	"mtcb_usb1=if fatload usb 0 400000 script.img; "		\
-		"then run mtcb_doscript; else run mtcb_usb2; fi\0"	\
-	"mtcb_usb2=if fatload usb 0 400000 $fw_image; "			\
-		"then run mtcb_dousb; else run mtcb_ide; fi\0"		\
-	"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "	\
-		"run mtcb_wait_flickr mtcb_ds_1;\0"			\
-	"mtcb_ds_1=if imi 400000; then mtc led usbbusy; "		\
-		"source 400000; else run mtcb_error; fi\0"		\
-	"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"	\
-	"mtcb_du_1=if imi 400000; then run mtcb_du_2; "			\
-		"else run mtcb_error; fi\0"				\
-	"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "		\
-		"run mtcb_checkfw\0"					\
-	"mtcb_checkfw=if imi ff000000; then run mtcb_success; "		\
-		"else run mtcb_error; fi\0"				\
-	"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0"	\
-	"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"		\
-	"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
-	"mtcb_uledflckr=mtc led user1 orange 11\0"			\
-	"mtcb_error=mtc led user1 red\0"				\
-	"mtcb_clear=erase ff000000 ff0fffff\0"				\
-	"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"			\
-	"mtcb_success=mtc led user1 green\0"				\
-	"mtcb_ide=if fatload ide 0 400000 $fw_image;"			\
-		"then run mtcb_doide; else run mtcb_error; fi\0"	\
-	"mtcb_doide=mtc led user2 green 1;"				\
-		"run mtcb_wait_flickr mtcb_di_1;\0"			\
-	"mtcb_di_1=if imi 400000; then run mtcb_di_2;"			\
-		"else run mtcb_error; fi\0"				\
-	"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"	\
-	"ramdisk_num_sector=16\0"					\
-	"flash_base=ff000000\0"						\
-	"flashdisk_size=e00000\0"					\
-	"env_sector=fff60000\0"						\
-	"flashdisk_start=ff100000\0"					\
-	"load_cmd=tftp 400000 digsyMPC.img\0"				\
-	"clear_cmd=erase ff000000 ff0fffff\0"				\
-	"flash_cmd=cp.b 400000 ff000000 ${filesize}\0"			\
-	"update_cmd=run load_cmd; "					\
-	"iminfo 400000; "						\
-	"run clear_cmd flash_cmd; "					\
-	"iminfo ff000000\0"						\
-	"spi_driver=yes\0"						\
-	"spi_watchdog=no\0"						\
-	"ftps_start=yes\0"						\
-	"ftps_user1=admin\0"						\
-	"ftps_pass1=admin\0"						\
-	"ftps_base1=/\0"						\
-	"ftps_home1=/\0"						\
-	"plc_sio_srv=no\0"						\
-	"plc_sio_baud=57600\0"						\
-	"plc_sio_parity=no\0"						\
-	"plc_sio_stop=1\0"						\
-	"plc_sio_com=2\0"						\
-	"plc_eth_srv=yes\0"						\
-	"plc_eth_port=1200\0"						\
-	"plc_root=/ide/\0"						\
-	"diag_level=0\0"						\
-	"webvisu=no\0"							\
-	"plc_can1_routing=no\0"						\
-	"plc_can1_baudrate=250\0"					\
-	"plc_can2_routing=no\0"						\
-	"plc_can2_baudrate=250\0"					\
-	"plc_can3_routing=no\0"						\
-	"plc_can3_baudrate=250\0"					\
-	"plc_can4_routing=no\0"						\
-	"plc_can4_baudrate=250\0"					\
-	"netdev=eth0\0"							\
-	"console=ttyPSC0\0"						\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=600000\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-	"nfsroot=${serverip}:${rootpath}\0"				\
-	"addip=setenv bootargs ${bootargs} "				\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
-	"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
-	"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdt_file};"			\
-		"run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"load=tftp 200000 ${u-boot}\0"					\
-	"update=protect off FFF00000 +${filesize};"			\
-		"erase FFF00000 +${filesize};"				\
-		"cp.b 200000 FFF00000 ${filesize};"			\
-		"protect on FFF00000 +${filesize}\0"			\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run mtcb_start"
-
-/*
- * Flash configuration
- */
-#define	CONFIG_SYS_FLASH_CFI		1
-#define	CONFIG_FLASH_CFI_DRIVER	1
-
-#if defined(CONFIG_DIGSY_REV5)
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_BASE_CS1	0xFC000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	2
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, \
-					CONFIG_SYS_FLASH_BASE_CS1}
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-#else
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-#define CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_SIZE	0x01000000
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#if defined(CONFIG_LOWBOOT)
-#define CONFIG_ENV_ADDR		0xFF060000
-#else	/* CONFIG_LOWBOOT */
-#define CONFIG_ENV_ADDR		0xFFF60000
-#endif	/* CONFIG_LOWBOOT */
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#else
-#define CONFIG_SYS_DEFAULT_MBAR	0xF0000000
-#endif
-
-/*
- *  Use SRAM until RAM will be available
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN	(4096 << 10)
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#if defined(CONFIG_DIGSY_REV5)
-#define CONFIG_PHY_ADDR		0x01
-#else
-#define CONFIG_PHY_ADDR		0x00
-#endif
-#define CONFIG_PHY_RESET_DELAY	1000
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-/*
- * GPIO configuration
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
- *  Bit 0   (mask 0x80000000) : 0x1
- * SPI on Tmr2/3/4/5 pins
- *  Bit 2:3 (mask 0x30000000) : 0x2
- * ATA cs0/1 on csb_4/5
- *  Bit 6:7 (mask 0x03000000) : 0x2
- * Ethernet 100Mbit with MD
- *  Bits 12:15 (mask 0x000f0000): 0x5
- * USB - Two UARTs
- *  Bits 18:19 (mask 0x00003000) : 0x2
- * PSC3 - USB2 on PSC3
- *  Bits 20:23 (mask 0x00000f00) : 0x1
- * PSC2 - CAN1&2 on PSC2 pins
- *  Bits 25:27 (mask 0x00000070) : 0x1
- * PSC1 - AC97 functionality
- *  Bits 29:31 (mask 0x00000007) : 0x2
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0xA2552112
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE	1
-#define CONFIG_CMDLINE_EDITING	1
-
-#define CONFIG_MX_CYCLIC	1
-
-#define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		32
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_SCRATCH	0x00001000
-#define CONFIG_SYS_MEMTEST_START	0x00010000
-#define CONFIG_SYS_MEMTEST_END		0x019fffff
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_SDRAM_CS1		1
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#if defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
-#endif
-
-#define CONFIG_SYS_CS4_START		0x60000000
-#define CONFIG_SYS_CS4_SIZE		0x1000
-#define CONFIG_SYS_CS4_CFG		0x0008FC00
-
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_CFG		0x0002DD00
-
-#if defined(CONFIG_DIGSY_REV5)
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE_CS1
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_CFG		0x0002DD00
-#endif
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x11111111
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#else
-#define CONFIG_SYS_RESET_ADDRESS	0xff000100
-#endif
-
-/*
- * USB
- */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#define CONFIG_USB_CLOCK	0x00013333
-#define CONFIG_USB_CONFIG	0x00002000
-
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-
-/*
- * IDE/ATA
- */
-#define CONFIG_IDE_RESET
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_ATA_CS_ON_I2C2
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#define CONFIG_ATAPI		1
-#define CONFIG_LBA48		1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
deleted file mode 100644
index 2816522..0000000
--- a/include/configs/inka4x0.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * (C) Copyright 2009
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU	*/
-#define CONFIG_INKA4X0		1	/* INKA4x0 board		*/
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFE00000	boot low
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFE00000	/* Standard: boot low */
-#endif
-#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
-
-#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-/* Partitions */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)		/* Boot low */
-#   define CONFIG_SYS_LOWBOOT		1
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_IPADDR		192.168.100.2
-#define	CONFIG_SERVERIP		192.168.100.1
-#define	CONFIG_NETMASK		255.255.255.0
-#define HOSTNAME		inka4x0
-#define CONFIG_BOOTFILE		"/tftpboot/inka4x0/uImage"
-#define	CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate}\0"				\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addcons;bootm\0"			\
-	"enable_disp=mw.l 100000 04000000 1;"				\
-		"cp.l 100000 f0000b20 1;"				\
-		"cp.l 100000 f0000b28 1\0"				\
-	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
-	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
-		"run ideargs addip addcons enable_disp;bootm\0"		\
-	"brightness=255\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run ide_boot"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
-#define CONFIG_SYS_FLASH_SIZE		0x00200000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/*
- * SDRAM controller configuration
- */
-#undef CONFIG_SDR_MT48LC16M16A2
-#undef CONFIG_DDR_MT46V16M16
-#undef CONFIG_DDR_MT46V32M16
-#undef CONFIG_DDR_HYB25D512160BF
-#define CONFIG_DDR_K4H511638C
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
-
-#ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII
-
-/*
- * GPIO configuration
- *
- * use CS1 as gpio_wkup_6 output
- *	Bit 0 (mask: 0x80000000): 0
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
- *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
- *	      EEPROM
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
- * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
- * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x01501444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* 32Mbit SRAM @0x30000000 */
-#define CONFIG_SYS_CS1_START		0x30000000
-#define CONFIG_SYS_CS1_SIZE		0x00400000
-#define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
-
-/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
-#define CONFIG_SYS_CS2_START		0x80000000
-#define CONFIG_SYS_CS2_SIZE		0x0001000
-#define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
-
-/* GPIO in @0x30400000 */
-#define CONFIG_SYS_CS3_START		0x30400000
-#define CONFIG_SYS_CS3_SIZE		0x00100000
-#define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_CLOCK	0x00015555
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/
-
-#define CONFIG_ATAPI            1
-
-#define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
deleted file mode 100644
index c6390db..0000000
--- a/include/configs/ipek01.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * (C) Copyright 2009
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_MPX5200		1	/* MPX5200 board */
-#define CONFIG_MPC5200_DDR	1	/* use DDR RAM */
-#define CONFIG_IPEK01           	/* Motherboard is ipek01 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfc000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_CACHELINE_SIZE	32 /* For MPC5xxx CPUs */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5  /* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
-
-/*
- * Video configuration for LIME GDC
- */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
-/* Lime clock frequency */
-#define CONFIG_SYS_MB862xx_CCF	0x90000	/* geo 166MHz other 133MHz */
-/* SDRAM parameter */
-#define CONFIG_SYS_MB862xx_MMR	0x41c767e3
-#endif
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI_SCAN_SHOW	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_MII		1
-#define CONFIG_EEPRO100		1
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI		/* pciinfo */
-
-#define CONFIG_SYS_LOWBOOT	1
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyPSC0\0"						\
-	"hostname=ipek01\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consoledev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdtaddr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"	\
-	"net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
-		"run nfsargs addip addtty;"    				\
-		 "bootm ${loadaddr} - ${fdtaddr}\0"			\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=ipek01/uImage\0"					\
-	"load=tftp 100000 ipek01/u-boot.bin\0"				\
-	"update=protect off FC000000 +60000; era FC000000 +60000; "	\
-		"cp.b 100000 FC000000 ${filesize}\0"   			\
-	"upd=run load;run update\0"					\
-	"fdtaddr=800000\0"						\
-	"loadaddr=400000\0"						\
-	"fdtfile=ipek01/ipek01.dtb\0"					\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 	/* for 133MHz */
-/* PCI clock must be 33, because board will not boot */
-#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for 66MHz */
-
-/*
- * Open firmware flat tree support
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
-					 CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	256  /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */
-
-/* use CFI flash driver */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x10000
-#define CONFIG_ENV_SECT_SIZE		0x20000
-#define CONFIG_ENV_OVERWRITE		1
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR			0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
-#define	CONFIG_SYS_SRAM_BASE		0xF1000000
-#define	CONFIG_SYS_SRAM_SIZE		0x00200000
-#define	CONFIG_SYS_LIME_BASE		0xE4000000
-#define	CONFIG_SYS_LIME_SIZE		0x04000000
-#define	CONFIG_SYS_FPGA_BASE		0xC0000000
-#define	CONFIG_SYS_FPGA_SIZE		0x10000000
-#define	CONFIG_SYS_MPEG_BASE		0xe2000000
-#define	CONFIG_SYS_MPEG_SIZE		0x01000000
-#define CONFIG_SYS_CF_BASE		0xe1000000
-#define CONFIG_SYS_CF_SIZE		0x01000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-/* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN	(384 << 10)  /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN	(4 << 20)    /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)    /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC		1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR			0x00
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1d556624
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1...15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_CS3_START		CONFIG_SYS_LIME_BASE
-#define CONFIG_SYS_CS3_SIZE		CONFIG_SYS_LIME_SIZE
-#define	CONFIG_SYS_CS6_START		CONFIG_SYS_FPGA_BASE
-#define	CONFIG_SYS_CS6_SIZE		CONFIG_SYS_FPGA_SIZE
-#define	CONFIG_SYS_CS5_START		CONFIG_SYS_CF_BASE
-#define	CONFIG_SYS_CS5_SIZE		CONFIG_SYS_CF_SIZE
-#define	CONFIG_SYS_CS7_START		CONFIG_SYS_MPEG_BASE
-#define	CONFIG_SYS_CS7_SIZE		CONFIG_SYS_MPEG_SIZE
-
-#ifdef CONFIG_SYS_PCISPEED_66
-#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
-#define CONFIG_SYS_CS1_CFG		0x0004FB00
-#define CONFIG_SYS_CS2_CFG		0x0006F900
-#else
-#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
-#define CONFIG_SYS_CS1_CFG		0x0001FB00
-#define CONFIG_SYS_CS2_CFG		0x0002F90C
-#endif
-
-/*
- * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
- * waitstates, writeswap and readswap enabled
- */
-#define CONFIG_SYS_CS3_CFG		0x00FFFB0C
-#define	CONFIG_SYS_CS6_CFG		0x00FFFB0C
-#define	CONFIG_SYS_CS7_CFG		0x4040751C
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x33330000
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK		0x0001BBBB
-#define CONFIG_USB_CONFIG		0x00005000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE	2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
deleted file mode 100644
index 4461623..0000000
--- a/include/configs/jupiter.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_JUPITER		1	/* ... on Jupiter board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000	boot high (standard configuration)
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_BOARD_EARLY_INIT_R	1
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-#endif
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-#define CONFIG_MII		1
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-
-/* Partitions */
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-
-#if defined(CONFIG_PCI)
-#define CODFIG_CMD_PCI
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"addcons=setenv bootargs ${bootargs} console=${contyp},"	\
-		"${baudrate}\0"						\
-	"contyp=ttyS0\0"						\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/jupiter/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
-
-#if 0
-/* pass open firmware flat tree */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_SYS_UPDATE_FLASH_SIZE	1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-#define CONFIG_SYS_ALT_MEMTEST		1
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
deleted file mode 100644
index 736bebb..0000000
--- a/include/configs/manroland/mpc5200-common.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2009
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MANROLAND_MPC52XX__COMMON_H
-#define __MANROLAND_MPC52XX__COMMON_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200		1	/* MPC5200 CPU */
-
-/* ... running at 33.000000MHz	*/
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported		*/
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200,\
-					 230400 }
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
-#   define CONFIG_SYS_LOWBOOT		1
-#endif
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFF800000
-
-#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
-
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout [ms]*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout [ms]*/
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SRAM_BASE	0x80100000	/* CS 1 */
-#define CONFIG_SYS_DISPLAY_BASE	0x80600000	/* CS 3 */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_DDR	 1
-#define SDRAM_MODE      0x018D0000
-#define SDRAM_EMODE     0x40090000
-#define SDRAM_CONTROL   0x714f0f00
-#define SDRAM_CONFIG1   0x73722930
-#define SDRAM_CONFIG2   0x47770000
-#define SDRAM_TAPDELAY  0x10000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII		1
-
-/*use  Hardware WDT */
-#define CONFIG_HW_WATCHDOG
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs	*/
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus	*/
-
-#define CONFIG_IDE_PREINIT	1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers	*/
-#define CONFIG_SYS_ATA_STRIDE          4
-
-#define CONFIG_ATAPI            1
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-#define CONFIG_OF_IDE_FIXUP
-
-#endif /* __MANROLAND_MPC52XX__COMMON_H */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
deleted file mode 100644
index 17a97df..0000000
--- a/include/configs/mecp5123.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009, DAVE Srl <www.dave.eu>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
- *
- */
-
-/*
- * MECP5123 board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MECP5123 1
-
-/*
- * Memory map for the MECP5123 board:
- *
- * 0x0000_0000 - 0x1FFF_FFFF	DDR RAM (512 MB)
- * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
- * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
- * 0x8200_0000 - 0x8200_FFFF	VPC-3 (64 KB)
- * 0xFFC0_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR		        0x80000000
-#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#define CONFIG_SYS_DDR_SIZE		512		/* MB */
-
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
-
-/* DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG	 0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG0	 0x06183D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_DDRCMD_EM2		0x01020000
-#define CONFIG_SYS_DDRCMD_EM3		0x01030000
-#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	0x01010780
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-
-#define CONFIG_SYS_FLASH_BASE		0xFFC00000	/* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* max flash size */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND FLASH
- * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE            0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH		1
-#define CONFIG_FSL_NFC_WRITE_SIZE	2048
-#define CONFIG_FSL_NFC_SPARE_SIZE	64
-#define CONFIG_FSL_NFC_CHIPS		1
-
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-/* Initialize Local Window for NOR FLASH access */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* ALE active low, data size 4bytes */
-#define CONFIG_SYS_CS0_CFG		0x05051150
-
-/* Use not alternative CS timing */
-#define CONFIG_SYS_CS_ALETIMING		0x00000000
-
-/* ALE active low, data size 4bytes */
-#define CONFIG_SYS_CS1_CFG		0x1f1f3090
-#define CONFIG_SYS_VPC3_BASE		0x82000000	/* start of VPC3 space */
-#define CONFIG_SYS_VPC3_SIZE		0x00010000	/* max VPC3 size */
-/* Initialize Local Window for VPC3 access */
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_VPC3_BASE
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_VPC3_SIZE
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Monitor length */
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* Malloc size */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |	\
-			 CLOCK_SCCR2_I2C_EN)
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC	1
-#define CONFIG_PHY_ADDR		0x1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_FEC_AN_TIMEOUT	1
-#define CONFIG_HAS_ETH0
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_SYS_RTC_BUS_NUM  0x01
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-#define CONFIG_RTC_RX8025
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_NOWHERE		/* Store env in I2C EEPROM	*/
-#define CONFIG_ENV_SIZE		0x1000
-#define CONFIG_ENV_OFFSET       0x0000	/* environment starts here	*/
-
-#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
-
-#define CONFIG_CMD_REGINFO
-
-/*
- * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
- * to 0xFFFF, watchdog timeouts after about 64s. For details refer
- * to chapter 36 of the MPC5121e Reference Manual.
- */
-/* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
- /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-				 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS	32
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Linux initial memory map */
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
-#define CONFIG_SYS_HID2		HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME		mecp512x
-#define CONFIG_BOOTFILE		"/tftpboot/mecp512x/uImage"
-#define CONFIG_ROOTPATH		"/tftpboot/mecp512x/target_root"
-
-#define CONFIG_LOADADDR		400000	/* def. location for tftp and bootm */
-
-#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Welcome to MECP5123" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=880000\0"						\
-	"ramdisk_addr_r=900000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFC40000\0"					\
-	"fdt_addr=FFEC0000\0"						\
-	"ramdisk_addr=FC040000\0"					\
-	"ramdiskfile=/tftpboot/mecp512x/uRamdisk\0"			\
-	"u-boot=/tftpboot/mecp512x/u-boot.bin\0"			\
-	"bootfile=/tftpboot/mecp512x/uImage\0"				\
-	"fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0"			\
-	"rootpath=/tftpboot/mecp512x/target_root\n"	      		\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
deleted file mode 100644
index 75633f6..0000000
--- a/include/configs/motionpro.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-/* CPU and board */
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_MOTIONPRO	1	/* ... on Promess Motion-PRO board */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_NETCONSOLE	1	/* network console */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x2
-#define CONFIG_PHY_TYPE		0x79c874
-#define CONFIG_RESET_PHY_R	1
-
-/*
- * Autobooting
- */
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_CMDLINE_EDITING		1	/* add command line history	*/
-
-/*
- * Default environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=motionpro\0"						\
-	"netmask=255.255.255.0\0"					\
-	"ipaddr=192.168.1.106\0"					\
-	"serverip=192.168.1.100\0"					\
-	"gatewayip=192.168.1.100\0"					\
-	"console=ttyPSC0,115200\0"					\
-	"u-boot_addr=400000\0"						\
-	"kernel_addr=400000\0"						\
-	"fdt_addr=700000\0"						\
-	"ramdisk_addr=800000\0"						\
-	"multi_image_addr=800000\0"					\
-	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
-	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
-	"bootfile=/tftpboot/motionpro/uImage\0"				\
-	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
-	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
-	"multi_image_file=kernel+initrd+dtb.img\0"			\
-	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
-	"update=prot off fff00000 +${filesize};"			\
-		"era fff00000 +${filesize}; "				\
-		"cp.b ${u-boot_addr} fff00000 ${filesize};"		\
-		"prot on fff00000 +${filesize}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"fat_args=setenv bootargs root=/dev/sda rw\0"			\
-	"mtdids=nor0=ff000000.flash\0"					\
-	"mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," 	\
-				"128k(env),128k(redund_env),"	  	\
-				"128k(dtb),128k(user_data)\0"		\
-	"addcons=setenv bootargs ${bootargs} console=${console}\0"	\
-	"addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0"	\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
-		"${netmask}:${hostname}:${netdev}:off panic=1 "		\
-		"console=${console}\0"					\
-	"net_nfs=tftp ${kernel_addr} ${bootfile}; "			\
-		"tftp ${fdt_addr} ${fdt_file}; "			\
-		"run nfsargs addip addmtd; "				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_self=tftp ${kernel_addr} ${bootfile}; "			\
-		"tftp ${fdt_addr} ${fdt_file}; "			\
-		"tftp ${ramdisk_addr} ${ramdisk_file}; "		\
-		"nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; "	\
-		"run ramargs addip addcons addmtd; "			\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"fat_multi=run fat_args addip addmtd; fatload ide 0:1 "		\
-		"${multi_image_addr} ${multi_image_file}; "		\
-		"bootm ${multi_image_addr}\0"				\
-	""
-#define CONFIG_BOOTCOMMAND	"run fat_multi"
-
-/*
- * do board-specific init
- */
-#define CONFIG_BOARD_EARLY_INIT_R	1
-
-/*
- * Low level configuration
- */
-
-/*
- * Clock configuration: SYS_XTALIN = 33MHz
- */
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-/*
- * Set IPB speed to 100MHz
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-
-/*
- * Memory map
- */
-/*
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000.
- * Setting MBAR to otherwise will cause system hang when using SmartDMA such
- * as network commands.
- */
-#define CONFIG_SYS_MBAR			0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-
-/*
- * If building for running out of SDRAM, then MBAR has been set up beforehand
- * (e.g., by the BDI). Otherwise we must specify the default boot-up value of
- * MBAR, as given in the doccumentation.
- */
-#if CONFIG_SYS_TEXT_BASE == 0x00100000
-#define CONFIG_SYS_DEFAULT_MBAR	0xf0000000
-#else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#define CONFIG_SYS_LOWBOOT		1
-#endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* 1 MiB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
-
-/*
- * Chip selects configuration
- */
-/* Boot Chipselect */
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00045D00
-
-/* Flash memory addressing */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_CFG		CONFIG_SYS_BOOTCS_CFG
-
-/* Dual Port SRAM -- Kollmorgen Drive memory addressing */
-#define CONFIG_SYS_CS1_START		0x50000000
-#define CONFIG_SYS_CS1_SIZE		0x10000
-#define CONFIG_SYS_CS1_CFG		0x05055800
-
-/* Local register access */
-#define CONFIG_SYS_CS2_START		0x50010000
-#define CONFIG_SYS_CS2_SIZE		0x10000
-#define CONFIG_SYS_CS2_CFG		0x05055800
-
-/* Anybus CompactCom Module memory addressing */
-#define CONFIG_SYS_CS3_START		0x50020000
-#define CONFIG_SYS_CS3_SIZE		0x10000
-#define CONFIG_SYS_CS3_CFG		0x05055800
-
-/* No burst and dead cycle = 2 for all CSs */
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x22222222
-
-/*
- * SDRAM configuration
- */
-/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */
-#define SDRAM_CONFIG1		0x62322900
-#define SDRAM_CONFIG2		0x88c70000
-#define SDRAM_CONTROL		0x504f0000
-#define SDRAM_MODE		0x00cd0000
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
-
-/*
- * MTD configuration
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=motionpro-0"
-#define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
-					"13m(fs),2m(kernel),384k(uboot)," \
-					"128k(env),128k(redund_env),"	  \
-					"128k(dtb),-(user_data)"
-
-/*
- * IDE/ATA configuration
- */
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	1
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060
-#define CONFIG_SYS_ATA_REG_OFFSET	CONFIG_SYS_ATA_DATA_OFFSET
-#define CONFIG_SYS_ATA_STRIDE		4
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_DS1337	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-
-/*
- * Status LED configuration
- */
-
-#define ENABLE_GPIO_OUT		0x00000024
-#define LED_ON			0x00000010
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x1000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-
-/* Configuration of redundant environment */
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Pin multiplexing configuration
- */
-
-/* PSC1: UART1
- * PSC2: GPIO (default)
- * PSC3: GPIO (default)
- * USB: 2xUART4/5
- * Ethernet: Ethernet 100Mbit with MD
- * Timer: CAN2/GPIO
- * PSC6/IRDA: GPIO (default)
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1105a004
-
-/*
- * Motion-PRO's CPLD revision control register
- */
-#define CPLD_REV_REGISTER	(CONFIG_SYS_CS2_START + 0x06)
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory    */
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03e00000	/* 1 ... 62 MiB in DRAM */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default kernel load addr */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-
-/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h
deleted file mode 100644
index d252297..0000000
--- a/include/configs/mpc5121-common.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2010 DENX Software Engineering
- * Anatolij Gustschin <agust@denx.de>
- *
- * Common configuration options for MPC5121 based boards
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MPC5121_COMMON_H
-#define __MPC5121_COMMON_H
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM base */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE /* Size of area */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * Serial console
- */
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_CMDLINE_EDITING		1	/* command line history */
-
-#endif /* __MPC5121_COMMON_H */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
deleted file mode 100644
index a6aaf0e..0000000
--- a/include/configs/mpc5121ads.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * MPC5121ADS board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC5121ADS 1
-
-/*
- * Memory map for the MPC5121ADS board:
- *
- * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
- * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
- * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
- * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
- * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
- * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
- * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
- * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-/* video */
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_IMMR + 0x2100)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-/* CONFIG_PCI is defined at config time */
-
-#ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_MPC512X_CLKIN	66000000	/* in Hz */
-#else
-#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
-#endif
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR		0x80000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#else
-#define CONFIG_SYS_DDR_SIZE		512		/* MB */
-#endif
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
-
-/* DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xE8604A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
-#else
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34310864
-#endif
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x06183D2E
-
-#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA	 	0xEA802B00
-#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA	0x690e1189
-#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA	0x35310864
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_DDRCMD_EM2		0x01020000
-#define CONFIG_SYS_DDRCMD_EM3		0x01030000
-#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-
-#define DDRCMD_EMR_OCD(pr, ohm) ( \
-	(1 << 24)	   | /* MDDRC Command Request	*/ \
-	(1 << 16)	   | /* MODE Reg BA[2:0] 	*/ \
-	(0 << 12)	   | /* Outputs 0=Enabled	*/ \
-	(0 << 11)	   | /* RDQS 			*/ \
-	(1 << 10)	   | /* DQS# 			*/ \
-	(pr <<  7)	   | /* OCD prog 7=deflt,0=exit	*/ \
-		    /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
-	((ohm & 0x2) <<  5)| /* Rtt1			*/ \
-	(0 <<  3)	   | /* additive posted CAS#	*/ \
-	((ohm & 0x1) <<  2)| /* Rtt0			*/ \
-	(0 <<  0)	   | /* Output Drive Strength	*/ \
-	(0 <<  0))	     /* DLL Enable 0=Normal	*/
-
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	DDRCMD_EMR_OCD(7, 0)
-#define CONFIG_SYS_ELPIDA_OCD_EXIT	DDRCMD_EMR_OCD(0, 0)
-
-#define DDRCMD_MODE_REG(cas, wr) ( \
-	(1 << 24)    | /* MDDRC Command Request			*/ \
-	(0 << 16)    | /* MODE Reg BA[2:0] 			*/ \
-	((wr-1) << 9)| /* Write Recovery 			*/ \
-	(cas << 4)   | /* CAS 					*/ \
-	(0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved	*/ \
-	(2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8	*/
-
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	DDRCMD_MODE_REG(3, 3)
-#define CONFIG_SYS_ELPIDA_INIT_DEV_OP	DDRCMD_MODE_REG(4, 4)
-#define CONFIG_SYS_ELPIDA_RES_DLL	(DDRCMD_MODE_REG(4, 4) | (1 << 8))
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#undef CONFIG_BKUP_FLASH
-#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#ifdef CONFIG_BKUP_FLASH
-#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* max flash size in bytes */
-#else
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size in bytes */
-#endif
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND FLASH
- * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
- */
-#define CONFIG_CMD_NAND					/* enable NAND support */
-#define CONFIG_JFFS2_NAND				/* with JFFS2 on it */
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE            0x40000000
-
-#define CONFIG_SYS_MAX_NAND_DEVICE      2
-#define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH 1
-#define CONFIG_FSL_NFC_WRITE_SIZE 2048
-#define CONFIG_FSL_NFC_SPARE_SIZE 64
-#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-
-/*
- * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
- * window is 64KB
- */
-#define CONFIG_SYS_CPLD_BASE		0x82000000
-#define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
-#define CONFIG_SYS_CS2_START		CONFIG_SYS_CPLD_BASE
-#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_CPLD_SIZE
-
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-#define CONFIG_SYS_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
-#define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
-#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE		/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)		/* Reserve 512 kB for Mon */
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PATA_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN |		\
-			 CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_USB1_EN |		\
-			 CLOCK_SCCR2_USB2_EN)
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-/*
- * General PCI
- */
-#define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
-#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
-#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC	1
-#define CONFIG_PHY_ADDR		0x1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_FEC_AN_TIMEOUT	1
-#define CONFIG_HAS_ETH0
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
-
-/*
- * USB  Support
- */
-
-#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_EHCI_FSL			/* On a FSL platform	*/
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN		/* With big-endian regs	*/
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_IS_TDI
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x2000
-#ifdef CONFIG_BKUP_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
-#else
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
-#endif
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=fc000000.flash,nand0=mpc5121.nand"
-
-/*
- * NOR flash layout:
- *
- * FC000000 - FEABFFFF 42.75 MiB	User Data
- * FEAC0000 - FFABFFFF  16 MiB		Root File System
- * FFAC0000 - FFEBFFFF   4 MiB		Linux Kernel
- * FFEC0000 - FFEFFFFF 256 KiB		Device Tree
- * FFF00000 - FFFFFFFF   1 MiB		U-Boot (up to 512 KiB) and 2 x * env
- *
- * NAND flash layout: one big partition
- */
-#define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:43776k(user),"	\
-						"16m(rootfs),"		\
-						"4m(kernel),"		\
-						"256k(dtb),"		\
-						"1m(u-boot);"		\
-					"mpc5121.nand:-(data)"
-
-#if defined(CONFIG_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
-#define CONFIG_SUPPORT_VFAT
-
-#endif /* defined(CONFIG_IDE) */
-
-/*
- * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
- * to 0xFFFF, watchdog timeouts after about 64s. For details refer
- * to chapter 36 of the MPC5121e Reference Manual.
- */
-/* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
- /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
-#endif
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME		mpc5121ads
-#define CONFIG_BOOTFILE		"mpc5121ads/uImage"
-#define CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"
-
-#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
-
-#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=880000\0"						\
-	"ramdisk_addr_r=900000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFAC0000\0"					\
-	"fdt_addr=FFEC0000\0"						\
-	"ramdisk_addr=FEAC0000\0"					\
-	"ramdiskfile=mpc5121ads/uRamdisk\0"				\
-	"u-boot=mpc5121ads/u-boot.bin\0"				\
-	"bootfile=mpc5121ads/uImage\0"					\
-	"fdtfile=mpc5121ads/mpc5121ads.dtb\0"				\
-	"rootpath=/opt/eldk/ppc_6xx\n"					\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
-
-/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
-
-/* Interval between registers	*/
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#define ATA_BASE_ADDR			get_pata_base()
-
-/*
- * Control register bit definitions
- */
-#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
-#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
-#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
-#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
-#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
-#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
-#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
-#define FSL_ATA_CTRL_IORDY_EN		0x01000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/munices.h b/include/configs/munices.h
deleted file mode 100644
index ad2d69e..0000000
--- a/include/configs/munices.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
-#define CONFIG_MUNICES		1	/* ... on MUNICes board */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33333333 /* ... running at 33.333333MHz */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-		":$(hostname):$(netdev):off panic=5\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm $(kernel_addr)\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/munices/u-boot.bin\0"			\
-	"update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \
-	"erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0"	\
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define  CONFIG_SYS_IPBSPEED_133		/* define for 133MHz speed */
-#if defined(CONFIG_SYS_IPBSPEED_133)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCISPEED_66		/* define for 66MHz speed */
-#else
-#undef CONFIG_SYS_PCISPEED_66			/* for 33MHz speed */
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config  */
-
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE		0x01000000 /* 16 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	 /* max num of flash banks (= chip selects) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
-
-/*
- * Chip selects configuration
- */
-/* Boot Chipselect */
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x40000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
-#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x01
-#define CONFIG_MII		1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
-						no PCI */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_CMDLINE_EDITING  1
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_SOC                  "soc5200@f0000000"
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/o2d.h b/include/configs/o2d.h
deleted file mode 100644
index 4b36af6..0000000
--- a/include/configs/o2d.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/*
- * GPIO configuration:
- * CS1 SDRAM activate + no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x8000A004
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
-
-#define CONFIG_BOARD_NAME		"o2d"
-#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=fc060000\0"						\
-	"lintop=fc15ffff\0"						\
-	"rambot=fc160000\0"						\
-	"ramtop=fc55ffff\0"						\
-	"jffbot=fc560000\0"						\
-	"jfftop=fcffffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"progCram=tftp ${fileaddr} ${cramfsname};"			\
-		"erase ${rambot} ${ramtop};"				\
-		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
-	"flash_for_configs=22396\0"					\
-	"flash_mtd=run mtd_args addip addmem;"				\
-		"bootm ${kernel_addr}\0"				\
-	"mtd_args=setenv bootargs root=/dev/mtdblock3 "			\
-		"rw rootfstype=cramfs\0"				\
-	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"		\
-	"dhcp_boot=run dhcpcmd;run flash_mtd\0"				\
-	"hostname=IFM_SENSOR\0"						\
-	"netretry=once\0"						\
-	"autoload=no\0"							\
-	"sensorType=O2D222AG\0"
diff --git a/include/configs/o2d300.h b/include/configs/o2d300.h
deleted file mode 100644
index a8222d9..0000000
--- a/include/configs/o2d300.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/*
- * GPIO configuration:
- * CS1 SDRAM activate + no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG      0x8000A004
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
-
-/* Use redundant environment */
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-
-#define CONFIG_BOARD_NAME		"o2d300"
-#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
-#define BOARD_POST_CRC32_END		__stringify(0x02000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"autoload=no\0"							\
-	"dhcp_boot=run dhcpcmd;run flash_mtd\0"				\
-	"flash_mtd=run mtd_args addip addmem;"				\
-		"bootm ${kernel_addr}\0"				\
-	"mtd_args=setenv bootargs root=/dev/mtdblock4 "			\
-		"rw rootfstype=cramfs\0"				\
-	"linbot=fc080000\0"						\
-	"lintop=fc17ffff\0"						\
-	"rambot=fc180000\0"						\
-	"ramtop=fc57ffff\0"						\
-	"jffbot=fc580000\0"						\
-	"jfftop=fd39ffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0"	\
-	"halbot=fd3a0000\0"						\
-	"haltop=fdf9ffff\0"						\
-	"progHal=tftp 200000 ${halname};erase ${halbot} ${haltop};"	\
-		"cp.b ${fileaddr} ${halbot} ${filesize}\0"		\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"		\
-	"netretry=once\0"						\
-	"protcmd=protect on ${linbot} ${lintop};"			\
-		"protect on ${rambot} ${ramtop}\0"			\
-	"o2derror=def_env\0"						\
-	"sensorType=O2D300AA\0"
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
deleted file mode 100644
index 1b4200b..0000000
--- a/include/configs/o2dnt-common.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- *  Common configuration options for ifm camera boards
- *
- * (C) Copyright 2005
- * Sebastien Cazaux, ifm electronic gmbh
- *
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __O2D_CONFIG_H
-#define __O2D_CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC5200
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* running at 33.000000MHz */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-/* log base 2 of the above value */
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-/*
-#define CONFIG_POST	(CONFIG_SYS_POST_MEMORY | \
-			 CONFIG_SYS_POST_I2C)
-*/
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-/* Partitions */
-
-#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
-
-#define CONFIG_SYS_ALT_MEMTEST	/* Much more complex memory test */
-
-/*
- * Supported commands
- */
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#endif
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
-/* Boot low with 16 or 32 MB Flash */
-#define CONFIG_SYS_LOWBOOT	1
-#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
-#error "CONFIG_SYS_TEXT_BASE value is invalid"
-#endif
-
-
-#define CONFIG_PREBOOT	"run master"
-
-#undef	CONFIG_BOOTARGS
-
-#if !defined(CONSOLE_DEV)
-#define CONSOLE_DEV	"ttyPSC1"
-#endif
-
-/*
- * Default environment for booting old and new kernel versions
- */
-#define CONFIG_IFM_DEFAULT_ENV_OLD					\
-	"flash_self_old=run ramargs addip addmem;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs_old=run nfsargs addip addmem;"			\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
-		"run nfsargs addip addmem;"				\
-		"bootm ${kernel_addr_r}\0"
-
-#define CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"fdt_addr_r=900000\0"						\
-	"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0"	\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-
-#define	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	"IOpin=0x64\0"							\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addmem=setenv bootargs ${bootargs} ${memlimit}\0"		\
-	"addmisc=sete bootargs ${bootargs} ${miscargs}\0"		\
-	"addtty=sete bootargs ${bootargs} console="			\
-		CONSOLE_DEV ",${baudrate}\0"			\
-	"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"	\
-	"kernel_addr_r=600000\0"					\
-	"initrd_high=0x03e00000\0"					\
-	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"			\
-	"memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
-	"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
-		"cp.b ${fileaddr} ${linbot} ${filesize}\0"		\
-	"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
-	"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};"	\
-		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
-	"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0"	\
-	"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};"	\
-		"cp.b ${fileaddr} ${jffbot} ${filesize}\0"		\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"uboname=" CONFIG_BOARD_NAME					\
-		"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0"		\
-	"progubo=tftp 200000 ${uboname};"				\
-		"protect off ${ubobot} ${ubotop};"			\
-		"erase ${ubobot} ${ubotop};"				\
-		"cp.b ${fileaddr} ${ubobot} ${filesize}\0"		\
-	"unlock=yes\0"							\
-	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"	\
-		"setenv bootdelay 1;"					\
-		"crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" "		\
-			BOARD_POST_CRC32_END";"				\
-		"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
-
-#define CONFIG_BOOTCOMMAND	"run post"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
-#endif
-
-/*
- * There is no write delay with FRAM, write operations are performed at bus
- * speed. Thus, no status polling or write delay is needed.
- */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER		1
-#define CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Write Timeout (in ms) */
-/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
-/* "Real" (hardware) sectors protection */
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-/* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10) /* 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial map for Linux */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR			0x00
-#define CONFIG_RESET_PHY_R
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPIO_DATADIR		0x00000064 /* PSC1_2, PSC2_1,2 output */
-#define CONFIG_SYS_GPIO_OPENDRAIN	0x00000000 /* No open drain */
-#define CONFIG_SYS_GPIO_DATAVALUE	0x00000000 /* PSC1_1 to 1, rest to 0 */
-#define CONFIG_SYS_GPIO_ENABLE		0x00000064 /* PSC1_2, PSC2_1,2 enable */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_CMDLINE_EDITING
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x100000
-
-/* decrementer freq: 1 ms ticks */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333333
-
-/*
- * DT support
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-
-#endif /* __O2D_CONFIG_H */
diff --git a/include/configs/o2dnt2.h b/include/configs/o2dnt2.h
deleted file mode 100644
index 00a8d96..0000000
--- a/include/configs/o2dnt2.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/*
- * GPIO configuration:
- * CS1 SDRAM activate + no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x8000A004
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
-
-#define CONFIG_BOARD_NAME		"o2dnt2"
-#define CONFIG_BOARD_BOOTCMD		"run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=fc060000\0"						\
-	"lintop=fc15ffff\0"						\
-	"rambot=fc160000\0"						\
-	"ramtop=fc55ffff\0"						\
-	"jffbot=fc560000\0"						\
-	"jfftop=fce5ffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
-	"calbot=fce60000\0"						\
-	"caltop=fcffffff\0"						\
-	"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};"	\
-		"cp.b ${fileaddr} ${calbot} ${filesize}\0"		\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/include/configs/o2i.h b/include/configs/o2i.h
deleted file mode 100644
index c0fceda..0000000
--- a/include/configs/o2i.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFF000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xff000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000      /* maximum 16MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/* GPIO configuration */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002006	/* no CAN */
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00087801
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM  */
-
-#define CONFIG_BOARD_NAME		"o2i"
-#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=ff060000\0"						\
-	"lintop=ff15ffff\0"						\
-	"rambot=ff160000\0"						\
-	"ramtop=ff55ffff\0"						\
-	"jffbot=ff560000\0"						\
-	"jfftop=ffebffff\0"						\
-	"kernel_addr=0xff060000\0"					\
-	"ramdisk_addr=0xff160000\0"					\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=ff03ffff\0"						\
-	"autoload=no\0"							\
-	"dhcp_boot=run dhcpcmd; run flash_mtd\0"			\
-	"hostname=IFM_SENSOR\0"						\
-	"flash_mtd=run mtd_args addip addmem;bootm ${kernel_addr}\0"	\
-	"mtd_args=setenv bootargs root=/dev/mtdblock3 "			\
-		"rw rootfstype=cramfs\0"				\
-	"sensorType=O2I100AA\0"						\
-	"netretry=once\0"						\
-	"master=mw f0000b00 0x00052006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/include/configs/o2mnt.h b/include/configs/o2mnt.h
deleted file mode 100644
index eb63cb0..0000000
--- a/include/configs/o2mnt.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFF000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xff000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000      /* maximum 16MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/* GPIO configuration */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002004	/* no CAN */
-
-/* Other board specific configs */
-#define CONFIG_NETCONSOLE
-
-#define CONFIG_SYS_BOOTCS_CFG		0x00087801
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM  */
-
-#define CONFIG_BOARD_NAME		"o2mnt"
-#define CONFIG_BOARD_BOOTCMD		"${newcmd}"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#ifndef CONFIG_IFM_SENSOR_TYPE
-#define CONFIG_IFM_SENSOR_TYPE		"O2M110"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=ff060000\0"						\
-	"lintop=ff25ffff\0"						\
-	"rambot=ff260000\0"						\
-	"ramtop=ffc5ffff\0"						\
-	"jffbot=ffc60000\0"						\
-	"jfftop=ffffffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=ff03ffff\0"						\
-	"kernel_addr=0xff060000\0"					\
-	"ramdisk_addr=0xff260000\0"					\
-	"newcmd=run scrprot;run flash_ext2\0"				\
-	"scrprot=protect on ${linbot} ${lintop};protect on ${rambot} "	\
-		"${ramtop}\0"						\
-	"flash_ext2=run ext2args addip addmem;bootm ${kernel_addr}\0"	\
-	"ext2args=setenv bootargs root=/dev/mtdblock3 ro "		\
-		"rootfstype=ext2\0"					\
-	"pwm=mw f0000674 0x10006;mw f0000678 0x30000;"			\
-		"mw f0000678 0x30001;mw f0000670 0x3\0"			\
-	"master=mw f0000b00 0x00052006;mw f0000b0c $(IOpin);"		\
-		"mw f0000b04 $(IOpin);mw f0000b10 0x24;run pwm\0"	\
-	"sensortyp="CONFIG_IFM_SENSOR_TYPE"\0"				\
-	"srelease=0.00\0"
diff --git a/include/configs/o3dnt.h b/include/configs/o3dnt.h
deleted file mode 100644
index f0fceda..0000000
--- a/include/configs/o3dnt.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/* Additional commands */
-#define CONFIG_CMD_REGINFO
-
-/*
- * GPIO configuration:
- * no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x0000A000
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM */
-
-#define CONFIG_BOARD_NAME		"o3dnt"
-#define CONFIG_BOARD_BOOTCMD		"run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=fc060000\0"						\
-	"lintop=fc15ffff\0"						\
-	"rambot=fc160000\0"						\
-	"ramtop=fc55ffff\0"						\
-	"jffbot=fc560000\0"						\
-	"jfftop=fce5ffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
-	"calbot=fce60000\0"						\
-	"caltop=fcffffff\0"						\
-	"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};"	\
-		"cp.b ${fileaddr} ${calbot} ${filesize}\0"		\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"master=mw f0000b00 0x0005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
deleted file mode 100644
index 500277f..0000000
--- a/include/configs/pcm030.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messatechnik GmbH
- *
- * (C) Copyright 2009
- * Jon Smirl <jonsmirl@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_BOARDINFO	 "phyCORE-MPC5200B-tiny"
-
-/*-----------------------------------------------------------------------------
-High Level Configuration Options
-(easy to change)
------------------------------------------------------------------------------*/
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
-#define CONFIG_PHYCORE_MPC5200B_TINY 1	/* phyCORE-MPC5200B -> */
-					/* FEC configuration and IDE */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000	boot high (standard configuration)
- * 0xFF000000	boot low
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
-
-/*-----------------------------------------------------------------------------
-Serial console configuration
------------------------------------------------------------------------------*/
-#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 -> */
-					/*define gps port conf. */
-					/* register later on to */
-					/*enable UART function! */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)	/* Boot low */
-#define CONFIG_SYS_LOWBOOT 1
-#endif
-/* RAMBOOT will be defined automatically in memory section */
-
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT 		"nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT   	"mtdparts=physmap-flash.0:256k(ubootl)," \
-	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
-		"mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"uimage=uImage-pcm030\0"					\
-	"oftree=oftree-pcm030.dtb\0"					\
-	"jffs2=root-pcm030.jffs2\0" 					\
-	"uboot=u-boot-pcm030.bin\0"					\
-	"bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)"	\
-		" $(mtdparts) rw\0" 					\
-	"bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2"	\
-		" rootfstype=jffs2\0" 					\
-	"bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs"		\
-		" ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::"	\
-		"$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
-	"bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
-		" tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0"	\
-	"bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - "	\
-		"0xfff40000\0" 						\
-		" cp.b 0x400000 0xff040000 $(filesize)\0" 		\
-	"prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
-		"cp.b 0x400000 0xff200000 $(filesize)\0" 		\
-	"prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
-		" cp.b 0x400000 0xfff40000 $(filesize)\0" 		\
-	"update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
-		" cp.b 0x400000 0xFFF00000 $(filesize)\0"		\
-	"unlock=yes\0"							\
-	""
-
-#define CONFIG_BOOTCOMMAND		"run bcmd_flash"
-
-/*--------------------------------------------------------------------------
-IPB Bus clocking configuration.
- ---------------------------------------------------------------------------*/
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
-
-/*-------------------------------------------------------------------------
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- * -----------------------------------------------------------------------*/
-#define CONFIG_PCI_SCAN_SHOW		1
-#define CONFIG_PCI_MEM_BUS		0x40000000
-#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE		0x10000000
-#define CONFIG_PCI_IO_BUS		0x50000000
-#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE		0x01000000
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-/*---------------------------------------------------------------------------
- Flash configuration
----------------------------------------------------------------------------*/
-
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-						/* (= chip selects) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Use also hardware protection. This seems required, as the BDI uses
- * hardware protection. Without this, U-Boot can't work with this sectors,
- * as its protection is software only by default
- */
-#define CONFIG_SYS_FLASH_PROTECTION	1
-
-/*---------------------------------------------------------------------------
- Environment settings
----------------------------------------------------------------------------*/
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OFFSET	0x00	/* environment starts at the */
-					/*beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		2048
-
-#define CONFIG_ENV_OVERWRITE	1
-
-/*-----------------------------------------------------------------------------
-  Memory map
------------------------------------------------------------------------------*/
-#define CONFIG_SYS_MBAR	0xF0000000	/* MBAR has to be switched by other */
-					/* bootloader or debugger config */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used */
-								/* area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#	define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------------
- Ethernet configuration
------------------------------------------------------------------------------*/
-#define CONFIG_MPC5xxx_FEC		1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR			0x01
-
-/*---------------------------------------------------------------------------
- GPIO configuration
- ---------------------------------------------------------------------------*/
-
-/* GPIO port configuration
- *
- * Pin mapping:
- *
- * [29:31] = 01x
- * PSC1_0 -> AC97 SDATA out
- * PSC1_1 -> AC97 SDTA in
- * PSC1_2 -> AC97 SYNC out
- * PSC1_3 -> AC97 bitclock out
- * PSC1_4 -> AC97 reset out
- *
- * [25:27] = 001
- * PSC2_0 -> CAN 1 Tx out
- * PSC2_1 -> CAN 1 Rx in
- * PSC2_2 -> CAN 2 Tx out
- * PSC2_3 -> CAN 2 Rx in
- * PSC2_4 -> GPIO (claimed for ATA reset, active low)
- *
- *
- * [20:23] = 1100
- * PSC3_0 -> UART Tx out
- * PSC3_1 -> UART Rx in
- * PSC3_2 -> UART RTS (in/out FIXME)
- * PSC3_3 -> UART CTS (in/out FIXME)
- * PSC3_4 -> LocalPlus Bus CS6 \
- * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
- * PSC3_6 -> dedicated SPI MOSI out (master case)
- * PSC3_7 -> dedicated SPI MISO in (master case)
- * PSC3_8 -> dedicated SPI SS out (master case)
- * PSC3_9 -> dedicated SPI CLK out (master case)
- *
- * [18:19] = 01
- * USB_0 -> USB OE out
- * USB_1 -> USB Tx- out
- * USB_2 -> USB Tx+ out
- * USB_3 -> USB RxD (in/out FIXME)
- * USB_4 -> USB Rx+ in
- * USB_5 -> USB Rx- in
- * USB_6 -> USB PortPower out
- * USB_7 -> USB speed out
- * USB_8 -> USB suspend (in/out FIXME)
- * USB_9 -> USB overcurrent in
- *
- * [17] = 0
- * USB differential mode
- *
- * [16] = 0
- * PCI enabled
- *
- * [12:15] = 0101
- * ETH_0 -> ETH Txen
- * ETH_1 -> ETH TxD0
- * ETH_2 -> ETH TxD1
- * ETH_3 -> ETH TxD2
- * ETH_4 -> ETH TxD3
- * ETH_5 -> ETH Txerr
- * ETH_6 -> ETH MDC
- * ETH_7 -> ETH MDIO
- * ETH_8 -> ETH RxDv
- * ETH_9 -> ETH RxCLK
- * ETH_10 -> ETH Collision
- * ETH_11 -> ETH TxD
- * ETH_12 -> ETH RxD0
- * ETH_13 -> ETH RxD1
- * ETH_14 -> ETH RxD2
- * ETH_15 -> ETH RxD3
- * ETH_16 -> ETH Rxerr
- * ETH_17 -> ETH CRS
- *
- * [9:11] = 101
- * PSC6_0 -> UART RxD in
- * PSC6_1 -> UART CTS (in/out FIXME)
- * PSC6_2 -> UART TxD out
- * PSC6_3 -> UART RTS (in/out FIXME)
- *
- * [2:3/6:7] = 00/11
- * TMR_0 -> ATA_CS0 out
- * TMR_1 -> ATA_CS1 out
- * TMR_2 -> GPIO
- * TMR_3 -> GPIO
- * TMR_4 -> GPIO
- * TMR_5 -> GPIO
- * TMR_6 -> GPIO
- * TMR_7 -> GPIO
- * I2C_0 -> I2C 1 Clock out
- * I2C_1 -> I2C 1 IO in/out
- * I2C_2 -> I2C 2 Clock out
- * I2C_3 -> I2C 2 IO in/out
- *
- * [4] = 1
- * PSC3_5 is used as CS7
- *
- * [5] = 1
- * PSC3_4 is used as CS6
- *
- * [1] = 0
- * gpio_wkup_7 is GPIO
- *
- * [0] = 0
- * gpio_wkup_6 is GPIO
- *
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x0f551c12
-
-/*-----------------------------------------------------------------------------
- Miscellaneous configurable options
--------------------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP	/* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-							/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-/*-----------------------------------------------------------------------------
- Various low-level settings
------------------------------------------------------------------------------*/
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-/* no burst access on the LPB */
-#define CONFIG_SYS_CS_BURST		0x00000000
-/* one deadcycle for the 33MHz statemachine */
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333331
-/* one additional waitstate for the 33MHz statemachine */
-#define CONFIG_SYS_BOOTCS_CFG		0x0001dd00
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_RESET_ADDRESS 	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK		0x0001BBBB
-#define CONFIG_USB_CONFIG		0x00001000
-
-/*---------------------------------------------------------------------------
- IDE/ATA stuff Supports IDE harddisk
-----------------------------------------------------------------------------*/
-
-#undef	CONFIG_IDE_LED		/* LED for ide not supported */
-#define CONFIG_SYS_ATA_CS_ON_TIMER01
-#define	CONFIG_IDE_RESET 1	/* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE		4
-#define CONFIG_ATAPI			1
-
-/* USB */
-#define CONFIG_USB_OHCI
-
-/* pass open firmware flat tree */
-#define OF_CPU				"PowerPC,5200@0"
-#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
-#define OF_SOC				"soc5200@f0000000"
-#define OF_STDOUT_PATH			"/soc5200@f0000000/serial@2400"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
deleted file mode 100644
index 676d55f..0000000
--- a/include/configs/pdm360ng.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * (C) Copyright 2009-2010
- * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * pdm360ng board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PDM360NG 1
-
-/*
- * Memory map for the PDM360NG board:
- *
- * 0x0000_0000 - 0x1FFF_FFFF	DDR RAM (512 MB)
- * 0x2000_0000 - 0x3FFF_FFFF	reserved (DDR RAM (512 MB)
- * 0x5000_0000 - 0x5001_FFFF	SRAM (128 KB)
- * 0x5004_0000 - 0x5005_FFFF	MRAM (CS2) (128 KB)
- * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
- * 0xF000_0000 - 0xF7FF_FFFF	NOR FLASH (CS0) (128 MB)
- * 0xF800_0000 - 0xFFFF_FFFF	NOR FLASH (CS1) (128 MB) optional
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
-
-#define	CONFIG_SYS_TEXT_BASE	0xF0000000
-
-/* Used for silent command in environment */
-#define CONFIG_SYS_DEVICE_NULLDEV
-
-/* Video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_RLE8
-#endif
-
-#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR			0x80000000
-#define CONFIG_SYS_DIU_ADDR		((CONFIG_SYS_IMMR) + 0x2100)
-
-/*
- * DDR Setup
- */
-
-/* DDR is system memory */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x40000000
-
-/* DDR pin mux and slew rate */
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000012
-
-/* Manually set all parameters as there's no SPD etc. */
-/*
- * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Read Delay:		3
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Enabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xEA804A40
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x030C3D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34310864
-
-/*
- * Alternative 1: small RAM (128 MB) configuration
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1	0xE8604A40
-#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1	0x030C3D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1	0x3CEC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1	0x33310863
-
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_DDRCMD_EM2		0x01020000  /* EMR2 */
-#define CONFIG_SYS_DDRCMD_EM3		0x01030000  /* EMR3 */
-/* EMR with 150 ohm ODT todo: verify */
-#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010040
-#define CONFIG_SYS_DDRCMD_RES_DLL	0x01000100
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-/* EMR with 150 ohm ODT todo: verify */
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	0x010107C0
-/* EMR new command with 150 ohm ODT todo: verify */
-#define CONFIG_SYS_DDRCMD_OCD_EXIT	0x01010440
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-#define CONFIG_SYS_FLASH_BASE		0xF0000000 /* start of FLASH-Bank0 */
-#define CONFIG_SYS_FLASH_SIZE		0x08000000 /* max size of a Bank */
-/* start of FLASH-Bank1 */
-#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_FLASH_BASE + \
-					 CONFIG_SYS_FLASH_SIZE)
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST \
-	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
-
-#define CONFIG_SYS_SRAM_BASE		0x50000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* ALE active low, data size 4 bytes */
-#define CONFIG_SYS_CS0_CFG		0x05059350
-/* ALE active low, data size 4 bytes */
-#define CONFIG_SYS_CS1_CFG		0x05059350
-
-#define CONFIG_SYS_MRAM_BASE		0x50040000
-#define CONFIG_SYS_MRAM_SIZE		0x00020000
-#define CONFIG_SYS_CS2_START		CONFIG_SYS_MRAM_BASE
-#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_MRAM_SIZE
-
-/* ALE active low, data size 4 bytes */
-#define CONFIG_SYS_CS2_CFG		0x05059110
-
-/* alt. CS timing for CS0, CS1, CS2 */
-#define CONFIG_SYS_CS_ALETIMING		0x00000007
-
-/*
- * NAND FLASH
- */
-#define CONFIG_CMD_NAND			/* enable NAND support */
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE            0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
-#define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH 1
-#define CONFIG_FSL_NFC_WRITE_SIZE 2048
-#define CONFIG_FSL_NFC_SPARE_SIZE 64
-#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-
-/*
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=f0000000.flash,nor1=f8000000.flash," \
-						"nand0=MPC5121 NAND"
-
-/*
- * Flash layout
- */
-#define MTDPARTS_DEFAULT	"mtdparts=f0000000.flash:512k(u-boot),"	\
-						"256k(environment1),"	\
-						"256k(environment2),"	\
-						"256k(splash-factory)," \
-						"2m(FIT: recovery),"	\
-						"4608k(fs-recovery),"   \
-						"256k(splash-customer),"\
-						"5m(FIT: kernel+dtb),"	\
-						"64m(rootfs squash)ro,"	\
-						"51m(userfs ubi);"	\
-					"f8000000.flash:-(unused);"	\
-					"MPC5121 NAND:1024m(extended-userfs)"
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* 512 kB for monitor */
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* for malloc */
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	6	/* console is on PSC6 */
-#if CONFIG_PSC_CONSOLE != 6
-#error CONFIG_PSC_CONSOLE must be 6
-#endif
-
-#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC6_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC6_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC6_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC6_RX_ADDR
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
-
-/*
- * Used PSC UART devices
- */
-#define CONFIG_SYS_PSC1
-#define CONFIG_SYS_PSC4
-#define CONFIG_SYS_PSC6
-
-/*
- * Co-processor communication parameters
- */
-#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY	5000
-#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE	38400
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Enabled only to delete "ethaddr" before testing
- * "ethaddr" setting from EEPROM
- */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC	1
-#define CONFIG_PHY_ADDR		0x1F
-#define CONFIG_MII		1	/* MII PHY management	*/
-#define CONFIG_FEC_AN_TIMEOUT	1
-#define CONFIG_HAS_ETH0
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
-				 CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x40000		/* one sector (256K) for env */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-#define CONFIG_CMD_REGINFO
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Max number of command args */
-#define CONFIG_SYS_MAXARGS	16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-/* Decrementer freq: 1ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-/* log base 2 of the above value */
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/* POST support */
-#define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
-
-/*
- * Environment Configuration
- */
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME		pdm360ng
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		400000
-
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo PDM360NG SAMPLE;" \
-	"echo"
-
-#define CONFIG_BOOTCOMMAND	"run env_cont"
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11600"
-
-/*
- * Include common options for all mpc5121 boards
- */
-#include "mpc5121-common.h"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
deleted file mode 100644
index c103215..0000000
--- a/include/configs/v38b.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
- * wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
-#define CONFIG_V38B			1	/* ...on V38B board */
-
-#define	CONFIG_SYS_TEXT_BASE		0xFF000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */
-
-#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
-#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */
-
-#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */
-
-#define CONFIG_NETCONSOLE		1
-
-#define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_XLB_PIPELINING		1	/* gives better performance */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * DDR
- */
-#define SDRAM_DDR		1	/* is DDR */
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE		0x018D0000
-#define SDRAM_EMODE		0x40090000
-#define SDRAM_CONTROL		0x704f0f00
-#define SDRAM_CONFIG1		0x73722930
-#define SDRAM_CONFIG2		0x47770000
-#define SDRAM_TAPDELAY		0x10000000
-
-/*
- * PCI - no support
- */
-
-/*
- * USB
- */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * Boot low with 16 MB Flash
- */
-#define CONFIG_SYS_LOWBOOT		1
-#define CONFIG_SYS_LOWBOOT16		1
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"bootcmd=run net_nfs\0"						\
-	"bootdelay=3\0"							\
-	"baudrate=115200\0"						\
-	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
-		"filesystem over NFS; echo\0"				\
-	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"		\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath) wdt=off\0"		\
-	"hostname=v38b\0"						\
-	"ethact=FEC\0"							\
-	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
-	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "	\
-		"cp.b 200000 ff000000 $(filesize);"			\
-		"prot on ff000000 ff03ffff\0"				\
-	"load=tftp 200000 $(u-boot)\0"					\
-	"netmask=255.255.0.0\0"						\
-	"ipaddr=192.168.160.18\0"					\
-	"serverip=192.168.1.1\0"					\
-	"bootfile=/tftpboot/v38b/uImage\0"				\
-	"u-boot=/tftpboot/v38b/u-boot.bin\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
-
-/*
- * Flash configuration - use CFI driver
- */
-#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1		/* Use the common driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max num of flash banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_SIZE		0x01000000	/* 16 MiB */
-#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII		1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x90001404
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*
- * IDE/ATA (supports IDE harddisk)
- */
-#undef CONFIG_IDE_LED			/* LED for ide not supported */
-
-#define CONFIG_IDE_RESET		/* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */
-
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)	/* normal register accesses offset */
-
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */
-
-#define CONFIG_SYS_ATA_STRIDE		4		/* Interval between registers */
-
-/*
- * Status LED
- */
-
-#define CONFIG_SYS_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-	do { \
-		*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
-	} while(0)
-
-#define __led_set(_msk, _st) \
-	do { \
-		if ((_st)) \
-			*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
-		else \
-			*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
-	} while(0)
-
-#define __led_init(_msk, st) \
-	do { \
-		*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
-	} while(0)
-#endif /* __ASSEMBLY__ */
-
-#endif /* __CONFIG_H */
diff --git a/include/keyboard.h b/include/keyboard.h
index 5cbd9f8..9b51e20 100644
--- a/include/keyboard.h
+++ b/include/keyboard.h
@@ -98,7 +98,7 @@
 extern void pckbd_leds(unsigned char leds);
 #endif /* !CONFIG_DM_KEYBOARD */
 
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
+#if defined(CONFIG_ARCH_MPC8540) || \
 		defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
 int ps2ser_check(void);
 #endif
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
deleted file mode 100644
index 10daf09..0000000
--- a/include/mpc5xxx.h
+++ /dev/null
@@ -1,893 +0,0 @@
-/*
- * include/asm-ppc/mpc5xxx.h
- *
- * Prototypes, etc. for the Motorola MPC5xxx
- * embedded cpu chips
- *
- * 2003 (c) MontaVista, Software, Inc.
- * Author: Dale Farnsworth <dfarnsworth@mvista.com>
- *
- * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASMPPC_MPC5XXX_H
-#define __ASMPPC_MPC5XXX_H
-
-#include <asm/types.h>
-
-/* Processor name */
-#define CPU_ID_STR	"MPC5200"
-
-/* Exception offsets (PowerPC standard) */
-#define EXC_OFF_SYS_RESET	0x0100
-#define _START_OFFSET		EXC_OFF_SYS_RESET
-
-/* useful macros for manipulating CSx_START/STOP */
-#define START_REG(start)	((start) >> 16)
-#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
-
-/* Internal memory map */
-
-#define MPC5XXX_CS0_START	(CONFIG_SYS_MBAR + 0x0004)
-#define MPC5XXX_CS0_STOP	(CONFIG_SYS_MBAR + 0x0008)
-#define MPC5XXX_CS1_START	(CONFIG_SYS_MBAR + 0x000c)
-#define MPC5XXX_CS1_STOP	(CONFIG_SYS_MBAR + 0x0010)
-#define MPC5XXX_CS2_START	(CONFIG_SYS_MBAR + 0x0014)
-#define MPC5XXX_CS2_STOP	(CONFIG_SYS_MBAR + 0x0018)
-#define MPC5XXX_CS3_START	(CONFIG_SYS_MBAR + 0x001c)
-#define MPC5XXX_CS3_STOP	(CONFIG_SYS_MBAR + 0x0020)
-#define MPC5XXX_CS4_START	(CONFIG_SYS_MBAR + 0x0024)
-#define MPC5XXX_CS4_STOP	(CONFIG_SYS_MBAR + 0x0028)
-#define MPC5XXX_CS5_START	(CONFIG_SYS_MBAR + 0x002c)
-#define MPC5XXX_CS5_STOP	(CONFIG_SYS_MBAR + 0x0030)
-#define MPC5XXX_BOOTCS_START	(CONFIG_SYS_MBAR + 0x004c)
-#define MPC5XXX_BOOTCS_STOP	(CONFIG_SYS_MBAR + 0x0050)
-#define MPC5XXX_ADDECR		(CONFIG_SYS_MBAR + 0x0054)
-
-#define MPC5XXX_CS6_START	(CONFIG_SYS_MBAR + 0x0058)
-#define MPC5XXX_CS6_STOP	(CONFIG_SYS_MBAR + 0x005c)
-#define MPC5XXX_CS7_START	(CONFIG_SYS_MBAR + 0x0060)
-#define MPC5XXX_CS7_STOP	(CONFIG_SYS_MBAR + 0x0064)
-#define MPC5XXX_SDRAM_CS0CFG	(CONFIG_SYS_MBAR + 0x0034)
-#define MPC5XXX_SDRAM_CS1CFG	(CONFIG_SYS_MBAR + 0x0038)
-
-#define MPC5XXX_SDRAM		(CONFIG_SYS_MBAR + 0x0100)
-#define MPC5XXX_CDM		(CONFIG_SYS_MBAR + 0x0200)
-#define MPC5XXX_LPB		(CONFIG_SYS_MBAR + 0x0300)
-#define MPC5XXX_ICTL		(CONFIG_SYS_MBAR + 0x0500)
-#define MPC5XXX_GPT		(CONFIG_SYS_MBAR + 0x0600)
-#define MPC5XXX_GPIO		(CONFIG_SYS_MBAR + 0x0b00)
-#define MPC5XXX_WU_GPIO         (CONFIG_SYS_MBAR + 0x0c00)
-#define MPC5XXX_PCI		(CONFIG_SYS_MBAR + 0x0d00)
-#define MPC5XXX_SPI		(CONFIG_SYS_MBAR + 0x0f00)
-#define MPC5XXX_USB		(CONFIG_SYS_MBAR + 0x1000)
-#define MPC5XXX_SDMA		(CONFIG_SYS_MBAR + 0x1200)
-#define MPC5XXX_XLBARB		(CONFIG_SYS_MBAR + 0x1f00)
-
-#define	MPC5XXX_PSC1		(CONFIG_SYS_MBAR + 0x2000)
-#define	MPC5XXX_PSC2		(CONFIG_SYS_MBAR + 0x2200)
-#define	MPC5XXX_PSC3		(CONFIG_SYS_MBAR + 0x2400)
-#define	MPC5XXX_PSC4		(CONFIG_SYS_MBAR + 0x2600)
-#define	MPC5XXX_PSC5		(CONFIG_SYS_MBAR + 0x2800)
-#define	MPC5XXX_PSC6		(CONFIG_SYS_MBAR + 0x2c00)
-
-#define	MPC5XXX_FEC		(CONFIG_SYS_MBAR + 0x3000)
-#define MPC5XXX_ATA             (CONFIG_SYS_MBAR + 0x3A00)
-
-#define MPC5XXX_I2C1		(CONFIG_SYS_MBAR + 0x3D00)
-#define MPC5XXX_I2C2		(CONFIG_SYS_MBAR + 0x3D40)
-
-#define MPC5XXX_SRAM		(CONFIG_SYS_MBAR + 0x8000)
-#define MPC5XXX_SRAM_SIZE	(16*1024)
-
-/* SDRAM Controller */
-#define MPC5XXX_SDRAM_MODE	(MPC5XXX_SDRAM + 0x0000)
-#define MPC5XXX_SDRAM_CTRL	(MPC5XXX_SDRAM + 0x0004)
-#define MPC5XXX_SDRAM_CONFIG1	(MPC5XXX_SDRAM + 0x0008)
-#define MPC5XXX_SDRAM_CONFIG2	(MPC5XXX_SDRAM + 0x000c)
-#define MPC5XXX_SDRAM_SDELAY	(MPC5XXX_SDRAM + 0x0090)
-
-/* Clock Distribution Module */
-#define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
-#define MPC5XXX_CDM_PORCFG	(MPC5XXX_CDM + 0x0004)
-#define MPC5XXX_CDM_BRDCRMB  	(MPC5XXX_CDM + 0x0008)
-#define MPC5XXX_CDM_CFG		(MPC5XXX_CDM + 0x000c)
-#define MPC5XXX_CDM_48_FDC	(MPC5XXX_CDM + 0x0010)
-#define MPC5XXX_CDM_CLK_ENA	(MPC5XXX_CDM + 0x0014)
-#define MPC5XXX_CDM_SRESET	(MPC5XXX_CDM + 0x0020)
-
-/* Local Plus Bus interface */
-#define MPC5XXX_CS0_CFG		(MPC5XXX_LPB + 0x0000)
-#define MPC5XXX_CS1_CFG		(MPC5XXX_LPB + 0x0004)
-#define MPC5XXX_CS2_CFG		(MPC5XXX_LPB + 0x0008)
-#define MPC5XXX_CS3_CFG		(MPC5XXX_LPB + 0x000c)
-#define MPC5XXX_CS4_CFG		(MPC5XXX_LPB + 0x0010)
-#define MPC5XXX_CS5_CFG		(MPC5XXX_LPB + 0x0014)
-#define MPC5XXX_BOOTCS_CFG	MPC5XXX_CS0_CFG
-#define MPC5XXX_CS_CTRL		(MPC5XXX_LPB + 0x0018)
-#define MPC5XXX_CS_STATUS	(MPC5XXX_LPB + 0x001c)
-#define MPC5XXX_CS6_CFG		(MPC5XXX_LPB + 0x0020)
-#define MPC5XXX_CS7_CFG		(MPC5XXX_LPB + 0x0024)
-#define MPC5XXX_CS_BURST	(MPC5XXX_LPB + 0x0028)
-#define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
-
-/* XLB Arbiter registers */
-#define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)
-#define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)
-#define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)
-
-/* GPIO registers */
-#define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
-
-/* Standard GPIO registers (simple, output only and simple interrupt */
-#define MPC5XXX_GPIO_ENABLE     (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_GPIO_ODE        (MPC5XXX_GPIO + 0x0008)
-#define MPC5XXX_GPIO_DIR        (MPC5XXX_GPIO + 0x000c)
-#define MPC5XXX_GPIO_DATA_O     (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_GPIO_DATA_I     (MPC5XXX_GPIO + 0x0014)
-#define MPC5XXX_GPIO_OO_ENABLE  (MPC5XXX_GPIO + 0x0018)
-#define MPC5XXX_GPIO_OO_DATA    (MPC5XXX_GPIO + 0x001C)
-#define MPC5XXX_GPIO_SI_ENABLE  (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_GPIO_SI_ODE     (MPC5XXX_GPIO + 0x0024)
-#define MPC5XXX_GPIO_SI_DIR     (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_GPIO_SI_DATA    (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_GPIO_SI_IEN     (MPC5XXX_GPIO + 0x0030)
-#define MPC5XXX_GPIO_SI_ITYPE   (MPC5XXX_GPIO + 0x0034)
-#define MPC5XXX_GPIO_SI_MEN     (MPC5XXX_GPIO + 0x0038)
-#define MPC5XXX_GPIO_SI_STATUS  (MPC5XXX_GPIO + 0x003C)
-
-/* WakeUp GPIO registers */
-#define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
-#define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
-#define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
-#define MPC5XXX_WU_GPIO_DATA_O  (MPC5XXX_WU_GPIO + 0x000c)
-#define MPC5XXX_WU_GPIO_DATA_I  (MPC5XXX_WU_GPIO + 0x0020)
-
-/* GPIO pins, for Rev.B chip */
-#define GPIO_WKUP_7		0x80000000UL
-#define GPIO_PSC6_0		0x10000000UL
-#define GPIO_PSC3_9		0x04000000UL
-#define GPIO_PSC1_4		0x01000000UL
-#define GPIO_PSC2_4		0x02000000UL
-
-#define MPC5XXX_GPIO_SIMPLE_PSC6_3   0x20000000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC6_2   0x10000000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_7   0x00002000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_6   0x00001000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_3   0x00000800UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_2   0x00000400UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_1   0x00000200UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_0   0x00000100UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_3   0x00000080UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_2   0x00000040UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_1   0x00000020UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_0   0x00000010UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_3   0x00000008UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_2   0x00000004UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_1   0x00000002UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_0   0x00000001UL
-
-#define MPC5XXX_GPIO_SINT_ETH_16     0x80
-#define MPC5XXX_GPIO_SINT_ETH_15     0x40
-#define MPC5XXX_GPIO_SINT_ETH_14     0x20
-#define MPC5XXX_GPIO_SINT_ETH_13     0x10
-#define MPC5XXX_GPIO_SINT_USB1_9     0x08
-#define MPC5XXX_GPIO_SINT_PSC3_8     0x04
-#define MPC5XXX_GPIO_SINT_PSC3_5     0x02
-#define MPC5XXX_GPIO_SINT_PSC3_4     0x01
-
-#define MPC5XXX_GPIO_WKUP_7          0x80
-#define MPC5XXX_GPIO_WKUP_6          0x40
-#define MPC5XXX_GPIO_WKUP_PSC6_1     0x20
-#define MPC5XXX_GPIO_WKUP_PSC6_0     0x10
-#define MPC5XXX_GPIO_WKUP_ETH17      0x08
-#define MPC5XXX_GPIO_WKUP_PSC3_9     0x04
-#define MPC5XXX_GPIO_WKUP_PSC2_4     0x02
-#define MPC5XXX_GPIO_WKUP_PSC1_4     0x01
-
-/* PCI registers */
-#define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)
-#define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)
-#define MPC5XXX_PCI_BAR0	(MPC5XXX_PCI + 0x10)
-#define MPC5XXX_PCI_BAR1	(MPC5XXX_PCI + 0x14)
-#define MPC5XXX_PCI_GSCR	(MPC5XXX_PCI + 0x60)
-#define MPC5XXX_PCI_TBATR0	(MPC5XXX_PCI + 0x64)
-#define MPC5XXX_PCI_TBATR1	(MPC5XXX_PCI + 0x68)
-#define MPC5XXX_PCI_TCR		(MPC5XXX_PCI + 0x6c)
-#define MPC5XXX_PCI_IW0BTAR	(MPC5XXX_PCI + 0x70)
-#define MPC5XXX_PCI_IW1BTAR	(MPC5XXX_PCI + 0x74)
-#define MPC5XXX_PCI_IW2BTAR	(MPC5XXX_PCI + 0x78)
-#define MPC5XXX_PCI_IWCR	(MPC5XXX_PCI + 0x80)
-#define MPC5XXX_PCI_ICR		(MPC5XXX_PCI + 0x84)
-#define MPC5XXX_PCI_ISR		(MPC5XXX_PCI + 0x88)
-#define MPC5XXX_PCI_ARB		(MPC5XXX_PCI + 0x8c)
-#define MPC5XXX_PCI_CAR		(MPC5XXX_PCI + 0xf8)
-
-/* Interrupt Controller registers */
-#define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)
-#define MPC5XXX_ICTL_PER_PRIO1	(MPC5XXX_ICTL + 0x0004)
-#define MPC5XXX_ICTL_PER_PRIO2	(MPC5XXX_ICTL + 0x0008)
-#define MPC5XXX_ICTL_PER_PRIO3	(MPC5XXX_ICTL + 0x000c)
-#define MPC5XXX_ICTL_EXT	(MPC5XXX_ICTL + 0x0010)
-#define MPC5XXX_ICTL_CRIT	(MPC5XXX_ICTL + 0x0014)
-#define MPC5XXX_ICTL_MAIN_PRIO1	(MPC5XXX_ICTL + 0x0018)
-#define MPC5XXX_ICTL_MAIN_PRIO2	(MPC5XXX_ICTL + 0x001c)
-#define MPC5XXX_ICTL_STS	(MPC5XXX_ICTL + 0x0024)
-#define MPC5XXX_ICTL_CRIT_STS	(MPC5XXX_ICTL + 0x0028)
-#define MPC5XXX_ICTL_MAIN_STS	(MPC5XXX_ICTL + 0x002c)
-#define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
-#define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
-
-#define NR_IRQS			64
-
-/* IRQ mapping - these are our logical IRQ numbers */
-#define MPC5XXX_CRIT_IRQ_NUM	4
-#define MPC5XXX_MAIN_IRQ_NUM	17
-#define MPC5XXX_SDMA_IRQ_NUM	17
-#define MPC5XXX_PERP_IRQ_NUM	23
-
-#define MPC5XXX_CRIT_IRQ_BASE	1
-#define MPC5XXX_MAIN_IRQ_BASE	(MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
-#define MPC5XXX_SDMA_IRQ_BASE	(MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
-#define MPC5XXX_PERP_IRQ_BASE	(MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
-
-#define MPC5XXX_IRQ0			(MPC5XXX_CRIT_IRQ_BASE + 0)
-#define MPC5XXX_SLICE_TIMER_0_IRQ	(MPC5XXX_CRIT_IRQ_BASE + 1)
-#define MPC5XXX_HI_INT_IRQ		(MPC5XXX_CRIT_IRQ_BASE + 2)
-#define MPC5XXX_CCS_IRQ			(MPC5XXX_CRIT_IRQ_BASE + 3)
-
-#define MPC5XXX_IRQ1			(MPC5XXX_MAIN_IRQ_BASE + 1)
-#define MPC5XXX_IRQ2			(MPC5XXX_MAIN_IRQ_BASE + 2)
-#define MPC5XXX_IRQ3			(MPC5XXX_MAIN_IRQ_BASE + 3)
-#define MPC5XXX_RTC_PINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 5)
-#define MPC5XXX_RTC_SINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 6)
-#define MPC5XXX_RTC_GPIO_STD_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 7)
-#define MPC5XXX_RTC_GPIO_WKUP_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 8)
-#define MPC5XXX_TMR0_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 9)
-#define MPC5XXX_TMR1_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 10)
-#define MPC5XXX_TMR2_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 11)
-#define MPC5XXX_TMR3_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 12)
-#define MPC5XXX_TMR4_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 13)
-#define MPC5XXX_TMR5_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 14)
-#define MPC5XXX_TMR6_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 15)
-#define MPC5XXX_TMR7_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 16)
-
-#define MPC5XXX_SDMA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 0)
-#define MPC5XXX_PSC1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 1)
-#define MPC5XXX_PSC2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 2)
-#define MPC5XXX_PSC3_IRQ		(MPC5XXX_PERP_IRQ_BASE + 3)
-#define MPC5XXX_PSC6_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
-#define MPC5XXX_IRDA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
-#define MPC5XXX_FEC_IRQ			(MPC5XXX_PERP_IRQ_BASE + 5)
-#define MPC5XXX_USB_IRQ			(MPC5XXX_PERP_IRQ_BASE + 6)
-#define MPC5XXX_ATA_IRQ			(MPC5XXX_PERP_IRQ_BASE + 7)
-#define MPC5XXX_PCI_CNTRL_IRQ		(MPC5XXX_PERP_IRQ_BASE + 8)
-#define MPC5XXX_PCI_SCIRX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 9)
-#define MPC5XXX_PCI_SCITX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 10)
-#define MPC5XXX_PSC4_IRQ		(MPC5XXX_PERP_IRQ_BASE + 11)
-#define MPC5XXX_PSC5_IRQ		(MPC5XXX_PERP_IRQ_BASE + 12)
-#define MPC5XXX_SPI_MODF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 13)
-#define MPC5XXX_SPI_SPIF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 14)
-#define MPC5XXX_I2C1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 15)
-#define MPC5XXX_I2C2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 16)
-#define MPC5XXX_MSCAN1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 17)
-#define MPC5XXX_MSCAN2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 18)
-#define MPC5XXX_IR_RX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 19)
-#define MPC5XXX_IR_TX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 20)
-#define MPC5XXX_XLB_ARB_IRQ		(MPC5XXX_PERP_IRQ_BASE + 21)
-#define MPC5XXX_BDLC_IRQ		(MPC5XXX_PERP_IRQ_BASE + 22)
-
-/* General Purpose Timers registers */
-#define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
-#define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
-#define MPC5XXX_GPT0_STATUS		(MPC5XXX_GPT + 0x0C)
-#define MPC5XXX_GPT1_ENABLE		(MPC5XXX_GPT + 0x10)
-#define MPC5XXX_GPT1_COUNTER		(MPC5XXX_GPT + 0x14)
-#define MPC5XXX_GPT1_STATUS		(MPC5XXX_GPT + 0x1C)
-#define MPC5XXX_GPT2_ENABLE		(MPC5XXX_GPT + 0x20)
-#define MPC5XXX_GPT2_COUNTER		(MPC5XXX_GPT + 0x24)
-#define MPC5XXX_GPT2_STATUS		(MPC5XXX_GPT + 0x2C)
-#define MPC5XXX_GPT3_ENABLE		(MPC5XXX_GPT + 0x30)
-#define MPC5XXX_GPT3_COUNTER		(MPC5XXX_GPT + 0x34)
-#define MPC5XXX_GPT3_STATUS		(MPC5XXX_GPT + 0x3C)
-#define MPC5XXX_GPT4_ENABLE		(MPC5XXX_GPT + 0x40)
-#define MPC5XXX_GPT4_COUNTER		(MPC5XXX_GPT + 0x44)
-#define MPC5XXX_GPT4_STATUS		(MPC5XXX_GPT + 0x4C)
-#define MPC5XXX_GPT5_ENABLE		(MPC5XXX_GPT + 0x50)
-#define MPC5XXX_GPT5_STATUS		(MPC5XXX_GPT + 0x5C)
-#define MPC5XXX_GPT5_COUNTER		(MPC5XXX_GPT + 0x54)
-#define MPC5XXX_GPT6_ENABLE		(MPC5XXX_GPT + 0x60)
-#define MPC5XXX_GPT6_COUNTER		(MPC5XXX_GPT + 0x64)
-#define MPC5XXX_GPT6_STATUS		(MPC5XXX_GPT + 0x6C)
-#define MPC5XXX_GPT7_ENABLE		(MPC5XXX_GPT + 0x70)
-#define MPC5XXX_GPT7_COUNTER		(MPC5XXX_GPT + 0x74)
-#define MPC5XXX_GPT7_STATUS		(MPC5XXX_GPT + 0x7C)
-
-#define MPC5XXX_GPT_GPIO_PIN(status)	((0x00000100 & (status)) >> 8)
-
-#define MPC5XXX_GPT7_PWMCFG		(MPC5XXX_GPT + 0x78)
-
-/* ATA registers */
-#define MPC5XXX_ATA_HOST_CONFIG         (MPC5XXX_ATA + 0x0000)
-#define MPC5XXX_ATA_PIO1                (MPC5XXX_ATA + 0x0008)
-#define MPC5XXX_ATA_PIO2                (MPC5XXX_ATA + 0x000C)
-#define MPC5XXX_ATA_SHARE_COUNT         (MPC5XXX_ATA + 0x002C)
-
-/* I2Cn control register bits */
-#define I2C_EN		0x80
-#define I2C_IEN		0x40
-#define I2C_STA		0x20
-#define I2C_TX		0x10
-#define I2C_TXAK	0x08
-#define I2C_RSTA	0x04
-#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
-
-/* I2Cn status register bits */
-#define I2C_CF		0x80
-#define I2C_AAS		0x40
-#define I2C_BB		0x20
-#define I2C_AL		0x10
-#define I2C_SRW		0x04
-#define I2C_IF		0x02
-#define I2C_RXAK	0x01
-
-/* SPI control register 1 bits */
-#define SPI_CR_LSBFE	0x01
-#define SPI_CR_SSOE	0x02
-#define SPI_CR_CPHA	0x04
-#define SPI_CR_CPOL	0x08
-#define SPI_CR_MSTR	0x10
-#define SPI_CR_SWOM	0x20
-#define SPI_CR_SPE	0x40
-#define SPI_CR_SPIE	0x80
-
-/* SPI status register bits */
-#define SPI_SR_MODF	0x10
-#define SPI_SR_WCOL	0x40
-#define SPI_SR_SPIF	0x80
-
-/* SPI port data register bits */
-#define SPI_PDR_SS	0x08
-
-/* Programmable Serial Controller (PSC) status register bits */
-#define PSC_SR_CDE		0x0080
-#define PSC_SR_RXRDY		0x0100
-#define PSC_SR_RXFULL		0x0200
-#define PSC_SR_TXRDY		0x0400
-#define PSC_SR_TXEMP		0x0800
-#define PSC_SR_OE		0x1000
-#define PSC_SR_PE		0x2000
-#define PSC_SR_FE		0x4000
-#define PSC_SR_RB		0x8000
-
-/* PSC Command values */
-#define PSC_RX_ENABLE		0x0001
-#define PSC_RX_DISABLE		0x0002
-#define PSC_TX_ENABLE		0x0004
-#define PSC_TX_DISABLE		0x0008
-#define PSC_SEL_MODE_REG_1	0x0010
-#define PSC_RST_RX		0x0020
-#define PSC_RST_TX		0x0030
-#define PSC_RST_ERR_STAT	0x0040
-#define PSC_RST_BRK_CHG_INT	0x0050
-#define PSC_START_BRK		0x0060
-#define PSC_STOP_BRK		0x0070
-
-/* PSC Rx FIFO status bits */
-#define PSC_RX_FIFO_ERR		0x0040
-#define PSC_RX_FIFO_UF		0x0020
-#define PSC_RX_FIFO_OF		0x0010
-#define PSC_RX_FIFO_FR		0x0008
-#define PSC_RX_FIFO_FULL	0x0004
-#define PSC_RX_FIFO_ALARM	0x0002
-#define PSC_RX_FIFO_EMPTY	0x0001
-
-/* PSC interrupt mask bits */
-#define PSC_IMR_TXRDY		0x0100
-#define PSC_IMR_RXRDY		0x0200
-#define PSC_IMR_DB		0x0400
-#define PSC_IMR_IPC		0x8000
-
-/* PSC input port change bits */
-#define PSC_IPCR_CTS		0x01
-#define PSC_IPCR_DCD		0x02
-
-/* PSC mode fields */
-#define PSC_MODE_5_BITS		0x00
-#define PSC_MODE_6_BITS		0x01
-#define PSC_MODE_7_BITS		0x02
-#define PSC_MODE_8_BITS		0x03
-#define PSC_MODE_PAREVEN	0x00
-#define PSC_MODE_PARODD		0x04
-#define PSC_MODE_PARFORCE	0x08
-#define PSC_MODE_PARNONE	0x10
-#define PSC_MODE_ERR		0x20
-#define PSC_MODE_FFULL		0x40
-#define PSC_MODE_RXRTS		0x80
-
-#define PSC_MODE_ONE_STOP_5_BITS	0x00
-#define PSC_MODE_ONE_STOP		0x07
-#define PSC_MODE_TWO_STOP		0x0f
-
-/* ATA config fields */
-#define MPC5xxx_ATA_HOSTCONF_SMR	0x80000000UL	/* State machine
-							   reset */
-#define MPC5xxx_ATA_HOSTCONF_FR		0x40000000UL	/* FIFO Reset */
-#define MPC5xxx_ATA_HOSTCONF_IE		0x02000000UL	/* Enable interrupt
-							   in PIO */
-#define MPC5xxx_ATA_HOSTCONF_IORDY	0x01000000UL	/* Drive supports
-							   IORDY protocol */
-
-#ifndef __ASSEMBLY__
-/* Memory map registers */
-struct mpc5xxx_mmap_ctl {
-	volatile u32	mbar;
-	volatile u32	cs0_start;	/* 0x0004 */
-	volatile u32	cs0_stop;
-	volatile u32	cs1_start;	/* 0x000c */
-	volatile u32	cs1_stop;
-	volatile u32	cs2_start;	/* 0x0014 */
-	volatile u32	cs2_stop;
-	volatile u32	cs3_start;	/* 0x001c */
-	volatile u32	cs3_stop;
-	volatile u32	cs4_start;	/* 0x0024 */
-	volatile u32	cs4_stop;
-	volatile u32	cs5_start;	/* 0x002c */
-	volatile u32	cs5_stop;
-	volatile u32	sdram0;		/* 0x0034 */
-	volatile u32	sdram1;		/* 0x0038 */
-	volatile u32	dummy1[4];	/* 0x003c */
-	volatile u32	boot_start;	/* 0x004c */
-	volatile u32	boot_stop;
-	volatile u32	ipbi_ws_ctrl;	/* 0x0054 */
-	volatile u32	cs6_start;	/* 0x0058 */
-	volatile u32	cs6_stop;
-	volatile u32	cs7_start;	/* 0x0060 */
-	volatile u32	cs7_stop;
-};
-
-/* Clock distribution module */
-struct mpc5xxx_cdm {
-	volatile u32	jtagid;		/* 0x0000 */
-	volatile u32	porcfg;
-	volatile u32	brdcrmb;	/* 0x0008 */
-	volatile u32	cfg;
-	volatile u32	fourtyeight_fdc;/* 0x0010 */
-	volatile u32	clock_enable;
-	volatile u32	system_osc;	/* 0x0018 */
-	volatile u32	ccscr;
-	volatile u32	sreset;		/* 0x0020 */
-	volatile u32	pll_status;
-	volatile u32	psc1_mccr;	/* 0x0028 */
-	volatile u32	psc2_mccr;
-	volatile u32	psc3_mccr;	/* 0x0030 */
-	volatile u32	psc6_mccr;
-};
-
-/* SDRAM controller */
-struct mpc5xxx_sdram {
-	volatile u32	mode;
-	volatile u32	ctrl;
-	volatile u32	config1;
-	volatile u32	config2;
-	volatile u32	dummy[32];
-	volatile u32	sdelay;
-};
-
-struct mpc5xxx_lpb {
-	volatile u32	cs0_cfg;
-	volatile u32	cs1_cfg;
-	volatile u32	cs2_cfg;
-	volatile u32	cs3_cfg;
-	volatile u32	cs4_cfg;
-	volatile u32	cs5_cfg;
-	volatile u32	cs_ctrl;
-	volatile u32	cs_status;
-	volatile u32	cs6_cfg;
-	volatile u32	cs7_cfg;
-	volatile u32	cs_burst;
-	volatile u32	cs_deadcycle;
-};
-
-
-struct mpc5xxx_psc {
-	volatile u8	mode;		/* PSC + 0x00 */
-	volatile u8	reserved0[3];
-	union {				/* PSC + 0x04 */
-		volatile u16	status;
-		volatile u16	clock_select;
-	} sr_csr;
-#define psc_status	sr_csr.status
-#define psc_clock_select sr_csr.clock_select
-	volatile u16	reserved1;
-	volatile u8	command;	/* PSC + 0x08 */
-	volatile u8	reserved2[3];
-	union {				/* PSC + 0x0c */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} buffer;
-#define psc_buffer_8	buffer.buffer_8
-#define psc_buffer_16	buffer.buffer_16
-#define psc_buffer_32	buffer.buffer_32
-	union {				/* PSC + 0x10 */
-		volatile u8	ipcr;
-		volatile u8	acr;
-	} ipcr_acr;
-#define psc_ipcr	ipcr_acr.ipcr
-#define psc_acr		ipcr_acr.acr
-	volatile u8	reserved3[3];
-	union {				/* PSC + 0x14 */
-		volatile u16	isr;
-		volatile u16	imr;
-	} isr_imr;
-#define psc_isr		isr_imr.isr
-#define psc_imr		isr_imr.imr
-	volatile u16	reserved4;
-	volatile u8	ctur;		/* PSC + 0x18 */
-	volatile u8	reserved5[3];
-	volatile u8	ctlr;		/* PSC + 0x1c */
-	volatile u8	reserved6[3];
-	volatile u16	ccr;		/* PSC + 0x20 */
-	volatile u8	reserved7[14];
-	volatile u8	ivr;		/* PSC + 0x30 */
-	volatile u8	reserved8[3];
-	volatile u8	ip;		/* PSC + 0x34 */
-	volatile u8	reserved9[3];
-	volatile u8	op1;		/* PSC + 0x38 */
-	volatile u8	reserved10[3];
-	volatile u8	op0;		/* PSC + 0x3c */
-	volatile u8	reserved11[3];
-	volatile u32	sicr;		/* PSC + 0x40 */
-	volatile u8	ircr1;		/* PSC + 0x44 */
-	volatile u8	reserved12[3];
-	volatile u8	ircr2;		/* PSC + 0x44 */
-	volatile u8	reserved13[3];
-	volatile u8	irsdr;		/* PSC + 0x4c */
-	volatile u8	reserved14[3];
-	volatile u8	irmdr;		/* PSC + 0x50 */
-	volatile u8	reserved15[3];
-	volatile u8	irfdr;		/* PSC + 0x54 */
-	volatile u8	reserved16[3];
-	volatile u16	rfnum;		/* PSC + 0x58 */
-	volatile u16	reserved17;
-	volatile u16	tfnum;		/* PSC + 0x5c */
-	volatile u16	reserved18;
-	volatile u32	rfdata;		/* PSC + 0x60 */
-	volatile u16	rfstat;		/* PSC + 0x64 */
-	volatile u16	reserved20;
-	volatile u8	rfcntl;		/* PSC + 0x68 */
-	volatile u8	reserved21[5];
-	volatile u16	rfalarm;	/* PSC + 0x6e */
-	volatile u16	reserved22;
-	volatile u16	rfrptr;		/* PSC + 0x72 */
-	volatile u16	reserved23;
-	volatile u16	rfwptr;		/* PSC + 0x76 */
-	volatile u16	reserved24;
-	volatile u16	rflrfptr;	/* PSC + 0x7a */
-	volatile u16	reserved25;
-	volatile u16	rflwfptr;	/* PSC + 0x7e */
-	volatile u32	tfdata;		/* PSC + 0x80 */
-	volatile u16	tfstat;		/* PSC + 0x84 */
-	volatile u16	reserved26;
-	volatile u8	tfcntl;		/* PSC + 0x88 */
-	volatile u8	reserved27[5];
-	volatile u16	tfalarm;	/* PSC + 0x8e */
-	volatile u16	reserved28;
-	volatile u16	tfrptr;		/* PSC + 0x92 */
-	volatile u16	reserved29;
-	volatile u16	tfwptr;		/* PSC + 0x96 */
-	volatile u16	reserved30;
-	volatile u16	tflrfptr;	/* PSC + 0x9a */
-	volatile u16	reserved31;
-	volatile u16	tflwfptr;	/* PSC + 0x9e */
-};
-
-struct mpc5xxx_intr {
-	volatile u32	per_mask;	/* INTR + 0x00 */
-	volatile u32	per_pri1;	/* INTR + 0x04 */
-	volatile u32	per_pri2;	/* INTR + 0x08 */
-	volatile u32	per_pri3;	/* INTR + 0x0c */
-	volatile u32	ctrl;		/* INTR + 0x10 */
-	volatile u32	main_mask;	/* INTR + 0x14 */
-	volatile u32	main_pri1;	/* INTR + 0x18 */
-	volatile u32	main_pri2;	/* INTR + 0x1c */
-	volatile u32	reserved1;	/* INTR + 0x20 */
-	volatile u32	enc_status;	/* INTR + 0x24 */
-	volatile u32	crit_status;	/* INTR + 0x28 */
-	volatile u32	main_status;	/* INTR + 0x2c */
-	volatile u32	per_status;	/* INTR + 0x30 */
-	volatile u32	reserved2;	/* INTR + 0x34 */
-	volatile u32	per_error;	/* INTR + 0x38 */
-};
-
-struct mpc5xxx_gpio {
-	volatile u32 port_config;	/* GPIO + 0x00 */
-	volatile u32 simple_gpioe;	/* GPIO + 0x04 */
-	volatile u32 simple_ode;	/* GPIO + 0x08 */
-	volatile u32 simple_ddr;	/* GPIO + 0x0c */
-	volatile u32 simple_dvo;	/* GPIO + 0x10 */
-	volatile u32 simple_ival;	/* GPIO + 0x14 */
-	volatile u8 outo_gpioe;		/* GPIO + 0x18 */
-	volatile u8 reserved1[3];	/* GPIO + 0x19 */
-	volatile u8 outo_dvo;		/* GPIO + 0x1c */
-	volatile u8 reserved2[3];	/* GPIO + 0x1d */
-	volatile u8 sint_gpioe;		/* GPIO + 0x20 */
-	volatile u8 reserved3[3];	/* GPIO + 0x21 */
-	volatile u8 sint_ode;		/* GPIO + 0x24 */
-	volatile u8 reserved4[3];	/* GPIO + 0x25 */
-	volatile u8 sint_ddr;		/* GPIO + 0x28 */
-	volatile u8 reserved5[3];	/* GPIO + 0x29 */
-	volatile u8 sint_dvo;		/* GPIO + 0x2c */
-	volatile u8 reserved6[3];	/* GPIO + 0x2d */
-	volatile u8 sint_inten;		/* GPIO + 0x30 */
-	volatile u8 reserved7[3];	/* GPIO + 0x31 */
-	volatile u16 sint_itype;	/* GPIO + 0x34 */
-	volatile u16 reserved8;		/* GPIO + 0x36 */
-	volatile u8 gpio_control;	/* GPIO + 0x38 */
-	volatile u8 reserved9[3];	/* GPIO + 0x39 */
-	volatile u8 sint_istat;		/* GPIO + 0x3c */
-	volatile u8 sint_ival;		/* GPIO + 0x3d */
-	volatile u8 bus_errs;		/* GPIO + 0x3e */
-	volatile u8 reserved10;		/* GPIO + 0x3f */
-};
-
-struct mpc5xxx_wu_gpio {
-	volatile u8 enable;		/* WU_GPIO + 0x00 */
-	volatile u8 reserved1[3];	/* WU_GPIO + 0x01 */
-	volatile u8 ode;		/* WU_GPIO + 0x04 */
-	volatile u8 reserved2[3];	/* WU_GPIO + 0x05 */
-	volatile u8 ddr;		/* WU_GPIO + 0x08 */
-	volatile u8 reserved3[3];	/* WU_GPIO + 0x09 */
-	volatile u8 dvo;		/* WU_GPIO + 0x0c */
-	volatile u8 reserved4[3];	/* WU_GPIO + 0x0d */
-	volatile u8 inten;		/* WU_GPIO + 0x10 */
-	volatile u8 reserved5[3];	/* WU_GPIO + 0x11 */
-	volatile u8 iinten;		/* WU_GPIO + 0x14 */
-	volatile u8 reserved6[3];	/* WU_GPIO + 0x15 */
-	volatile u16 itype;		/* WU_GPIO + 0x18 */
-	volatile u8 reserved7[2];	/* WU_GPIO + 0x1a */
-	volatile u8 master_enable;	/* WU_GPIO + 0x1c */
-	volatile u8 reserved8[3];	/* WU_GPIO + 0x1d */
-	volatile u8 ival;		/* WU_GPIO + 0x20 */
-	volatile u8 reserved9[3];	/* WU_GPIO + 0x21 */
-	volatile u8 status;		/* WU_GPIO + 0x24 */
-	volatile u8 reserved10[3];	/* WU_GPIO + 0x25 */
-};
-
-struct mpc5xxx_sdma {
-	volatile u32 taskBar;		/* SDMA + 0x00 */
-	volatile u32 currentPointer;	/* SDMA + 0x04 */
-	volatile u32 endPointer;	/* SDMA + 0x08 */
-	volatile u32 variablePointer;	/* SDMA + 0x0c */
-
-	volatile u8 IntVect1;		/* SDMA + 0x10 */
-	volatile u8 IntVect2;		/* SDMA + 0x11 */
-	volatile u16 PtdCntrl;		/* SDMA + 0x12 */
-
-	volatile u32 IntPend;		/* SDMA + 0x14 */
-	volatile u32 IntMask;		/* SDMA + 0x18 */
-
-	volatile u16 tcr_0;		/* SDMA + 0x1c */
-	volatile u16 tcr_1;		/* SDMA + 0x1e */
-	volatile u16 tcr_2;		/* SDMA + 0x20 */
-	volatile u16 tcr_3;		/* SDMA + 0x22 */
-	volatile u16 tcr_4;		/* SDMA + 0x24 */
-	volatile u16 tcr_5;		/* SDMA + 0x26 */
-	volatile u16 tcr_6;		/* SDMA + 0x28 */
-	volatile u16 tcr_7;		/* SDMA + 0x2a */
-	volatile u16 tcr_8;		/* SDMA + 0x2c */
-	volatile u16 tcr_9;		/* SDMA + 0x2e */
-	volatile u16 tcr_a;		/* SDMA + 0x30 */
-	volatile u16 tcr_b;		/* SDMA + 0x32 */
-	volatile u16 tcr_c;		/* SDMA + 0x34 */
-	volatile u16 tcr_d;		/* SDMA + 0x36 */
-	volatile u16 tcr_e;		/* SDMA + 0x38 */
-	volatile u16 tcr_f;		/* SDMA + 0x3a */
-
-	volatile u8 IPR0;		/* SDMA + 0x3c */
-	volatile u8 IPR1;		/* SDMA + 0x3d */
-	volatile u8 IPR2;		/* SDMA + 0x3e */
-	volatile u8 IPR3;		/* SDMA + 0x3f */
-	volatile u8 IPR4;		/* SDMA + 0x40 */
-	volatile u8 IPR5;		/* SDMA + 0x41 */
-	volatile u8 IPR6;		/* SDMA + 0x42 */
-	volatile u8 IPR7;		/* SDMA + 0x43 */
-	volatile u8 IPR8;		/* SDMA + 0x44 */
-	volatile u8 IPR9;		/* SDMA + 0x45 */
-	volatile u8 IPR10;		/* SDMA + 0x46 */
-	volatile u8 IPR11;		/* SDMA + 0x47 */
-	volatile u8 IPR12;		/* SDMA + 0x48 */
-	volatile u8 IPR13;		/* SDMA + 0x49 */
-	volatile u8 IPR14;		/* SDMA + 0x4a */
-	volatile u8 IPR15;		/* SDMA + 0x4b */
-	volatile u8 IPR16;		/* SDMA + 0x4c */
-	volatile u8 IPR17;		/* SDMA + 0x4d */
-	volatile u8 IPR18;		/* SDMA + 0x4e */
-	volatile u8 IPR19;		/* SDMA + 0x4f */
-	volatile u8 IPR20;		/* SDMA + 0x50 */
-	volatile u8 IPR21;		/* SDMA + 0x51 */
-	volatile u8 IPR22;		/* SDMA + 0x52 */
-	volatile u8 IPR23;		/* SDMA + 0x53 */
-	volatile u8 IPR24;		/* SDMA + 0x54 */
-	volatile u8 IPR25;		/* SDMA + 0x55 */
-	volatile u8 IPR26;		/* SDMA + 0x56 */
-	volatile u8 IPR27;		/* SDMA + 0x57 */
-	volatile u8 IPR28;		/* SDMA + 0x58 */
-	volatile u8 IPR29;		/* SDMA + 0x59 */
-	volatile u8 IPR30;		/* SDMA + 0x5a */
-	volatile u8 IPR31;		/* SDMA + 0x5b */
-
-	volatile u32 res1;		/* SDMA + 0x5c */
-	volatile u32 res2;		/* SDMA + 0x60 */
-	volatile u32 res3;		/* SDMA + 0x64 */
-	volatile u32 MDEDebug;		/* SDMA + 0x68 */
-	volatile u32 ADSDebug;		/* SDMA + 0x6c */
-	volatile u32 Value1;		/* SDMA + 0x70 */
-	volatile u32 Value2;		/* SDMA + 0x74 */
-	volatile u32 Control;		/* SDMA + 0x78 */
-	volatile u32 Status;		/* SDMA + 0x7c */
-	volatile u32 EU00;		/* SDMA + 0x80 */
-	volatile u32 EU01;		/* SDMA + 0x84 */
-	volatile u32 EU02;		/* SDMA + 0x88 */
-	volatile u32 EU03;		/* SDMA + 0x8c */
-	volatile u32 EU04;		/* SDMA + 0x90 */
-	volatile u32 EU05;		/* SDMA + 0x94 */
-	volatile u32 EU06;		/* SDMA + 0x98 */
-	volatile u32 EU07;		/* SDMA + 0x9c */
-	volatile u32 EU10;		/* SDMA + 0xa0 */
-	volatile u32 EU11;		/* SDMA + 0xa4 */
-	volatile u32 EU12;		/* SDMA + 0xa8 */
-	volatile u32 EU13;		/* SDMA + 0xac */
-	volatile u32 EU14;		/* SDMA + 0xb0 */
-	volatile u32 EU15;		/* SDMA + 0xb4 */
-	volatile u32 EU16;		/* SDMA + 0xb8 */
-	volatile u32 EU17;		/* SDMA + 0xbc */
-	volatile u32 EU20;		/* SDMA + 0xc0 */
-	volatile u32 EU21;		/* SDMA + 0xc4 */
-	volatile u32 EU22;		/* SDMA + 0xc8 */
-	volatile u32 EU23;		/* SDMA + 0xcc */
-	volatile u32 EU24;		/* SDMA + 0xd0 */
-	volatile u32 EU25;		/* SDMA + 0xd4 */
-	volatile u32 EU26;		/* SDMA + 0xd8 */
-	volatile u32 EU27;		/* SDMA + 0xdc */
-	volatile u32 EU30;		/* SDMA + 0xe0 */
-	volatile u32 EU31;		/* SDMA + 0xe4 */
-	volatile u32 EU32;		/* SDMA + 0xe8 */
-	volatile u32 EU33;		/* SDMA + 0xec */
-	volatile u32 EU34;		/* SDMA + 0xf0 */
-	volatile u32 EU35;		/* SDMA + 0xf4 */
-	volatile u32 EU36;		/* SDMA + 0xf8 */
-	volatile u32 EU37;		/* SDMA + 0xfc */
-};
-
-struct mpc5xxx_i2c {
-	volatile u32 madr;		/* I2Cn + 0x00 */
-	volatile u32 mfdr;		/* I2Cn + 0x04 */
-	volatile u32 mcr;		/* I2Cn + 0x08 */
-	volatile u32 msr;		/* I2Cn + 0x0C */
-	volatile u32 mdr;		/* I2Cn + 0x10 */
-};
-
-struct mpc5xxx_spi {
-	volatile u8 cr1;		/* SPI + 0x0F00 */
-	volatile u8 cr2;		/* SPI + 0x0F01 */
-	volatile u8 reserved1[2];
-	volatile u8 brr;		/* SPI + 0x0F04 */
-	volatile u8 sr;			/* SPI + 0x0F05 */
-	volatile u8 reserved2[3];
-	volatile u8 dr;			/* SPI + 0x0F09 */
-	volatile u8 reserved3[3];
-	volatile u8 pdr;		/* SPI + 0x0F0D */
-	volatile u8 reserved4[2];
-	volatile u8 ddr;		/* SPI + 0x0F10 */
-};
-
-
-struct mpc5xxx_gpt {
-	volatile u32 emsr;		/* GPT + Timer# * 0x10 + 0x00 */
-	volatile u32 cir;		/* GPT + Timer# * 0x10 + 0x04 */
-	volatile u32 pwmcr;		/* GPT + Timer# * 0x10 + 0x08 */
-	volatile u32 sr;		/* GPT + Timer# * 0x10 + 0x0c */
-};
-
-struct mpc5xxx_gpt_0_7 {
-	struct mpc5xxx_gpt gpt0;
-	struct mpc5xxx_gpt gpt1;
-	struct mpc5xxx_gpt gpt2;
-	struct mpc5xxx_gpt gpt3;
-	struct mpc5xxx_gpt gpt4;
-	struct mpc5xxx_gpt gpt5;
-	struct mpc5xxx_gpt gpt6;
-	struct mpc5xxx_gpt gpt7;
-};
-
-struct mscan_buffer {
-	volatile u8  idr[0x8];          /* 0x00 */
-	volatile u8  dsr[0x10];         /* 0x08 */
-	volatile u8  dlr;               /* 0x18 */
-	volatile u8  tbpr;              /* 0x19 */      /* This register is not applicable for receive buffers */
-	volatile u16 rsrv1;             /* 0x1A */
-	volatile u8  tsrh;              /* 0x1C */
-	volatile u8  tsrl;              /* 0x1D */
-	volatile u16 rsrv2;             /* 0x1E */
-};
-
-struct mpc5xxx_mscan {
-	volatile u8  canctl0;           /* MSCAN + 0x00 */
-	volatile u8  canctl1;           /* MSCAN + 0x01 */
-	volatile u16 rsrv1;             /* MSCAN + 0x02 */
-	volatile u8  canbtr0;           /* MSCAN + 0x04 */
-	volatile u8  canbtr1;           /* MSCAN + 0x05 */
-	volatile u16 rsrv2;             /* MSCAN + 0x06 */
-	volatile u8  canrflg;           /* MSCAN + 0x08 */
-	volatile u8  canrier;           /* MSCAN + 0x09 */
-	volatile u16 rsrv3;             /* MSCAN + 0x0A */
-	volatile u8  cantflg;           /* MSCAN + 0x0C */
-	volatile u8  cantier;           /* MSCAN + 0x0D */
-	volatile u16 rsrv4;             /* MSCAN + 0x0E */
-	volatile u8  cantarq;           /* MSCAN + 0x10 */
-	volatile u8  cantaak;           /* MSCAN + 0x11 */
-	volatile u16 rsrv5;             /* MSCAN + 0x12 */
-	volatile u8  cantbsel;          /* MSCAN + 0x14 */
-	volatile u8  canidac;           /* MSCAN + 0x15 */
-	volatile u16 rsrv6[3];          /* MSCAN + 0x16 */
-	volatile u8  canrxerr;          /* MSCAN + 0x1C */
-	volatile u8  cantxerr;          /* MSCAN + 0x1D */
-	volatile u16 rsrv7;             /* MSCAN + 0x1E */
-	volatile u8  canidar0;          /* MSCAN + 0x20 */
-	volatile u8  canidar1;          /* MSCAN + 0x21 */
-	volatile u16 rsrv8;             /* MSCAN + 0x22 */
-	volatile u8  canidar2;          /* MSCAN + 0x24 */
-	volatile u8  canidar3;          /* MSCAN + 0x25 */
-	volatile u16 rsrv9;             /* MSCAN + 0x26 */
-	volatile u8  canidmr0;          /* MSCAN + 0x28 */
-	volatile u8  canidmr1;          /* MSCAN + 0x29 */
-	volatile u16 rsrv10;            /* MSCAN + 0x2A */
-	volatile u8  canidmr2;          /* MSCAN + 0x2C */
-	volatile u8  canidmr3;          /* MSCAN + 0x2D */
-	volatile u16 rsrv11;            /* MSCAN + 0x2E */
-	volatile u8  canidar4;          /* MSCAN + 0x30 */
-	volatile u8  canidar5;          /* MSCAN + 0x31 */
-	volatile u16 rsrv12;            /* MSCAN + 0x32 */
-	volatile u8  canidar6;          /* MSCAN + 0x34 */
-	volatile u8  canidar7;          /* MSCAN + 0x35 */
-	volatile u16 rsrv13;            /* MSCAN + 0x36 */
-	volatile u8  canidmr4;          /* MSCAN + 0x38 */
-	volatile u8  canidmr5;          /* MSCAN + 0x39 */
-	volatile u16 rsrv14;            /* MSCAN + 0x3A */
-	volatile u8  canidmr6;          /* MSCAN + 0x3C */
-	volatile u8  canidmr7;          /* MSCAN + 0x3D */
-	volatile u16 rsrv15;            /* MSCAN + 0x3E */
-
-	struct mscan_buffer canrxfg;    /* MSCAN + 0x40 */    /* Foreground receive buffer */
-	struct mscan_buffer cantxfg;    /* MSCAN + 0x60 */    /* Foreground transmit buffer */
-	};
-
-struct mpc5xxx_xlb {
-	volatile u8 reserved[0x40];	/* XLB + 0x00 */
-	volatile u32 config;		/* XLB + 0x40 */
-	volatile u32 version;		/* XLB + 0x44 */
-	volatile u32 status;		/* XLB + 0x48 */
-	volatile u32 int_enable;	/* XLB + 0x4c */
-	volatile u32 addr_capture;	/* XLB + 0x50 */
-	volatile u32 bus_sig_capture;	/* XLB + 0x54 */
-	volatile u32 addr_timeout;	/* XLB + 0x58 */
-	volatile u32 data_timeout;	/* XLB + 0x5c */
-	volatile u32 bus_act_timeout;	/* XLB + 0x60 */
-	volatile u32 master_pri_enable; /* XLB + 0x64 */
-	volatile u32 master_priority;	/* XLB + 0x68 */
-	volatile u32 base_address;	/* XLB + 0x6c */
-	volatile u32 snoop_window;	/* XLB + 0x70 */
-};
-
-struct pci_controller;
-
-/* function prototypes */
-void loadtask(int basetask, int tasks);
-void pci_mpc5xxx_init(struct pci_controller *);
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASMPPC_MPC5XXX_H */
diff --git a/include/mpc5xxx_sdma.h b/include/mpc5xxx_sdma.h
deleted file mode 100644
index 821ac0a..0000000
--- a/include/mpc5xxx_sdma.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on code
- * (C) Copyright Motorola, Inc., 2000
- *
- * odin smartdma header file
- */
-
-#ifndef __MPC5XXX_SDMA_H
-#define __MPC5XXX_SDMA_H
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-/* Task number assignment */
-#define FEC_RECV_TASK_NO            0
-#define FEC_XMIT_TASK_NO            1
-
-/*---------------------------------------------------------------------*/
-
-/* Stuff for Ethernet Tx/Rx tasks                                      */
-
-/*---------------------------------------------------------------------*/
-
-/* Layout of Ethernet controller Parameter SRAM area:
-----------------------------------------------------------------
-0x00: TBD_BASE, base address of TX BD ring
-0x04: TBD_NEXT, address of next TX BD to be processed
-0x08: RBD_BASE, base address of RX BD ring
-0x0C: RBD_NEXT, address of next RX BD to be processed
----------------------------------------------------------------
-ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
-*/
-
-/* base address of SRAM area to store parameters used by Ethernet tasks */
-#define FEC_PARAM_BASE		(MPC5XXX_SRAM + 0x0800)
-
-/* base address of SRAM area for buffer descriptors */
-#define FEC_BD_BASE		(MPC5XXX_SRAM + 0x0820)
-
-/*---------------------------------------------------------------------*/
-
-/* common shortcuts  used  by driver C code                            */
-
-/*---------------------------------------------------------------------*/
-
-/* Disable SmartDMA task */
-#define SDMA_TASK_DISABLE(tasknum)                     \
-{                                                      \
-    volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
-    *tcr = (*tcr) & (~0x8000);                         \
-}
-
-/* Enable SmartDMA task */
-#define SDMA_TASK_ENABLE(tasknum)                      \
-{                                                      \
-    volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
-    *tcr = (*tcr)  | 0x8000;                           \
-}
-
-/* Enable interrupt */
-#define SDMA_INT_ENABLE(tasknum)                       \
-{                                                      \
-    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
-    sdma->IntMask &= ~(1 << tasknum);                  \
-}
-
-/* Disable interrupt */
-#define SDMA_INT_DISABLE(tasknum)   \
-{                                                      \
-    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
-    sdma->IntMask |= (1 << tasknum);                   \
-}
-
-
-/* Clear interrupt pending bits */
-#define SDMA_CLEAR_IEVENT(tasknum)  \
-{                                                      \
-    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
-    sdma->IntPend = (1 << tasknum);                    \
-}
-
-/* get interrupt pending bit of a task */
-#define SDMA_GET_PENDINGBIT(tasknum)                   \
-	((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
-
-/* get interrupt mask bit of a task */
-#define SDMA_GET_MASKBIT(tasknum)                      \
-	((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
-
-#endif	/* __MPC5XXX_SDMA_H */
diff --git a/include/netdev.h b/include/netdev.h
index 8eb8b46..38c0453 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -57,8 +57,6 @@
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int mcdmafec_initialize(bd_t *bis);
 int mcffec_initialize(bd_t *bis);
-int mpc512x_fec_initialize(bd_t *bis);
-int mpc5xxx_fec_initialize(bd_t *bis);
 int mpc82xx_scc_enet_initialize(bd_t *bis);
 int mvgbe_initialize(bd_t *bis);
 int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
diff --git a/include/post.h b/include/post.h
index 8bee125..b9b9c37 100644
--- a/include/post.h
+++ b/include/post.h
@@ -22,14 +22,7 @@
 #define _POST_WORD_ADDR	CONFIG_SYS_POST_WORD_ADDR
 #else
 
-#ifdef CONFIG_MPC5xxx
-#define _POST_WORD_ADDR	(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE)
-
-#elif defined(CONFIG_MPC512X)
-#define _POST_WORD_ADDR \
-	(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#elif defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
 #include <linux/immap_qe.h>
 #define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
 
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 5a0fda2..ce71ee9 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -81,13 +81,6 @@
 #define	r30	30
 #define	r31	31
 
-#if defined(CONFIG_MPC5xxx)
-
-#define HID0_ICE_BITPOS	16
-#define HID0_DCE_BITPOS	17
-
-#endif
-
 #define curptr r2
 
 #define SYNC \
diff --git a/include/serial.h b/include/serial.h
index 47332c5..a37ea18 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -29,9 +29,8 @@
 #if	defined(CONFIG_405GP) || \
 	defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 	defined(CONFIG_405EX) || defined(CONFIG_440) || \
-	defined(CONFIG_MPC5xxx) || \
 	defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
-	defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
+	defined(CONFIG_MPC86xx) || \
 	defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
 	defined(CONFIG_MICROBLAZE)
 extern struct serial_device serial0_device;
@@ -69,13 +68,6 @@
 
 #endif /* CONFIG_USB_TTY */
 
-#if defined(CONFIG_MPC512X)
-extern struct stdio_dev *open_port(int num, int baudrate);
-extern int close_port(int num);
-extern int write_port(struct stdio_dev *port, char *buf);
-extern int read_port(struct stdio_dev *port, char *buf, int size);
-#endif
-
 struct udevice;
 
 /**
@@ -192,7 +184,6 @@
 void max3100_serial_initialize(void);
 void mcf_serial_initialize(void);
 void ml2_serial_initialize(void);
-void mpc512x_serial_initialize(void);
 void mpc5xx_serial_initialize(void);
 void mpc8260_scc_serial_initialize(void);
 void mpc8260_smc_serial_initialize(void);
diff --git a/include/status_led.h b/include/status_led.h
index e377346..8178e93 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -56,10 +56,6 @@
    * filling this file up with lots of custom board stuff.
    */
 
-#elif defined(CONFIG_V38B)
-
-# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
-
 #elif defined(CONFIG_LED_STATUS_BOARD_SPECIFIC)
 /* led_id_t is unsigned long mask */
 typedef unsigned long led_id_t;
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 8f3437a..847b698 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -156,9 +156,6 @@
 #elif defined(CONFIG_MPC85xx)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
-#elif defined(CONFIG_MPC512X)
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
-#define CONFIG_SYS_FSL_USB2_ADDR	0
 #elif defined(CONFIG_ARCH_LS1021A)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR        0
diff --git a/include/watchdog.h b/include/watchdog.h
index 20ac59a..322dda7 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -72,11 +72,6 @@
  * Prototypes from $(CPU)/cpu.c.
  */
 
-/* MPC 5xxx */
-#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__)
-	void reset_5xxx_watchdog(void);
-#endif
-
 /* AMCC 4xx */
 #if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
 	void reset_4xx_watchdog(void);