powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x
There was for long time no activity in the mpx5xxx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in mpc5xxx,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c
index f1425cb..0299a5a 100644
--- a/drivers/bootcount/bootcount.c
+++ b/drivers/bootcount/bootcount.c
@@ -14,16 +14,6 @@
*/
#if !defined(CONFIG_SYS_BOOTCOUNT_ADDR)
-#if defined(CONFIG_MPC5xxx)
-#define CONFIG_SYS_BOOTCOUNT_ADDR (MPC5XXX_CDM_BRDCRMB)
-#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
-#endif /* defined(CONFIG_MPC5xxx) */
-
-#if defined(CONFIG_MPC512X)
-#define CONFIG_SYS_BOOTCOUNT_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->clk.bcr)
-#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
-#endif /* defined(CONFIG_MPC512X) */
-
#if defined(CONFIG_QE)
#include <linux/immap_qe.h>
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index 7af5868..84ee015 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c
@@ -20,7 +20,7 @@
static int kbd_read_keys(struct input_config *config)
{
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
+#if defined(CONFIG_ARCH_MPC8540) || \
defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index bcbe52a..0b5ce06 100644
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c
@@ -29,25 +29,6 @@
#define PS2SER_BAUD 57600
-#ifdef CONFIG_MPC5xxx
-#if CONFIG_PS2SERIAL == 1
-#define PSC_BASE MPC5XXX_PSC1
-#elif CONFIG_PS2SERIAL == 2
-#define PSC_BASE MPC5XXX_PSC2
-#elif CONFIG_PS2SERIAL == 3
-#define PSC_BASE MPC5XXX_PSC3
-#elif CONFIG_PS2SERIAL == 4
-#define PSC_BASE MPC5XXX_PSC4
-#elif CONFIG_PS2SERIAL == 5
-#define PSC_BASE MPC5XXX_PSC5
-#elif CONFIG_PS2SERIAL == 6
-#define PSC_BASE MPC5XXX_PSC6
-#else
-#error CONFIG_PS2SERIAL must be in 1 ... 6
-#endif
-
-#else
-
#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
#elif CONFIG_PS2SERIAL == 2
@@ -56,8 +37,6 @@
#error CONFIG_PS2SERIAL must be in 1 ... 2
#endif
-#endif /* CONFIG_MPC5xxx / other */
-
static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
@@ -68,45 +47,6 @@
static int ps2buf_in_idx;
static int ps2buf_out_idx;
-#ifdef CONFIG_MPC5xxx
-int ps2ser_init(void)
-{
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
- unsigned long baseclk;
- int div;
-
- /* reset PSC */
- psc->command = PSC_SEL_MODE_REG_1;
-
- /* select clock sources */
- psc->psc_clock_select = 0;
- baseclk = (gd->arch.ipb_clk + 16) / 32;
-
- /* switch to UART mode */
- psc->sicr = 0;
-
- /* configure parity, bit length and so on */
- psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
- psc->mode = PSC_MODE_ONE_STOP;
-
- /* set up UART divisor */
- div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
- psc->ctur = (div >> 8) & 0xff;
- psc->ctlr = div & 0xff;
-
- /* disable all interrupts */
- psc->psc_imr = 0;
-
- /* reset and enable Rx/Tx */
- psc->command = PSC_RST_RX;
- psc->command = PSC_RST_TX;
- psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
-
- return (0);
-}
-
-#else
-
int ps2ser_init(void)
{
NS16550_t com_port = (NS16550_t)COM_BASE;
@@ -122,45 +62,23 @@
return (0);
}
-#endif /* CONFIG_MPC5xxx / other */
-
void ps2ser_putc(int chr)
{
-#ifdef CONFIG_MPC5xxx
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#else
NS16550_t com_port = (NS16550_t)COM_BASE;
-#endif
debug(">>>> 0x%02x\n", chr);
-#ifdef CONFIG_MPC5xxx
- while (!(psc->psc_status & PSC_SR_TXRDY));
-
- psc->psc_buffer_8 = chr;
-#else
while ((com_port->lsr & UART_LSR_THRE) == 0);
com_port->thr = chr;
-#endif
}
static int ps2ser_getc_hw(void)
{
-#ifdef CONFIG_MPC5xxx
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#else
NS16550_t com_port = (NS16550_t)COM_BASE;
-#endif
int res = -1;
-#ifdef CONFIG_MPC5xxx
- if (psc->psc_status & PSC_SR_RXRDY) {
- res = (psc->psc_buffer_8);
- }
-#else
if (com_port->lsr & UART_LSR_DR) {
res = com_port->rbr;
}
-#endif
return res;
}
@@ -206,21 +124,13 @@
static void ps2ser_interrupt(void *dev_id)
{
-#ifdef CONFIG_MPC5xxx
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#else
NS16550_t com_port = (NS16550_t)COM_BASE;
-#endif
int chr;
int status;
do {
chr = ps2ser_getc_hw();
-#ifdef CONFIG_MPC5xxx
- status = psc->psc_status;
-#else
status = com_port->lsr;
-#endif
if (chr < 0) continue;
if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
@@ -230,11 +140,7 @@
} else {
printf ("ps2ser.c: buffer overflow\n");
}
-#ifdef CONFIG_MPC5xxx
- } while (status & PSC_SR_RXRDY);
-#else
} while (status & UART_LSR_DR);
-#endif
if (atomic_read(&ps2buf_cnt)) {
ps2mult_callback(atomic_read(&ps2buf_cnt));
}
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index 2feb182..3c9f029 100644
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -13,9 +13,7 @@
#include <fuse.h>
#include <linux/errno.h>
#include <asm/io.h>
-#ifndef CONFIG_MPC512X
#include <asm/arch/imx-regs.h>
-#endif
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/clock.h>
#endif
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a7b76f4..ce8ba99 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -33,11 +33,11 @@
used to preserve the bad block marker in the OOB area.
config NAND_VF610_NFC
- bool "Support for Freescale NFC for VF610/MPC5125"
+ bool "Support for Freescale NFC for VF610"
select SYS_NAND_SELF_INIT
help
Enables support for NAND Flash Controller on some Freescale
- processors like the VF610, MPC5125, MCF54418 or Kinetis K70.
+ processors like the VF610, MCF54418 or Kinetis K70.
The driver supports a maximum 2k page size. The driver
currently does not support hardware ECC.
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 5d5f9f5..c3d4a99 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,7 +53,6 @@
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
-obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
deleted file mode 100644
index 7faabdd..0000000
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * Copyright 2004-2008 Freescale Semiconductor, Inc.
- * Copyright 2009 Semihalf.
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>
- *
- * Based on original driver from Freescale Semiconductor
- * written by John Rigby <jrigby@freescale.com> on basis
- * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
- * Piotr Ziecik <kosmo@semihalf.com>.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/compat.h>
-
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <nand.h>
-
-#define DRV_NAME "mpc5121_nfc"
-
-/* Timeouts */
-#define NFC_RESET_TIMEOUT 1000 /* 1 ms */
-#define NFC_TIMEOUT 2000 /* 2000 us */
-
-/* Addresses for NFC MAIN RAM BUFFER areas */
-#define NFC_MAIN_AREA(n) ((n) * 0x200)
-
-/* Addresses for NFC SPARE BUFFER areas */
-#define NFC_SPARE_BUFFERS 8
-#define NFC_SPARE_LEN 0x40
-#define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
-
-/* MPC5121 NFC registers */
-#define NFC_BUF_ADDR 0x1E04
-#define NFC_FLASH_ADDR 0x1E06
-#define NFC_FLASH_CMD 0x1E08
-#define NFC_CONFIG 0x1E0A
-#define NFC_ECC_STATUS1 0x1E0C
-#define NFC_ECC_STATUS2 0x1E0E
-#define NFC_SPAS 0x1E10
-#define NFC_WRPROT 0x1E12
-#define NFC_NF_WRPRST 0x1E18
-#define NFC_CONFIG1 0x1E1A
-#define NFC_CONFIG2 0x1E1C
-#define NFC_UNLOCKSTART_BLK0 0x1E20
-#define NFC_UNLOCKEND_BLK0 0x1E22
-#define NFC_UNLOCKSTART_BLK1 0x1E24
-#define NFC_UNLOCKEND_BLK1 0x1E26
-#define NFC_UNLOCKSTART_BLK2 0x1E28
-#define NFC_UNLOCKEND_BLK2 0x1E2A
-#define NFC_UNLOCKSTART_BLK3 0x1E2C
-#define NFC_UNLOCKEND_BLK3 0x1E2E
-
-/* Bit Definitions: NFC_BUF_ADDR */
-#define NFC_RBA_MASK (7 << 0)
-#define NFC_ACTIVE_CS_SHIFT 5
-#define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
-
-/* Bit Definitions: NFC_CONFIG */
-#define NFC_BLS_UNLOCKED (1 << 1)
-
-/* Bit Definitions: NFC_CONFIG1 */
-#define NFC_ECC_4BIT (1 << 0)
-#define NFC_FULL_PAGE_DMA (1 << 1)
-#define NFC_SPARE_ONLY (1 << 2)
-#define NFC_ECC_ENABLE (1 << 3)
-#define NFC_INT_MASK (1 << 4)
-#define NFC_BIG_ENDIAN (1 << 5)
-#define NFC_RESET (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-#define NFC_PPB_32 (0 << 9)
-#define NFC_PPB_64 (1 << 9)
-#define NFC_PPB_128 (2 << 9)
-#define NFC_PPB_256 (3 << 9)
-#define NFC_PPB_MASK (3 << 9)
-#define NFC_FULL_PAGE_INT (1 << 11)
-
-/* Bit Definitions: NFC_CONFIG2 */
-#define NFC_COMMAND (1 << 0)
-#define NFC_ADDRESS (1 << 1)
-#define NFC_INPUT (1 << 2)
-#define NFC_OUTPUT (1 << 3)
-#define NFC_ID (1 << 4)
-#define NFC_STATUS (1 << 5)
-#define NFC_CMD_FAIL (1 << 15)
-#define NFC_INT (1 << 15)
-
-/* Bit Definitions: NFC_WRPROT */
-#define NFC_WPC_LOCK_TIGHT (1 << 0)
-#define NFC_WPC_LOCK (1 << 1)
-#define NFC_WPC_UNLOCK (1 << 2)
-
-struct mpc5121_nfc_prv {
- struct nand_chip chip;
- int irq;
- void __iomem *regs;
- struct clk *clk;
- uint column;
- int spareonly;
- int chipsel;
-};
-
-int mpc5121_nfc_chip = 0;
-
-static void mpc5121_nfc_done(struct mtd_info *mtd);
-
-/* Read NFC register */
-static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
-
- return in_be16(prv->regs + reg);
-}
-
-/* Write NFC register */
-static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
-
- out_be16(prv->regs + reg, val);
-}
-
-/* Set bits in NFC register */
-static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
-{
- nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
-}
-
-/* Clear bits in NFC register */
-static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
-{
- nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
-}
-
-/* Invoke address cycle */
-static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
-{
- nfc_write(mtd, NFC_FLASH_ADDR, addr);
- nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
- mpc5121_nfc_done(mtd);
-}
-
-/* Invoke command cycle */
-static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
-{
- nfc_write(mtd, NFC_FLASH_CMD, cmd);
- nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
- mpc5121_nfc_done(mtd);
-}
-
-/* Send data from NFC buffers to NAND flash */
-static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
-{
- nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
- nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
- mpc5121_nfc_done(mtd);
-}
-
-/* Receive data from NAND flash */
-static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
-{
- nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
- nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
- mpc5121_nfc_done(mtd);
-}
-
-/* Receive ID from NAND flash */
-static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
-{
- nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
- nfc_write(mtd, NFC_CONFIG2, NFC_ID);
- mpc5121_nfc_done(mtd);
-}
-
-/* Receive status from NAND flash */
-static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
-{
- nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
- nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
- mpc5121_nfc_done(mtd);
-}
-
-static void mpc5121_nfc_done(struct mtd_info *mtd)
-{
- int max_retries = NFC_TIMEOUT;
-
- while (1) {
- max_retries--;
- if (nfc_read(mtd, NFC_CONFIG2) & NFC_INT)
- break;
- udelay(1);
- }
-
- if (max_retries <= 0)
- printk(KERN_WARNING DRV_NAME
- ": Timeout while waiting for completion.\n");
-}
-
-/* Do address cycle(s) */
-static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- u32 pagemask = chip->pagemask;
-
- if (column != -1) {
- mpc5121_nfc_send_addr(mtd, column);
- if (mtd->writesize > 512)
- mpc5121_nfc_send_addr(mtd, column >> 8);
- }
-
- if (page != -1) {
- do {
- mpc5121_nfc_send_addr(mtd, page & 0xFF);
- page >>= 8;
- pagemask >>= 8;
- } while (pagemask);
- }
-}
-
-/* Control chip select signals */
-
-/*
- * Selecting the active device:
- *
- * This is different than the linux version. Switching between chips
- * is done via board_nand_select_device(). The Linux select_chip
- * function used here in U-Boot has only 2 valid chip numbers:
- * 0 select
- * -1 deselect
- */
-
-/*
- * Implement it as a weak default, so that boards with a specific
- * chip-select routine can use their own function.
- */
-void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
-{
- if (chip < 0) {
- nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
- return;
- }
-
- nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
- nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
- NFC_ACTIVE_CS_MASK);
- nfc_set(mtd, NFC_CONFIG1, NFC_CE);
-}
-void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
- __attribute__((weak, alias("__mpc5121_nfc_select_chip")));
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
- /*
- * Only save this chip number in global variable here. This
- * will be used later in mpc5121_nfc_select_chip().
- */
- mpc5121_nfc_chip = chip;
-}
-
-/* Read NAND Ready/Busy signal */
-static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
-{
- /*
- * NFC handles ready/busy signal internally. Therefore, this function
- * always returns status as ready.
- */
- return 1;
-}
-
-/* Write command to NAND flash */
-static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
- int column, int page)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
-
- prv->column = (column >= 0) ? column : 0;
- prv->spareonly = 0;
-
- switch (command) {
- case NAND_CMD_PAGEPROG:
- mpc5121_nfc_send_prog_page(mtd);
- break;
- /*
- * NFC does not support sub-page reads and writes,
- * so emulate them using full page transfers.
- */
- case NAND_CMD_READ0:
- column = 0;
- break;
-
- case NAND_CMD_READ1:
- prv->column += 256;
- command = NAND_CMD_READ0;
- column = 0;
- break;
-
- case NAND_CMD_READOOB:
- prv->spareonly = 1;
- command = NAND_CMD_READ0;
- column = 0;
- break;
-
- case NAND_CMD_SEQIN:
- mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
- column = 0;
- break;
-
- case NAND_CMD_ERASE1:
- case NAND_CMD_ERASE2:
- case NAND_CMD_READID:
- case NAND_CMD_STATUS:
- case NAND_CMD_RESET:
- break;
-
- default:
- return;
- }
-
- mpc5121_nfc_send_cmd(mtd, command);
- mpc5121_nfc_addr_cycle(mtd, column, page);
-
- switch (command) {
- case NAND_CMD_READ0:
- if (mtd->writesize > 512)
- mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
- mpc5121_nfc_send_read_page(mtd);
- break;
-
- case NAND_CMD_READID:
- mpc5121_nfc_send_read_id(mtd);
- break;
-
- case NAND_CMD_STATUS:
- mpc5121_nfc_send_read_status(mtd);
- if (chip->options & NAND_BUSWIDTH_16)
- prv->column = 1;
- else
- prv->column = 0;
- break;
- }
-}
-
-/* Copy data from/to NFC spare buffers. */
-static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
- u8 * buffer, uint size, int wr)
-{
- struct nand_chip *nand = mtd_to_nand(mtd);
- struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
- uint o, s, sbsize, blksize;
-
- /*
- * NAND spare area is available through NFC spare buffers.
- * The NFC divides spare area into (page_size / 512) chunks.
- * Each chunk is placed into separate spare memory area, using
- * first (spare_size / num_of_chunks) bytes of the buffer.
- *
- * For NAND device in which the spare area is not divided fully
- * by the number of chunks, number of used bytes in each spare
- * buffer is rounded down to the nearest even number of bytes,
- * and all remaining bytes are added to the last used spare area.
- *
- * For more information read section 26.6.10 of MPC5121e
- * Microcontroller Reference Manual, Rev. 3.
- */
-
- /* Calculate number of valid bytes in each spare buffer */
- sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
-
- while (size) {
- /* Calculate spare buffer number */
- s = offset / sbsize;
- if (s > NFC_SPARE_BUFFERS - 1)
- s = NFC_SPARE_BUFFERS - 1;
-
- /*
- * Calculate offset to requested data block in selected spare
- * buffer and its size.
- */
- o = offset - (s * sbsize);
- blksize = min(sbsize - o, size);
-
- if (wr)
- memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
- buffer, blksize);
- else
- memcpy_fromio(buffer,
- prv->regs + NFC_SPARE_AREA(s) + o,
- blksize);
-
- buffer += blksize;
- offset += blksize;
- size -= blksize;
- };
-}
-
-/* Copy data from/to NFC main and spare buffers */
-static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len,
- int wr)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
- uint c = prv->column;
- uint l;
-
- /* Handle spare area access */
- if (prv->spareonly || c >= mtd->writesize) {
- /* Calculate offset from beginning of spare area */
- if (c >= mtd->writesize)
- c -= mtd->writesize;
-
- prv->column += len;
- mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
- return;
- }
-
- /*
- * Handle main area access - limit copy length to prevent
- * crossing main/spare boundary.
- */
- l = min((uint) len, mtd->writesize - c);
- prv->column += l;
-
- if (wr)
- memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
- else
- memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
-
- /* Handle crossing main/spare boundary */
- if (l != len) {
- buf += l;
- len -= l;
- mpc5121_nfc_buf_copy(mtd, buf, len, wr);
- }
-}
-
-/* Read data from NFC buffers */
-static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char * buf, int len)
-{
- mpc5121_nfc_buf_copy(mtd, buf, len, 0);
-}
-
-/* Write data to NFC buffers */
-static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
- const u_char * buf, int len)
-{
- mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1);
-}
-
-/* Read byte from NFC buffers */
-static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
-{
- u8 tmp;
-
- mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
-
- return tmp;
-}
-
-/* Read word from NFC buffers */
-static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
-{
- u16 tmp;
-
- mpc5121_nfc_read_buf(mtd, (u_char *) & tmp, sizeof(tmp));
-
- return tmp;
-}
-
-/*
- * Read NFC configuration from Reset Config Word
- *
- * NFC is configured during reset in basis of information stored
- * in Reset Config Word. There is no other way to set NAND block
- * size, spare size and bus width.
- */
-static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- struct nand_chip *chip = mtd_to_nand(mtd);
- uint rcw_pagesize = 0;
- uint rcw_sparesize = 0;
- uint rcw_width;
- uint rcwh;
- uint romloc, ps;
-
- rcwh = in_be32(&(im->reset.rcwh));
-
- /* Bit 6: NFC bus width */
- rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
-
- /* Bit 7: NFC Page/Spare size */
- ps = (rcwh >> 7) & 0x1;
-
- /* Bits [22:21]: ROM Location */
- romloc = (rcwh >> 21) & 0x3;
-
- /* Decode RCW bits */
- switch ((ps << 2) | romloc) {
- case 0x00:
- case 0x01:
- rcw_pagesize = 512;
- rcw_sparesize = 16;
- break;
- case 0x02:
- case 0x03:
- rcw_pagesize = 4096;
- rcw_sparesize = 128;
- break;
- case 0x04:
- case 0x05:
- rcw_pagesize = 2048;
- rcw_sparesize = 64;
- break;
- case 0x06:
- case 0x07:
- rcw_pagesize = 4096;
- rcw_sparesize = 218;
- break;
- }
-
- mtd->writesize = rcw_pagesize;
- mtd->oobsize = rcw_sparesize;
- if (rcw_width == 2)
- chip->options |= NAND_BUSWIDTH_16;
-
- debug(KERN_NOTICE DRV_NAME ": Configured for "
- "%u-bit NAND, page size %u with %u spare.\n",
- rcw_width * 8, rcw_pagesize, rcw_sparesize);
- return 0;
-}
-
-int board_nand_init(struct nand_chip *chip)
-{
- struct mpc5121_nfc_prv *prv;
- struct mtd_info *mtd;
- int resettime = 0;
- int retval = 0;
- int rev;
-
- /*
- * Check SoC revision. This driver supports only NFC
- * in MPC5121 revision 2.
- */
- rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
- if (rev != 2) {
- printk(KERN_ERR DRV_NAME
- ": SoC revision %u is not supported!\n", rev);
- return -ENXIO;
- }
-
- prv = malloc(sizeof(*prv));
- if (!prv) {
- printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
- return -ENOMEM;
- }
-
- mtd = &chip->mtd;
- nand_set_controller_data(chip, prv);
-
- /* Read NFC configuration from Reset Config Word */
- retval = mpc5121_nfc_read_hw_config(mtd);
- if (retval) {
- printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n");
- return retval;
- }
-
- prv->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
- chip->dev_ready = mpc5121_nfc_dev_ready;
- chip->cmdfunc = mpc5121_nfc_command;
- chip->read_byte = mpc5121_nfc_read_byte;
- chip->read_word = mpc5121_nfc_read_word;
- chip->read_buf = mpc5121_nfc_read_buf;
- chip->write_buf = mpc5121_nfc_write_buf;
- chip->select_chip = mpc5121_nfc_select_chip;
- chip->bbt_options = NAND_BBT_USE_FLASH;
- chip->ecc.mode = NAND_ECC_SOFT;
-
- /* Reset NAND Flash controller */
- nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
- while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
- if (resettime++ >= NFC_RESET_TIMEOUT) {
- printk(KERN_ERR DRV_NAME
- ": Timeout while resetting NFC!\n");
- retval = -EINVAL;
- goto error;
- }
-
- udelay(1);
- }
-
- /* Enable write to NFC memory */
- nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
-
- /* Enable write to all NAND pages */
- nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
- nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
- nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
-
- /*
- * Setup NFC:
- * - Big Endian transfers,
- * - Interrupt after full page read/write.
- */
- nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
- NFC_FULL_PAGE_INT);
-
- /* Set spare area size */
- nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
-
- /* Detect NAND chips */
- if (nand_scan(mtd, 1)) {
- printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n");
- retval = -ENXIO;
- goto error;
- }
-
- /* Set erase block size */
- switch (mtd->erasesize / mtd->writesize) {
- case 32:
- nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
- break;
-
- case 64:
- nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
- break;
-
- case 128:
- nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
- break;
-
- case 256:
- nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
- break;
-
- default:
- printk(KERN_ERR DRV_NAME ": Unsupported NAND flash!\n");
- retval = -ENXIO;
- goto error;
- }
-
- return 0;
-error:
- return retval;
-}
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0aaac6b..03ed224 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -39,8 +39,6 @@
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
-obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
-obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
deleted file mode 100644
index a18b959..0000000
--- a/drivers/net/mpc512x_fec.c
+++ /dev/null
@@ -1,769 +0,0 @@
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Derived from the MPC8xx FEC driver.
- * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/io.h>
-#include "mpc512x_fec.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DEBUG 0
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr);
-int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr, u16 data);
-int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
-
-static uchar rx_buff[FEC_BUFFER_SIZE];
-static int rx_buff_idx = 0;
-
-/********************************************************************/
-#if (DEBUG & 0x2)
-static void mpc512x_fec_phydump (char *devname)
-{
- u16 phyStatus, i;
- u8 phyAddr = CONFIG_PHY_ADDR;
- u8 reg_mask[] = {
- /* regs to print: 0...8, 21,27,31 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
- };
-
- for (i = 0; i < 32; i++) {
- if (reg_mask[i]) {
- miiphy_read (devname, phyAddr, i, &phyStatus);
- printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
- }
- }
-}
-#endif
-
-/********************************************************************/
-static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
-{
- int ix;
-
- /*
- * Receive BDs init
- */
- for (ix = 0; ix < FEC_RBD_NUM; ix++) {
- fec->bdBase->rbd[ix].dataPointer =
- (u32)&fec->bdBase->recv_frames[ix];
- fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
- fec->bdBase->rbd[ix].dataLength = 0;
- }
-
- /*
- * have the last RBD to close the ring
- */
- fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
- fec->rbdIndex = 0;
-
- /*
- * Trasmit BDs init
- */
- for (ix = 0; ix < FEC_TBD_NUM; ix++) {
- fec->bdBase->tbd[ix].status = 0;
- }
-
- /*
- * Have the last TBD to close the ring
- */
- fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
-
- /*
- * Initialize some indices
- */
- fec->tbdIndex = 0;
- fec->usedTbdIndex = 0;
- fec->cleanTbdNum = FEC_TBD_NUM;
-
- return 0;
-}
-
-/********************************************************************/
-static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
-{
- /*
- * Reset buffer descriptor as empty
- */
- if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
- pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
- else
- pRbd->status = FEC_RBD_EMPTY;
-
- pRbd->dataLength = 0;
-
- /*
- * Increment BD count
- */
- fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
-
- /*
- * Now, we have an empty RxBD, notify FEC
- * Set Descriptor polling active
- */
- out_be32(&fec->eth->r_des_active, 0x01000000);
-}
-
-/********************************************************************/
-static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
-{
- volatile FEC_TBD *pUsedTbd;
-
-#if (DEBUG & 0x1)
- printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
- fec->cleanTbdNum, fec->usedTbdIndex);
-#endif
-
- /*
- * process all the consumed TBDs
- */
- while (fec->cleanTbdNum < FEC_TBD_NUM) {
- pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
- if (pUsedTbd->status & FEC_TBD_READY) {
-#if (DEBUG & 0x20)
- printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
-#endif
- return;
- }
-
- /*
- * clean this buffer descriptor
- */
- if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
- pUsedTbd->status = FEC_TBD_WRAP;
- else
- pUsedTbd->status = 0;
-
- /*
- * update some indeces for a correct handling of the TBD ring
- */
- fec->cleanTbdNum++;
- fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
- }
-}
-
-/********************************************************************/
-static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac)
-{
- u8 currByte; /* byte for which to compute the CRC */
- int byte; /* loop - counter */
- int bit; /* loop - counter */
- u32 crc = 0xffffffff; /* initial value */
-
- /*
- * The algorithm used is the following:
- * we loop on each of the six bytes of the provided address,
- * and we compute the CRC by left-shifting the previous
- * value by one position, so that each bit in the current
- * byte of the address may contribute the calculation. If
- * the latter and the MSB in the CRC are different, then
- * the CRC value so computed is also ex-ored with the
- * "polynomium generator". The current byte of the address
- * is also shifted right by one bit at each iteration.
- * This is because the CRC generatore in hardware is implemented
- * as a shift-register with as many ex-ores as the radixes
- * in the polynomium. This suggests that we represent the
- * polynomiumm itself as a 32-bit constant.
- */
- for (byte = 0; byte < 6; byte++) {
- currByte = mac[byte];
- for (bit = 0; bit < 8; bit++) {
- if ((currByte & 0x01) ^ (crc & 0x01)) {
- crc >>= 1;
- crc = crc ^ 0xedb88320;
- } else {
- crc >>= 1;
- }
- currByte >>= 1;
- }
- }
-
- crc = crc >> 26;
-
- /*
- * Set individual hash table register
- */
- if (crc >= 32) {
- out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
- out_be32(&fec->eth->iaddr2, 0);
- } else {
- out_be32(&fec->eth->iaddr1, 0);
- out_be32(&fec->eth->iaddr2, (1 << crc));
- }
-
- /*
- * Set physical address
- */
- out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
- (mac[2] << 8) + mac[3]);
- out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
- 0x8808);
-}
-
-/********************************************************************/
-static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
-{
- mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-
-#if (DEBUG & 0x1)
- printf ("mpc512x_fec_init... Begin\n");
-#endif
-
- mpc512x_fec_set_hwaddr (fec, dev->enetaddr);
- out_be32(&fec->eth->gaddr1, 0x00000000);
- out_be32(&fec->eth->gaddr2, 0x00000000);
-
- mpc512x_fec_init_phy (dev, bis);
-
- /* Set interrupt mask register */
- out_be32(&fec->eth->imask, 0x00000000);
-
- /* Clear FEC-Lite interrupt event register(IEVENT) */
- out_be32(&fec->eth->ievent, 0xffffffff);
-
- /* Set transmit fifo watermark register(X_WMRK), default = 64 */
- out_be32(&fec->eth->x_wmrk, 0x0);
-
- /* Set Opcode/Pause Duration Register */
- out_be32(&fec->eth->op_pause, 0x00010020);
-
- /* Frame length=1522; MII mode */
- out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
-
- /* Half-duplex, heartbeat disabled */
- out_be32(&fec->eth->x_cntrl, 0x00000000);
-
- /* Enable MIB counters */
- out_be32(&fec->eth->mib_control, 0x0);
-
- /* Setup recv fifo start and buff size */
- out_be32(&fec->eth->r_fstart, 0x500);
- out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
-
- /* Setup BD base addresses */
- out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
- out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
-
- /* DMA Control */
- out_be32(&fec->eth->dma_control, 0xc0000000);
-
- /* Enable FEC */
- setbits_be32(&fec->eth->ecntrl, 0x00000006);
-
- /* Initilize addresses and status words of BDs */
- mpc512x_fec_bd_init (fec);
-
- /* Descriptor polling active */
- out_be32(&fec->eth->r_des_active, 0x01000000);
-
-#if (DEBUG & 0x1)
- printf("mpc512x_fec_init... Done \n");
-#endif
- return 1;
-}
-
-/********************************************************************/
-int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
-{
- mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
- const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
- int timeout = 1;
- u16 phyStatus;
-
-#if (DEBUG & 0x1)
- printf ("mpc512x_fec_init_phy... Begin\n");
-#endif
-
- /*
- * Clear FEC-Lite interrupt event register(IEVENT)
- */
- out_be32(&fec->eth->ievent, 0xffffffff);
-
- /*
- * Set interrupt mask register
- */
- out_be32(&fec->eth->imask, 0x00000000);
-
- if (fec->xcv_type != SEVENWIRE) {
- /*
- * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
- * and do not drop the Preamble.
- */
- out_be32(&fec->eth->mii_speed,
- (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1);
-
- /*
- * Reset PHY, then delay 300ns
- */
- miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
- udelay (1000);
-
- if (fec->xcv_type == MII10) {
- /*
- * Force 10Base-T, FDX operation
- */
-#if (DEBUG & 0x2)
- printf ("Forcing 10 Mbps ethernet link... ");
-#endif
- miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-
- miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
-
- timeout = 20;
- do { /* wait for link status to go down */
- udelay (10000);
- if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
- printf ("hmmm, should not have waited...");
-#endif
- break;
- }
- miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
- printf ("=");
-#endif
- } while ((phyStatus & 0x0004)); /* !link up */
-
- timeout = 1000;
- do { /* wait for link status to come back up */
- udelay (10000);
- if ((timeout--) == 0) {
- printf ("failed. Link is down.\n");
- break;
- }
- miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
- printf ("+");
-#endif
- } while (!(phyStatus & 0x0004)); /* !link up */
-
-#if (DEBUG & 0x2)
- printf ("done.\n");
-#endif
- } else { /* MII100 */
- /*
- * Set the auto-negotiation advertisement register bits
- */
- miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
-
- /*
- * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
- */
- miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
-
- /*
- * Wait for AN completion
- */
- timeout = 2500;
- do {
- udelay (1000);
-
- if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
- printf ("PHY auto neg 0 failed...\n");
-#endif
- return -1;
- }
-
- if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
-#if (DEBUG & 0x2)
- printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
-#endif
- return -1;
- }
- } while (!(phyStatus & 0x0004));
-
-#if (DEBUG & 0x2)
- printf ("PHY auto neg complete! \n");
-#endif
- }
- }
-
-#if (DEBUG & 0x2)
- if (fec->xcv_type != SEVENWIRE)
- mpc512x_fec_phydump (dev->name);
-#endif
-
-#if (DEBUG & 0x1)
- printf ("mpc512x_fec_init_phy... Done \n");
-#endif
- return 1;
-}
-
-/********************************************************************/
-static void mpc512x_fec_halt (struct eth_device *dev)
-{
- mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
- int counter = 0xffff;
-
-#if (DEBUG & 0x2)
- if (fec->xcv_type != SEVENWIRE)
- mpc512x_fec_phydump (dev->name);
-#endif
-
- /*
- * mask FEC chip interrupts
- */
- out_be32(&fec->eth->imask, 0);
-
- /*
- * issue graceful stop command to the FEC transmitter if necessary
- */
- setbits_be32(&fec->eth->x_cntrl, 0x00000001);
-
- /*
- * wait for graceful stop to register
- */
- while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
- ;
-
- /*
- * Disable the Ethernet Controller
- */
- clrbits_be32(&fec->eth->ecntrl, 0x00000002);
-
- /*
- * Issue a reset command to the FEC chip
- */
- setbits_be32(&fec->eth->ecntrl, 0x1);
-
- /*
- * wait at least 16 clock cycles
- */
- udelay (10);
-#if (DEBUG & 0x3)
- printf ("Ethernet task stopped\n");
-#endif
-}
-
-/********************************************************************/
-
-static int mpc512x_fec_send(struct eth_device *dev, void *eth_data,
- int data_length)
-{
- /*
- * This routine transmits one frame. This routine only accepts
- * 6-byte Ethernet addresses.
- */
- mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
- volatile FEC_TBD *pTbd;
-
-#if (DEBUG & 0x20)
- printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
-#endif
-
- /*
- * Clear Tx BD ring at first
- */
- mpc512x_fec_tbd_scrub (fec);
-
- /*
- * Check for valid length of data.
- */
- if ((data_length > 1500) || (data_length <= 0)) {
- return -1;
- }
-
- /*
- * Check the number of vacant TxBDs.
- */
- if (fec->cleanTbdNum < 1) {
-#if (DEBUG & 0x20)
- printf ("No available TxBDs ...\n");
-#endif
- return -1;
- }
-
- /*
- * Get the first TxBD to send the mac header
- */
- pTbd = &fec->bdBase->tbd[fec->tbdIndex];
- pTbd->dataLength = data_length;
- pTbd->dataPointer = (u32)eth_data;
- pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
- fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
-
- /* Activate transmit Buffer Descriptor polling */
- out_be32(&fec->eth->x_des_active, 0x01000000);
-
-#if (DEBUG & 0x8)
- printf ( "+" );
-#endif
-
- fec->cleanTbdNum -= 1;
-
- /*
- * wait until frame is sent .
- */
- while (pTbd->status & FEC_TBD_READY) {
- udelay (10);
-#if (DEBUG & 0x8)
- printf ("TDB status = %04x\n", pTbd->status);
-#endif
- }
-
- return 0;
-}
-
-
-/********************************************************************/
-static int mpc512x_fec_recv (struct eth_device *dev)
-{
- /*
- * This command pulls one frame from the card
- */
- mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
- volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
- unsigned long ievent;
- int frame_length = 0;
-
-#if (DEBUG & 0x1)
- printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
-#endif
-#if (DEBUG & 0x8)
- printf( "-" );
-#endif
-
- /*
- * Check if any critical events have happened
- */
- ievent = in_be32(&fec->eth->ievent);
- out_be32(&fec->eth->ievent, ievent);
- if (ievent & 0x20060000) {
- /* BABT, Rx/Tx FIFO errors */
- mpc512x_fec_halt (dev);
- mpc512x_fec_init (dev, NULL);
- return 0;
- }
- if (ievent & 0x80000000) {
- /* Heartbeat error */
- setbits_be32(&fec->eth->x_cntrl, 0x00000001);
- }
- if (ievent & 0x10000000) {
- /* Graceful stop complete */
- if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
- mpc512x_fec_halt (dev);
- clrbits_be32(&fec->eth->x_cntrl, 0x00000001);
- mpc512x_fec_init (dev, NULL);
- }
- }
-
- if (!(pRbd->status & FEC_RBD_EMPTY)) {
- if (!(pRbd->status & FEC_RBD_ERR) &&
- ((pRbd->dataLength - 4) > 14)) {
-
- /*
- * Get buffer size
- */
- if (pRbd->status & FEC_RBD_LAST)
- frame_length = pRbd->dataLength - 4;
- else
- frame_length = pRbd->dataLength;
-#if (DEBUG & 0x20)
- {
- int i;
- printf ("recv data length 0x%08x data hdr: ",
- pRbd->dataLength);
- for (i = 0; i < 14; i++)
- printf ("%x ", *((u8*)pRbd->dataPointer + i));
- printf("\n");
- }
-#endif
- /*
- * Fill the buffer and pass it to upper layers
- */
- memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
- frame_length - rx_buff_idx);
- rx_buff_idx = frame_length;
-
- if (pRbd->status & FEC_RBD_LAST) {
- net_process_received_packet((uchar *)rx_buff,
- frame_length);
- rx_buff_idx = 0;
- }
- }
-
- /*
- * Reset buffer descriptor as empty
- */
- mpc512x_fec_rbd_clean (fec, pRbd);
- }
-
- /* Try to fill Buffer Descriptors */
- out_be32(&fec->eth->r_des_active, 0x01000000);
-
- return frame_length;
-}
-
-/********************************************************************/
-int mpc512x_fec_initialize (bd_t * bis)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- mpc512x_fec_priv *fec;
- struct eth_device *dev;
- void * bd;
-
- fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
- dev = (struct eth_device *) malloc (sizeof(*dev));
- memset (dev, 0, sizeof *dev);
-
- fec->eth = &im->fec;
-
-# ifndef CONFIG_FEC_10MBIT
- fec->xcv_type = MII100;
-# else
- fec->xcv_type = MII10;
-# endif
- dev->priv = (void *)fec;
- dev->iobase = (int)&im->fec;
- dev->init = mpc512x_fec_init;
- dev->halt = mpc512x_fec_halt;
- dev->send = mpc512x_fec_send;
- dev->recv = mpc512x_fec_recv;
-
- strcpy(dev->name, "FEC");
- eth_register (dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = fec512x_miiphy_read;
- mdiodev->write = fec512x_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- /* Clean up space FEC's MIB and FIFO RAM ...*/
- memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib));
- memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
-
- /*
- * Malloc space for BDs (must be quad word-aligned)
- * this pointer is lost, so cannot be freed
- */
- bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
- fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
- memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
-
- /*
- * Set interrupt mask register
- */
- out_be32(&fec->eth->imask, 0x00000000);
-
- /*
- * Clear FEC-Lite interrupt event register(IEVENT)
- */
- out_be32(&fec->eth->ievent, 0xffffffff);
-
- return 1;
-}
-
-/* MII-interface related functions */
-/********************************************************************/
-int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr)
-{
- u16 retVal = 0;
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec512x_t *eth = &im->fec;
- u32 reg; /* convenient holder for the PHY register */
- u32 phy; /* convenient holder for the PHY */
- int timeout = 0xffff;
-
- /*
- * reading from any PHY's register is done by properly
- * programming the FEC's MII data register.
- */
- reg = regAddr << FEC_MII_DATA_RA_SHIFT;
- phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
- out_be32(ð->mii_data, FEC_MII_DATA_ST |
- FEC_MII_DATA_OP_RD |
- FEC_MII_DATA_TA |
- phy | reg);
-
- /*
- * wait for the related interrupt
- */
- while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
- ;
-
- if (timeout == 0) {
-#if (DEBUG & 0x2)
- printf ("Read MDIO failed...\n");
-#endif
- return -1;
- }
-
- /*
- * clear mii interrupt bit
- */
- out_be32(ð->ievent, 0x00800000);
-
- /*
- * it's now safe to read the PHY's register
- */
- retVal = (u16) in_be32(ð->mii_data);
-
- return retVal;
-}
-
-/********************************************************************/
-int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr, u16 data)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec512x_t *eth = &im->fec;
- u32 reg; /* convenient holder for the PHY register */
- u32 phy; /* convenient holder for the PHY */
- int timeout = 0xffff;
-
- reg = regAddr << FEC_MII_DATA_RA_SHIFT;
- phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
- out_be32(ð->mii_data, FEC_MII_DATA_ST |
- FEC_MII_DATA_OP_WR |
- FEC_MII_DATA_TA |
- phy | reg | data);
-
- /*
- * wait for the MII interrupt
- */
- while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
- ;
-
- if (timeout == 0) {
-#if (DEBUG & 0x2)
- printf ("Write MDIO failed...\n");
-#endif
- return -1;
- }
-
- /*
- * clear MII interrupt bit
- */
- out_be32(ð->ievent, 0x00800000);
-
- return 0;
-}
diff --git a/drivers/net/mpc512x_fec.h b/drivers/net/mpc512x_fec.h
deleted file mode 100644
index a083cca..0000000
--- a/drivers/net/mpc512x_fec.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2003 - 2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Derived from the MPC8xx driver's header file.
- */
-
-#ifndef __MPC512X_FEC_H
-#define __MPC512X_FEC_H
-
-#include <common.h>
-
-/* Receive & Transmit Buffer Descriptor definitions */
-typedef struct BufferDescriptor {
- u16 status;
- u16 dataLength;
- u32 dataPointer;
-} FEC_RBD;
-
-typedef struct {
- u16 status;
- u16 dataLength;
- u32 dataPointer;
-} FEC_TBD;
-
-/* private structure */
-typedef enum {
- SEVENWIRE, /* 7-wire */
- MII10, /* MII 10Mbps */
- MII100 /* MII 100Mbps */
-} xceiver_type;
-
-/* BD Numer definitions */
-#define FEC_TBD_NUM 48 /* The user can adjust this value */
-#define FEC_RBD_NUM 32 /* The user can adjust this value */
-
-/* packet size limit */
-#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
-
-/* Buffer size must be evenly divisible by 16 */
-#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
-
-typedef struct {
- u8 frame[FEC_BUFFER_SIZE];
-} mpc512x_frame;
-
-typedef struct {
- FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
- FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
- mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
-} mpc512x_buff_descs;
-
-typedef struct {
- volatile fec512x_t *eth;
- xceiver_type xcv_type; /* transceiver type */
- mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
- u16 rbdIndex; /* next receive BD to read */
- u16 tbdIndex; /* next transmit BD to send */
- u16 usedTbdIndex; /* next transmit BD to clean */
- u16 cleanTbdNum; /* the number of available transmit BDs */
-} mpc512x_fec_priv;
-
-/* RBD bits definitions */
-#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
-#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
-#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
-#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
-#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
-#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
-#define FEC_RBD_LG 0x0020 /* Frame length violation */
-#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
-#define FEC_RBD_SH 0x0008 /* Short frame */
-#define FEC_RBD_CR 0x0004 /* CRC error */
-#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
-#define FEC_RBD_TR 0x0001 /* Frame is truncated */
-#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
- FEC_RBD_OV | FEC_RBD_TR)
-
-/* TBD bits definitions */
-#define FEC_TBD_READY 0x8000 /* Buffer is ready */
-#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
-#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
-#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
-#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
-
-/* MII-related definitios */
-#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
-#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
-#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
-#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
-#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
-#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
-#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
-
-#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
-#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
-
-#endif /* __MPC512X_FEC_H */
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
deleted file mode 100644
index d75e858..0000000
--- a/drivers/net/mpc5xxx_fec.c
+++ /dev/null
@@ -1,1031 +0,0 @@
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on mpc4200fec.c,
- * (C) Copyright Motorola, Inc., 2000
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <mpc5xxx_sdma.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include "mpc5xxx_fec.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* #define DEBUG 0x28 */
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#if (DEBUG & 0x60)
-static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
-static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
-#endif /* DEBUG */
-
-typedef struct {
- uint8 data[1500]; /* actual data */
- int length; /* actual length */
- int used; /* buffer in use or not */
- uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
-} NBUF;
-
-int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr);
-int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr, u16 data);
-
-static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
-
-/********************************************************************/
-#if (DEBUG & 0x2)
-static void mpc5xxx_fec_phydump (char *devname)
-{
- uint16 phyStatus, i;
- uint8 phyAddr = CONFIG_PHY_ADDR;
- uint8 reg_mask[] = {
-#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
- /* regs to print: 0...7, 16...19, 21, 23, 24 */
- 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
-#else
- /* regs to print: 0...8, 16...20 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-#endif
- };
-
- for (i = 0; i < 32; i++) {
- if (reg_mask[i]) {
- miiphy_read(devname, phyAddr, i, &phyStatus);
- printf("Mii reg %d: 0x%04x\n", i, phyStatus);
- }
- }
-}
-#endif
-
-/********************************************************************/
-static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
-{
- int ix;
- char *data;
- static int once = 0;
-
- for (ix = 0; ix < FEC_RBD_NUM; ix++) {
- if (!once) {
- data = (char *)malloc(FEC_MAX_PKT_SIZE);
- if (data == NULL) {
- printf ("RBD INIT FAILED\n");
- return -1;
- }
- fec->rbdBase[ix].dataPointer = (uint32)data;
- }
- fec->rbdBase[ix].status = FEC_RBD_EMPTY;
- fec->rbdBase[ix].dataLength = 0;
- }
- once ++;
-
- /*
- * have the last RBD to close the ring
- */
- fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
- fec->rbdIndex = 0;
-
- return 0;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
-{
- int ix;
-
- for (ix = 0; ix < FEC_TBD_NUM; ix++) {
- fec->tbdBase[ix].status = 0;
- }
-
- /*
- * Have the last TBD to close the ring
- */
- fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
-
- /*
- * Initialize some indices
- */
- fec->tbdIndex = 0;
- fec->usedTbdIndex = 0;
- fec->cleanTbdNum = FEC_TBD_NUM;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
-{
- /*
- * Reset buffer descriptor as empty
- */
- if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
- pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
- else
- pRbd->status = FEC_RBD_EMPTY;
-
- pRbd->dataLength = 0;
-
- /*
- * Now, we have an empty RxBD, restart the SmartDMA receive task
- */
- SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
-
- /*
- * Increment BD count
- */
- fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
-{
- volatile FEC_TBD *pUsedTbd;
-
-#if (DEBUG & 0x1)
- printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
- fec->cleanTbdNum, fec->usedTbdIndex);
-#endif
-
- /*
- * process all the consumed TBDs
- */
- while (fec->cleanTbdNum < FEC_TBD_NUM) {
- pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
- if (pUsedTbd->status & FEC_TBD_READY) {
-#if (DEBUG & 0x20)
- printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
-#endif
- return;
- }
-
- /*
- * clean this buffer descriptor
- */
- if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
- pUsedTbd->status = FEC_TBD_WRAP;
- else
- pUsedTbd->status = 0;
-
- /*
- * update some indeces for a correct handling of the TBD ring
- */
- fec->cleanTbdNum++;
- fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
- }
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
-{
- uint8 currByte; /* byte for which to compute the CRC */
- int byte; /* loop - counter */
- int bit; /* loop - counter */
- uint32 crc = 0xffffffff; /* initial value */
-
- /*
- * The algorithm used is the following:
- * we loop on each of the six bytes of the provided address,
- * and we compute the CRC by left-shifting the previous
- * value by one position, so that each bit in the current
- * byte of the address may contribute the calculation. If
- * the latter and the MSB in the CRC are different, then
- * the CRC value so computed is also ex-ored with the
- * "polynomium generator". The current byte of the address
- * is also shifted right by one bit at each iteration.
- * This is because the CRC generatore in hardware is implemented
- * as a shift-register with as many ex-ores as the radixes
- * in the polynomium. This suggests that we represent the
- * polynomiumm itself as a 32-bit constant.
- */
- for (byte = 0; byte < 6; byte++) {
- currByte = mac[byte];
- for (bit = 0; bit < 8; bit++) {
- if ((currByte & 0x01) ^ (crc & 0x01)) {
- crc >>= 1;
- crc = crc ^ 0xedb88320;
- } else {
- crc >>= 1;
- }
- currByte >>= 1;
- }
- }
-
- crc = crc >> 26;
-
- /*
- * Set individual hash table register
- */
- if (crc >= 32) {
- fec->eth->iaddr1 = (1 << (crc - 32));
- fec->eth->iaddr2 = 0;
- } else {
- fec->eth->iaddr1 = 0;
- fec->eth->iaddr2 = (1 << crc);
- }
-
- /*
- * Set physical address
- */
- fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
- fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
-}
-
-/********************************************************************/
-static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
-{
- mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
- struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-
-#if (DEBUG & 0x1)
- printf ("mpc5xxx_fec_init... Begin\n");
-#endif
-
- mpc5xxx_fec_init_phy(dev, bis);
-
- /*
- * Call board-specific PHY fixups (if any)
- */
-#ifdef CONFIG_RESET_PHY_R
- reset_phy();
-#endif
-
- /*
- * Initialize RxBD/TxBD rings
- */
- mpc5xxx_fec_rbd_init(fec);
- mpc5xxx_fec_tbd_init(fec);
-
- /*
- * Clear FEC-Lite interrupt event register(IEVENT)
- */
- fec->eth->ievent = 0xffffffff;
-
- /*
- * Set interrupt mask register
- */
- fec->eth->imask = 0x00000000;
-
- /*
- * Set FEC-Lite receive control register(R_CNTRL):
- */
- if (fec->xcv_type == SEVENWIRE) {
- /*
- * Frame length=1518; 7-wire mode
- */
- fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
- } else {
- /*
- * Frame length=1518; MII mode;
- */
- fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
- }
-
- fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
-
- /*
- * Set Opcode/Pause Duration Register
- */
- fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
-
- /*
- * Set Rx FIFO alarm and granularity value
- */
- fec->eth->rfifo_cntrl = 0x0c000000
- | (fec->eth->rfifo_cntrl & ~0x0f000000);
- fec->eth->rfifo_alarm = 0x0000030c;
-#if (DEBUG & 0x22)
- if (fec->eth->rfifo_status & 0x00700000 ) {
- printf("mpc5xxx_fec_init() RFIFO error\n");
- }
-#endif
-
- /*
- * Set Tx FIFO granularity value
- */
- fec->eth->tfifo_cntrl = 0x0c000000
- | (fec->eth->tfifo_cntrl & ~0x0f000000);
-#if (DEBUG & 0x2)
- printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
- printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
-#endif
-
- /*
- * Set transmit fifo watermark register(X_WMRK), default = 64
- */
- fec->eth->tfifo_alarm = 0x00000080;
- fec->eth->x_wmrk = 0x2;
-
- /*
- * Set individual address filter for unicast address
- * and set physical address registers.
- */
- mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
-
- /*
- * Set multicast address filter
- */
- fec->eth->gaddr1 = 0x00000000;
- fec->eth->gaddr2 = 0x00000000;
-
- /*
- * Turn ON cheater FSM: ????
- */
- fec->eth->xmit_fsm = 0x03000000;
-
- /*
- * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
- * work w/ the current receive task.
- */
- sdma->PtdCntrl |= 0x00000001;
-
- /*
- * Set priority of different initiators
- */
- sdma->IPR0 = 7; /* always */
- sdma->IPR3 = 6; /* Eth RX */
- sdma->IPR4 = 5; /* Eth Tx */
-
- /*
- * Clear SmartDMA task interrupt pending bits
- */
- SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
-
- /*
- * Initialize SmartDMA parameters stored in SRAM
- */
- *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
- *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
- *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
- *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
-
- /*
- * Enable FEC-Lite controller
- */
- fec->eth->ecntrl |= 0x00000006;
-
-#if (DEBUG & 0x2)
- if (fec->xcv_type != SEVENWIRE)
- mpc5xxx_fec_phydump (dev->name);
-#endif
-
- /*
- * Enable SmartDMA receive task
- */
- SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
-
-#if (DEBUG & 0x1)
- printf("mpc5xxx_fec_init... Done \n");
-#endif
-
- return 1;
-}
-
-/********************************************************************/
-static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
-{
- mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
- const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
- static int initialized = 0;
-
- if(initialized)
- return 0;
- initialized = 1;
-
-#if (DEBUG & 0x1)
- printf ("mpc5xxx_fec_init_phy... Begin\n");
-#endif
-
- /*
- * Initialize GPIO pins
- */
- if (fec->xcv_type == SEVENWIRE) {
- /* 10MBit with 7-wire operation */
- /* 7-wire only */
- *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
- } else {
- /* 100MBit with MD operation */
- *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
- }
-
- /*
- * Clear FEC-Lite interrupt event register(IEVENT)
- */
- fec->eth->ievent = 0xffffffff;
-
- /*
- * Set interrupt mask register
- */
- fec->eth->imask = 0x00000000;
-
-/*
- * In original Promess-provided code PHY initialization is disabled with the
- * following comment: "Phy initialization is DISABLED for now. There was a
- * problem with running 100 Mbps on PRO board". Thus we temporarily disable
- * PHY initialization for the Motion-PRO board, until a proper fix is found.
- */
-
- if (fec->xcv_type != SEVENWIRE) {
- /*
- * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
- * and do not drop the Preamble.
- * No MII for 7-wire mode
- */
- fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
- }
-
- if (fec->xcv_type != SEVENWIRE) {
- /*
- * Initialize PHY(LXT971A):
- *
- * Generally, on power up, the LXT971A reads its configuration
- * pins to check for forced operation, If not cofigured for
- * forced operation, it uses auto-negotiation/parallel detection
- * to automatically determine line operating conditions.
- * If the PHY device on the other side of the link supports
- * auto-negotiation, the LXT971A auto-negotiates with it
- * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
- * support auto-negotiation, the LXT971A automatically detects
- * the presence of either link pulses(10Mbps PHY) or Idle
- * symbols(100Mbps) and sets its operating conditions accordingly.
- *
- * When auto-negotiation is controlled by software, the following
- * steps are recommended.
- *
- * Note:
- * The physical address is dependent on hardware configuration.
- *
- */
- int timeout = 1;
- uint16 phyStatus;
-
- /*
- * Reset PHY, then delay 300ns
- */
- miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
- udelay(1000);
-
- if (fec->xcv_type == MII10) {
- /*
- * Force 10Base-T, FDX operation
- */
-#if (DEBUG & 0x2)
- printf("Forcing 10 Mbps ethernet link... ");
-#endif
- miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
- /*
- miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
- */
- miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
-
- timeout = 20;
- do { /* wait for link status to go down */
- udelay(10000);
- if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
- printf("hmmm, should not have waited...");
-#endif
- break;
- }
- miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
- printf("=");
-#endif
- } while ((phyStatus & 0x0004)); /* !link up */
-
- timeout = 1000;
- do { /* wait for link status to come back up */
- udelay(10000);
- if ((timeout--) == 0) {
- printf("failed. Link is down.\n");
- break;
- }
- miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
- printf("+");
-#endif
- } while (!(phyStatus & 0x0004)); /* !link up */
-
-#if (DEBUG & 0x2)
- printf ("done.\n");
-#endif
- } else { /* MII100 */
- /*
- * Set the auto-negotiation advertisement register bits
- */
- miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
-
- /*
- * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
- */
- miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
-
- /*
- * Wait for AN completion
- */
- timeout = 5000;
- do {
- udelay(1000);
-
- if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
- printf("PHY auto neg 0 failed...\n");
-#endif
- return -1;
- }
-
- if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
-#if (DEBUG & 0x2)
- printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
-#endif
- return -1;
- }
- } while (!(phyStatus & 0x0004));
-
-#if (DEBUG & 0x2)
- printf("PHY auto neg complete! \n");
-#endif
- }
-
- }
-
-#if (DEBUG & 0x2)
- if (fec->xcv_type != SEVENWIRE)
- mpc5xxx_fec_phydump (dev->name);
-#endif
-
-
-#if (DEBUG & 0x1)
- printf("mpc5xxx_fec_init_phy... Done \n");
-#endif
-
- return 1;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_halt(struct eth_device *dev)
-{
- struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
- mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
- int counter = 0xffff;
-
-#if (DEBUG & 0x2)
- if (fec->xcv_type != SEVENWIRE)
- mpc5xxx_fec_phydump (dev->name);
-#endif
-
- /*
- * mask FEC chip interrupts
- */
- fec->eth->imask = 0;
-
- /*
- * issue graceful stop command to the FEC transmitter if necessary
- */
- fec->eth->x_cntrl |= 0x00000001;
-
- /*
- * wait for graceful stop to register
- */
- while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
-
- /*
- * Disable SmartDMA tasks
- */
- SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
- SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
-
- /*
- * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
- * done. It doesn't work w/ the current receive task.
- */
- sdma->PtdCntrl &= ~0x00000001;
-
- /*
- * Disable the Ethernet Controller
- */
- fec->eth->ecntrl &= 0xfffffffd;
-
- /*
- * Clear FIFO status registers
- */
- fec->eth->rfifo_status &= 0x00700000;
- fec->eth->tfifo_status &= 0x00700000;
-
- fec->eth->reset_cntrl = 0x01000000;
-
- /*
- * Issue a reset command to the FEC chip
- */
- fec->eth->ecntrl |= 0x1;
-
- /*
- * wait at least 16 clock cycles
- */
- udelay(10);
-
- /* don't leave the MII speed set to zero */
- if (fec->xcv_type != SEVENWIRE) {
- /*
- * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
- * and do not drop the Preamble.
- * No MII for 7-wire mode
- */
- fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
- }
-
-#if (DEBUG & 0x3)
- printf("Ethernet task stopped\n");
-#endif
-}
-
-#if (DEBUG & 0x60)
-/********************************************************************/
-
-static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
-{
- uint16 phyAddr = CONFIG_PHY_ADDR;
- uint16 phyStatus;
-
- if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
- || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
-
- miiphy_read(devname, phyAddr, 0x1, &phyStatus);
- printf("\nphyStatus: 0x%04x\n", phyStatus);
- printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
- printf("ievent: 0x%08x\n", fec->eth->ievent);
- printf("x_status: 0x%08x\n", fec->eth->x_status);
- printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
-
- printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
- printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
- printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
- printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
- printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
- printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
- }
-}
-
-static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
-{
- uint16 phyAddr = CONFIG_PHY_ADDR;
- uint16 phyStatus;
-
- if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
- || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
-
- miiphy_read(devname, phyAddr, 0x1, &phyStatus);
- printf("\nphyStatus: 0x%04x\n", phyStatus);
- printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
- printf("ievent: 0x%08x\n", fec->eth->ievent);
- printf("x_status: 0x%08x\n", fec->eth->x_status);
- printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
-
- printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
- printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
- printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
- printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
- printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
- printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
- }
-}
-#endif /* DEBUG */
-
-/********************************************************************/
-
-static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
- int data_length)
-{
- /*
- * This routine transmits one frame. This routine only accepts
- * 6-byte Ethernet addresses.
- */
- mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
- volatile FEC_TBD *pTbd;
-
-#if (DEBUG & 0x20)
- printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
- tfifo_print(dev->name, fec);
-#endif
-
- /*
- * Clear Tx BD ring at first
- */
- mpc5xxx_fec_tbd_scrub(fec);
-
- /*
- * Check for valid length of data.
- */
- if ((data_length > 1500) || (data_length <= 0)) {
- return -1;
- }
-
- /*
- * Check the number of vacant TxBDs.
- */
- if (fec->cleanTbdNum < 1) {
-#if (DEBUG & 0x20)
- printf("No available TxBDs ...\n");
-#endif
- return -1;
- }
-
- /*
- * Get the first TxBD to send the mac header
- */
- pTbd = &fec->tbdBase[fec->tbdIndex];
- pTbd->dataLength = data_length;
- pTbd->dataPointer = (uint32)eth_data;
- pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
- fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
-
-#if (DEBUG & 0x100)
- printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
-#endif
-
- /*
- * Kick the MII i/f
- */
- if (fec->xcv_type != SEVENWIRE) {
- uint16 phyStatus;
- miiphy_read(dev->name, 0, 0x1, &phyStatus);
- }
-
- /*
- * Enable SmartDMA transmit task
- */
-
-#if (DEBUG & 0x20)
- tfifo_print(dev->name, fec);
-#endif
- SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
-#if (DEBUG & 0x20)
- tfifo_print(dev->name, fec);
-#endif
-#if (DEBUG & 0x8)
- printf( "+" );
-#endif
-
- fec->cleanTbdNum -= 1;
-
-#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
- printf ("smartDMA ethernet Tx task enabled\n");
-#endif
- /*
- * wait until frame is sent .
- */
- while (pTbd->status & FEC_TBD_READY) {
- udelay(10);
-#if (DEBUG & 0x8)
- printf ("TDB status = %04x\n", pTbd->status);
-#endif
- }
-
- return 0;
-}
-
-
-/********************************************************************/
-static int mpc5xxx_fec_recv(struct eth_device *dev)
-{
- /*
- * This command pulls one frame from the card
- */
- mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
- volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
- unsigned long ievent;
- int frame_length, len = 0;
- NBUF *frame;
- uchar buff[FEC_MAX_PKT_SIZE];
-
-#if (DEBUG & 0x1)
- printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
-#endif
-#if (DEBUG & 0x8)
- printf( "-" );
-#endif
-
- /*
- * Check if any critical events have happened
- */
- ievent = fec->eth->ievent;
- fec->eth->ievent = ievent;
- if (ievent & 0x20060000) {
- /* BABT, Rx/Tx FIFO errors */
- mpc5xxx_fec_halt(dev);
- mpc5xxx_fec_init(dev, NULL);
- return 0;
- }
- if (ievent & 0x80000000) {
- /* Heartbeat error */
- fec->eth->x_cntrl |= 0x00000001;
- }
- if (ievent & 0x10000000) {
- /* Graceful stop complete */
- if (fec->eth->x_cntrl & 0x00000001) {
- mpc5xxx_fec_halt(dev);
- fec->eth->x_cntrl &= ~0x00000001;
- mpc5xxx_fec_init(dev, NULL);
- }
- }
-
- if (!(pRbd->status & FEC_RBD_EMPTY)) {
- if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
- ((pRbd->dataLength - 4) > 14)) {
-
- /*
- * Get buffer address and size
- */
- frame = (NBUF *)pRbd->dataPointer;
- frame_length = pRbd->dataLength - 4;
-
-#if (DEBUG & 0x20)
- {
- int i;
- printf("recv data hdr:");
- for (i = 0; i < 14; i++)
- printf("%x ", *(frame->head + i));
- printf("\n");
- }
-#endif
- /*
- * Fill the buffer and pass it to upper layers
- */
- memcpy(buff, frame->head, 14);
- memcpy(buff + 14, frame->data, frame_length);
- net_process_received_packet(buff, frame_length);
- len = frame_length;
- }
- /*
- * Reset buffer descriptor as empty
- */
- mpc5xxx_fec_rbd_clean(fec, pRbd);
- }
- SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
- return len;
-}
-
-
-/********************************************************************/
-int mpc5xxx_fec_initialize(bd_t * bis)
-{
- mpc5xxx_fec_priv *fec;
- struct eth_device *dev;
- char *tmp, *end;
- char env_enetaddr[6];
- int i;
-
- fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
- dev = (struct eth_device *)malloc(sizeof(*dev));
- memset(dev, 0, sizeof *dev);
-
- fec->eth = (ethernet_regs *)MPC5XXX_FEC;
- fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
- fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_MPC5xxx_FEC_MII100)
- fec->xcv_type = MII100;
-#elif defined(CONFIG_MPC5xxx_FEC_MII10)
- fec->xcv_type = MII10;
-#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
- fec->xcv_type = SEVENWIRE;
-#else
-#error fec->xcv_type not initialized.
-#endif
- if (fec->xcv_type != SEVENWIRE) {
- /*
- * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
- * and do not drop the Preamble.
- * No MII for 7-wire mode
- */
- fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
- }
-
- dev->priv = (void *)fec;
- dev->iobase = MPC5XXX_FEC;
- dev->init = mpc5xxx_fec_init;
- dev->halt = mpc5xxx_fec_halt;
- dev->send = mpc5xxx_fec_send;
- dev->recv = mpc5xxx_fec_recv;
-
- strcpy(dev->name, "FEC");
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = fec5xxx_miiphy_read;
- mdiodev->write = fec5xxx_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- /*
- * Try to set the mac address now. The fec mac address is
- * a garbage after reset. When not using fec for booting
- * the Linux fec driver will try to work with this garbage.
- */
- tmp = getenv("ethaddr");
- if (tmp) {
- for (i=0; i<6; i++) {
- env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end+1 : end;
- }
- mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
- }
-
- return 1;
-}
-
-/* MII-interface related functions */
-/********************************************************************/
-int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr)
-{
- uint16 retVal = 0;
- ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
- uint32 reg; /* convenient holder for the PHY register */
- uint32 phy; /* convenient holder for the PHY */
- int timeout = 0xffff;
-
- /*
- * reading from any PHY's register is done by properly
- * programming the FEC's MII data register.
- */
- reg = regAddr << FEC_MII_DATA_RA_SHIFT;
- phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
- eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
-
- /*
- * wait for the related interrupt
- */
- while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
-
- if (timeout == 0) {
-#if (DEBUG & 0x2)
- printf ("Read MDIO failed...\n");
-#endif
- return -1;
- }
-
- /*
- * clear mii interrupt bit
- */
- eth->ievent = 0x00800000;
-
- /*
- * it's now safe to read the PHY's register
- */
- retVal = (uint16) eth->mii_data;
-
- return retVal;
-}
-
-/********************************************************************/
-int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
- int regAddr, u16 data)
-{
- ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
- uint32 reg; /* convenient holder for the PHY register */
- uint32 phy; /* convenient holder for the PHY */
- int timeout = 0xffff;
-
- reg = regAddr << FEC_MII_DATA_RA_SHIFT;
- phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
- eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
- FEC_MII_DATA_TA | phy | reg | data);
-
- /*
- * wait for the MII interrupt
- */
- while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
-
- if (timeout == 0) {
-#if (DEBUG & 0x2)
- printf ("Write MDIO failed...\n");
-#endif
- return -1;
- }
-
- /*
- * clear MII interrupt bit
- */
- eth->ievent = 0x00800000;
-
- return 0;
-}
diff --git a/drivers/net/mpc5xxx_fec.h b/drivers/net/mpc5xxx_fec.h
deleted file mode 100644
index 16c3e8e..0000000
--- a/drivers/net/mpc5xxx_fec.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on mpc4200fec.h
- * (C) Copyright Motorola, Inc., 2000
- *
- * odin ethernet header file
- */
-
-#ifndef __MPC5XXX_FEC_H
-#define __MPC5XXX_FEC_H
-
-typedef unsigned long uint32;
-typedef unsigned short uint16;
-typedef unsigned char uint8;
-
-typedef struct ethernet_register_set {
-
-/* [10:2]addr = 00 */
-
-/* Control and status Registers (offset 000-1FF) */
-
- volatile uint32 fec_id; /* MBAR_ETH + 0x000 */
- volatile uint32 ievent; /* MBAR_ETH + 0x004 */
- volatile uint32 imask; /* MBAR_ETH + 0x008 */
-
- volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
- volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
- volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
- volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */
- volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */
- volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */
- volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
-
- volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */
- volatile uint32 mii_data; /* MBAR_ETH + 0x040 */
- volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */
- volatile uint32 mii_status; /* MBAR_ETH + 0x048 */
-
- volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */
- volatile uint32 mib_data; /* MBAR_ETH + 0x060 */
- volatile uint32 mib_control; /* MBAR_ETH + 0x064 */
-
- volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */
- volatile uint32 r_activate; /* MBAR_ETH + 0x080 */
- volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
- volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
- volatile uint32 r_data; /* MBAR_ETH + 0x08C */
- volatile uint32 ar_done; /* MBAR_ETH + 0x090 */
- volatile uint32 r_test; /* MBAR_ETH + 0x094 */
- volatile uint32 r_mib; /* MBAR_ETH + 0x098 */
- volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */
- volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */
-
- volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */
- volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */
- volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
- volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */
- volatile uint32 x_data; /* MBAR_ETH + 0x0CC */
- volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */
- volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */
- volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */
- volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */
- volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */
- volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
- volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
- volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */
-
- volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */
- volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */
- volatile uint32 context_reg; /* MBAR_ETH + 0x104 */
- volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */
- volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */
- volatile uint32 ones; /* MBAR_ETH + 0x110 */
- volatile uint32 zeros; /* MBAR_ETH + 0x114 */
- volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */
- volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */
- volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */
- volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */
- volatile uint32 random; /* MBAR_ETH + 0x128 */
- volatile uint32 rand1; /* MBAR_ETH + 0x12C */
- volatile uint32 tmp; /* MBAR_ETH + 0x130 */
-
- volatile uint32 RES6[3]; /* MBAR_ETH + 0x134-13C */
- volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */
- volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */
- volatile uint32 fcntrl; /* MBAR_ETH + 0x148 */
- volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
- volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
- volatile uint32 r_count; /* MBAR_ETH + 0x154 */
- volatile uint32 r_lag; /* MBAR_ETH + 0x158 */
- volatile uint32 r_read; /* MBAR_ETH + 0x15C */
- volatile uint32 r_write; /* MBAR_ETH + 0x160 */
- volatile uint32 x_count; /* MBAR_ETH + 0x164 */
- volatile uint32 x_lag; /* MBAR_ETH + 0x168 */
- volatile uint32 x_retry; /* MBAR_ETH + 0x16C */
- volatile uint32 x_write; /* MBAR_ETH + 0x170 */
- volatile uint32 x_read; /* MBAR_ETH + 0x174 */
-
- volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */
- volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */
- volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */
- volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */
- volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */
- volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */
- volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */
- volatile uint32 rfifo_alarm; /* MBAR_ETH + 0x198 */
- volatile uint32 rfifo_rdptr; /* MBAR_ETH + 0x19C */
- volatile uint32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */
- volatile uint32 tfifo_data; /* MBAR_ETH + 0x1A4 */
- volatile uint32 tfifo_status; /* MBAR_ETH + 0x1A8 */
- volatile uint32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */
- volatile uint32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */
- volatile uint32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */
- volatile uint32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */
- volatile uint32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */
- volatile uint32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */
-
- volatile uint32 reset_cntrl; /* MBAR_ETH + 0x1C4 */
- volatile uint32 xmit_fsm; /* MBAR_ETH + 0x1C8 */
-
- volatile uint32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */
- volatile uint32 rdes_data0; /* MBAR_ETH + 0x1D8 */
- volatile uint32 rdes_data1; /* MBAR_ETH + 0x1DC */
- volatile uint32 r_length; /* MBAR_ETH + 0x1E0 */
- volatile uint32 x_length; /* MBAR_ETH + 0x1E4 */
- volatile uint32 x_addr; /* MBAR_ETH + 0x1E8 */
- volatile uint32 cdes_data; /* MBAR_ETH + 0x1EC */
- volatile uint32 status; /* MBAR_ETH + 0x1F0 */
- volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */
- volatile uint32 des_cmnd; /* MBAR_ETH + 0x1F8 */
- volatile uint32 data; /* MBAR_ETH + 0x1FC */
-
-/* MIB COUNTERS (Offset 200-2FF) */
-
- volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */
- volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */
- volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
- volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
- volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */
- volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */
- volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */
- volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */
- volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */
- volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */
- volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */
- volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */
- volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */
- volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */
- volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
- volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
- volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
- volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */
- volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */
- volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
- volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */
- volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */
- volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */
- volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */
- volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */
- volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */
- volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */
- volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */
- volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */
- volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
-
- volatile uint32 RES9[2]; /* MBAR_ETH + 0x278-27C */
- volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */
- volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */
- volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
- volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
- volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */
- volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */
- volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */
- volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */
- volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */
-
- volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
-
- volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */
- volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
- volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
- volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
- volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
- volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
- volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
- volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */
- volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */
- volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
- volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */
- volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */
- volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */
- volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */
- volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
-
- volatile uint32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */
-
- volatile uint32 RES11[64]; /* MBAR_ETH + 0x300-3FF */
-} ethernet_regs;
-
-/* Receive & Transmit Buffer Descriptor definitions */
-typedef struct BufferDescriptor {
- uint16 status;
- uint16 dataLength;
- uint32 dataPointer;
-} FEC_RBD;
-typedef struct {
- uint16 status;
- uint16 dataLength;
- uint32 dataPointer;
-} FEC_TBD;
-
-/* private structure */
-typedef enum {
- SEVENWIRE, /* 7-wire */
- MII10, /* MII 10Mbps */
- MII100 /* MII 100Mbps */
-} xceiver_type;
-
-typedef struct {
- ethernet_regs *eth;
- xceiver_type xcv_type; /* transceiver type */
- FEC_RBD *rbdBase; /* RBD ring */
- FEC_TBD *tbdBase; /* TBD ring */
- uint16 rbdIndex; /* next receive BD to read */
- uint16 tbdIndex; /* next transmit BD to send */
- uint16 usedTbdIndex; /* next transmit BD to clean */
- uint16 cleanTbdNum; /* the number of available transmit BDs */
-} mpc5xxx_fec_priv;
-
-/* Ethernet parameter area */
-#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00)
-#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04)
-#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08)
-#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c)
-
-/* BD Numer definitions */
-#define FEC_TBD_NUM 48 /* The user can adjust this value */
-#define FEC_RBD_NUM 32 /* The user can adjust this value */
-
-/* packet size limit */
-#define FEC_MAX_PKT_SIZE 1536
-
-/* RBD bits definitions */
-#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
-#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
-#define FEC_RBD_INT 0x1000 /* Interrupt */
-#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
-#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
-#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
-#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
-#define FEC_RBD_LG 0x0020 /* Frame length violation */
-#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
-#define FEC_RBD_SH 0x0008 /* Short frame */
-#define FEC_RBD_CR 0x0004 /* CRC error */
-#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
-#define FEC_RBD_TR 0x0001 /* Frame is truncated */
-#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
- FEC_RBD_OV | FEC_RBD_TR)
-
-/* TBD bits definitions */
-#define FEC_TBD_READY 0x8000 /* Buffer is ready */
-#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
-#define FEC_TBD_INT 0x1000 /* Interrupt */
-#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
-#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
-#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
-
-/* MII-related definitios */
-#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
-#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
-#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
-#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
-#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
-#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
-#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
-
-#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
-#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
-
-#endif /* __MPC5XXX_FEC_H */
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 3bc918c1..003e31a 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -38,7 +38,6 @@
obj-$(CONFIG_RTC_MCP79411) += ds1307.o
obj-$(CONFIG_MCFRTC) += mcfrtc.o
obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
-obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
obj-$(CONFIG_RTC_MV) += mvrtc.o
obj-$(CONFIG_RTC_MX27) += mx27rtc.o
obj-$(CONFIG_RTC_MXS) += mxsrtc.o
diff --git a/drivers/rtc/mpc5xxx.c b/drivers/rtc/mpc5xxx.c
deleted file mode 100644
index 929783e..0000000
--- a/drivers/rtc/mpc5xxx.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2004
- * Reinhard Meyer, EMK Elektronik GmbH
- * r.meyer@emk-elektronik.de
- * www.emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*****************************************************************************
- * Date & Time support for internal RTC of MPC52xx
- *****************************************************************************/
-/*#define DEBUG*/
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-/*****************************************************************************
- * this structure should be defined in mpc5200.h ...
- *****************************************************************************/
-typedef struct rtc5200 {
- volatile ulong tsr; /* MBAR+0x800: time set register */
- volatile ulong dsr; /* MBAR+0x804: data set register */
- volatile ulong nysr; /* MBAR+0x808: new year and stopwatch register */
- volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */
- volatile ulong ctr; /* MBAR+0x810: current time register */
- volatile ulong cdr; /* MBAR+0x814: current data register */
- volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */
- volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */
- volatile ulong trdr; /* MBAR+0x820: test register/divides register */
-} RTC5200;
-
-#define RTC_SET 0x02000000
-#define RTC_PAUSE 0x01000000
-
-/*****************************************************************************
- * get time
- *****************************************************************************/
-int rtc_get (struct rtc_time *tmp)
-{
- RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
- ulong time, date, time2;
-
- /* read twice to avoid getting a funny time when the second is just changing */
- do {
- time = rtc->ctr;
- date = rtc->cdr;
- time2 = rtc->ctr;
- } while (time != time2);
-
- tmp->tm_year = date & 0xfff;
- tmp->tm_mon = (date >> 24) & 0xf;
- tmp->tm_mday = (date >> 16) & 0x1f;
- tmp->tm_wday = (date >> 21) & 7;
- /* sunday is 7 in 5200 but 0 in rtc_time */
- if (tmp->tm_wday == 7)
- tmp->tm_wday = 0;
- tmp->tm_hour = (time >> 16) & 0x1f;
- tmp->tm_min = (time >> 8) & 0x3f;
- tmp->tm_sec = time & 0x3f;
-
- debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- return 0;
-}
-
-/*****************************************************************************
- * set time
- *****************************************************************************/
-int rtc_set (struct rtc_time *tmp)
-{
- RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
- ulong time, date, year;
-
- debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- time = (tmp->tm_hour << 16) | (tmp->tm_min << 8) | tmp->tm_sec;
- date = (tmp->tm_mon << 16) | tmp->tm_mday;
- if (tmp->tm_wday == 0)
- date |= (7 << 8);
- else
- date |= (tmp->tm_wday << 8);
- year = tmp->tm_year;
-
- /* mask unwanted bits that might show up when rtc_time is corrupt */
- time &= 0x001f3f3f;
- date &= 0x001f071f;
- year &= 0x00000fff;
-
- /* pause and set the RTC */
- rtc->nysr = year;
- rtc->dsr = date | RTC_PAUSE;
- udelay (1000);
- rtc->dsr = date | RTC_PAUSE | RTC_SET;
- udelay (1000);
- rtc->dsr = date | RTC_PAUSE;
- udelay (1000);
- rtc->dsr = date;
- udelay (1000);
-
- rtc->tsr = time | RTC_PAUSE;
- udelay (1000);
- rtc->tsr = time | RTC_PAUSE | RTC_SET;
- udelay (1000);
- rtc->tsr = time | RTC_PAUSE;
- udelay (1000);
- rtc->tsr = time;
- udelay (1000);
-
- return 0;
-}
-
-/*****************************************************************************
- * reset rtc circuit
- *****************************************************************************/
-void rtc_reset (void)
-{
- return; /* nothing to do */
-}
-
-#endif
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index f1bd15b..aa64b84 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -133,7 +133,6 @@
serial_initfunc(max3100_serial_initialize);
serial_initfunc(mcf_serial_initialize);
serial_initfunc(ml2_serial_initialize);
-serial_initfunc(mpc512x_serial_initialize);
serial_initfunc(mpc5xx_serial_initialize);
serial_initfunc(mpc8260_scc_serial_initialize);
serial_initfunc(mpc8260_smc_serial_initialize);
@@ -224,7 +223,6 @@
max3100_serial_initialize();
mcf_serial_initialize();
ml2_serial_initialize();
- mpc512x_serial_initialize();
mpc5xx_serial_initialize();
mpc8260_scc_serial_initialize();
mpc8260_smc_serial_initialize();
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index a73b255..ab5a99f 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -26,11 +26,7 @@
obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
-ifdef CONFIG_MPC512X
-obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
-else
obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
-endif
obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o
obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
deleted file mode 100644
index bb4f461..0000000
--- a/drivers/usb/host/ehci-mpc512x.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2010, Damien Dusha, <d.dusha@gmail.com>
- *
- * (C) Copyright 2009, Value Team S.p.A.
- * Francesco Rendine, <francesco.rendine@valueteam.com>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
- *
- * Author: Tor Krill tor@excito.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <pci.h>
-#include <usb.h>
-#include <asm/io.h>
-#include <usb/ehci-ci.h>
-
-#include "ehci.h"
-
-static void fsl_setup_phy(volatile struct ehci_hcor *);
-static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
-static int reset_usb_controller(volatile struct usb_ehci *ehci);
-static void usb_platform_dr_init(volatile struct usb_ehci *ehci);
-
-/*
- * Initialize SOC FSL EHCI Controller
- *
- * This code is derived from EHCI FSL USB Linux driver for MPC5121
- *
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- volatile struct usb_ehci *ehci;
-
- /* Hook the memory mapped registers for EHCI-Controller */
- ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
- *hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
- *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
- HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
- /* configure interface for UTMI_WIDE */
- usb_platform_dr_init(ehci);
-
- /* Init Phy USB0 to UTMI+ */
- fsl_setup_phy(*hcor);
-
- /* Set to host mode */
- fsl_platform_set_host_mode(ehci);
-
- /*
- * Setting the burst size seems to be required to prevent the
- * USB from hanging when communicating with certain USB Mass
- * storage devices. This was determined by analysing the
- * EHCI registers under Linux vs U-Boot and burstsize was the
- * major non-interrupt related difference between the two
- * implementations.
- *
- * Some USB sticks behave better than others. In particular,
- * the following USB stick is especially problematic:
- * 0930:6545 Toshiba Corp
- *
- * The burstsize is set here to match the Linux implementation.
- */
- out_be32(&ehci->burstsize, FSL_EHCI_TXPBURST(8) |
- FSL_EHCI_RXPBURST(8));
-
- return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
- volatile struct usb_ehci *ehci;
- int exit_status = 0;
-
- /* Reset the USB controller */
- ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
- exit_status = reset_usb_controller(ehci);
-
- return exit_status;
-}
-
-static int reset_usb_controller(volatile struct usb_ehci *ehci)
-{
- unsigned int i;
-
- /* Command a reset of the USB Controller */
- out_be32(&(ehci->usbcmd), CMD_RESET);
-
- /* Wait for the reset process to finish */
- for (i = 65535 ; i > 0 ; i--) {
- /*
- * The host will set this bit to zero once the
- * reset process is complete
- */
- if ((in_be32(&(ehci->usbcmd)) & CMD_RESET) == 0)
- return 0;
- }
-
- /* Hub did not reset in time */
- return -1;
-}
-
-static void fsl_setup_phy(volatile struct ehci_hcor *hcor)
-{
- uint32_t portsc;
-
- portsc = ehci_readl(&hcor->or_portsc[0]);
- portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
-
- /* Enable the phy mode to UTMI Wide */
- portsc |= PORT_PTS_PTW;
- portsc |= PORT_PTS_UTMI;
-
- ehci_writel(&hcor->or_portsc[0], portsc);
-}
-
-static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci)
-{
- uint32_t temp;
-
- temp = in_le32(&ehci->usbmode);
- temp |= CM_HOST | ES_BE;
- out_le32(&ehci->usbmode, temp);
-}
-
-static void usb_platform_dr_init(volatile struct usb_ehci *ehci)
-{
- /* Configure interface for UTMI_WIDE */
- out_be32(&ehci->isiphyctrl, PHYCTRL_PHYE | PHYCTRL_PXE);
- out_be32(&ehci->usbgenctrl, GC_PPP | GC_PFP );
-}
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index b5e0304..272df07 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -53,7 +53,6 @@
#if defined(CONFIG_CPU_ARM920T) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
- defined(CONFIG_MPC5200) || \
defined(CONFIG_SYS_OHCI_USE_NPS)
# define OHCI_USE_NPS /* force NoPowerSwitching mode */
#endif
@@ -1088,10 +1087,6 @@
*phwHeadP &= m32_swap(0xfffffff2);
flush_dcache_ed(td_list->ed);
}
-#ifdef CONFIG_MPC5200
- td_list->hwNextTD = 0;
- flush_dcache_td(td_list);
-#endif
}
}
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index db0924c..2350831 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -115,9 +115,7 @@
__u32 hwNextTD; /* Next TD Pointer */
__u32 hwBE; /* Memory Buffer End Pointer */
-/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
__u16 hwPSW[MAXPSW];
-/* #endif */
__u8 unused;
__u8 index;
struct ed *ed;
@@ -141,13 +139,8 @@
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
__u32 int_table[NUM_INTS]; /* Interrupt ED table */
-#if defined(CONFIG_MPC5200)
- __u16 pad1; /* set to 0 on each frame_no change */
- __u16 frame_no; /* current frame number */
-#else
__u16 frame_no; /* current frame number */
__u16 pad1; /* set to 0 on each frame_no change */
-#endif
__u32 done_head; /* info returned for an interrupt */
u8 reserved_for_hc[116];
} __attribute__((aligned(256)));