ColdFire: Add M5373EVB platform support - 2
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off by: John Rigby <jrigby@freescale.com>
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 912753d..852d941 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -169,7 +169,7 @@
#endif
#endif /* CONFIG_M5282 */
-#ifdef CONFIG_M5329
+#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
#include <asm/immap_5329.h>
#include <asm/m5329.h>
@@ -197,7 +197,7 @@
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
-#endif /* CONFIG_M5329 */
+#endif /* CONFIG_M5329 && CONFIG_M5373 */
#ifdef CONFIG_M54455
#include <asm/immap_5445x.h>
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 7ff0b93..7678406 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -378,91 +378,133 @@
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
+#ifdef CONFIG_M5329
u8 podr_fech; /* 0x00 */
u8 podr_fecl; /* 0x01 */
+#else
+ u16 res00; /* 0x00 - 0x01 */
+#endif
u8 podr_ssi; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_be; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_pwm; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
- u8 res1; /* 0x08 */
+ u8 res08; /* 0x08 */
u8 podr_uart; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
- u8 res2; /* 0x0C */
+#ifdef CONFIG_M5329
+ u8 res0C; /* 0x0C */
u8 podr_lcddatah; /* 0x0D */
u8 podr_lcddatam; /* 0x0E */
u8 podr_lcddatal; /* 0x0F */
u8 podr_lcdctlh; /* 0x10 */
u8 podr_lcdctll; /* 0x11 */
+#else
+ u16 res0C; /* 0x0C - 0x0D */
+ u8 podr_fech; /* 0x0E */
+ u8 podr_fecl; /* 0x0F */
+ u16 res10[3]; /* 0x10 - 0x15 */
+#endif
/* Port Data Direction Registers */
- u16 res3; /* 0x12 - 0x13 */
+#ifdef CONFIG_M5329
+ u16 res12; /* 0x12 - 0x13 */
u8 pddr_fech; /* 0x14 */
u8 pddr_fecl; /* 0x15 */
+#endif
u8 pddr_ssi; /* 0x16 */
u8 pddr_busctl; /* 0x17 */
u8 pddr_be; /* 0x18 */
u8 pddr_cs; /* 0x19 */
u8 pddr_pwm; /* 0x1A */
u8 pddr_feci2c; /* 0x1B */
- u8 res4; /* 0x1C */
+ u8 res1C; /* 0x1C */
u8 pddr_uart; /* 0x1D */
u8 pddr_qspi; /* 0x1E */
u8 pddr_timer; /* 0x1F */
- u8 res5; /* 0x20 */
+#ifdef CONFIG_M5329
+ u8 res20; /* 0x20 */
u8 pddr_lcddatah; /* 0x21 */
u8 pddr_lcddatam; /* 0x22 */
u8 pddr_lcddatal; /* 0x23 */
u8 pddr_lcdctlh; /* 0x24 */
u8 pddr_lcdctll; /* 0x25 */
- u16 res6; /* 0x26 - 0x27 */
+ u16 res26; /* 0x26 - 0x27 */
+#else
+ u16 res20; /* 0x20 - 0x21 */
+ u8 pddr_fech; /* 0x22 */
+ u8 pddr_fecl; /* 0x23 */
+ u16 res24[3]; /* 0x24 - 0x29 */
+#endif
/* Port Data Direction Registers */
+#ifdef CONFIG_M5329
u8 ppd_fech; /* 0x28 */
u8 ppd_fecl; /* 0x29 */
+#endif
u8 ppd_ssi; /* 0x2A */
u8 ppd_busctl; /* 0x2B */
u8 ppd_be; /* 0x2C */
u8 ppd_cs; /* 0x2D */
u8 ppd_pwm; /* 0x2E */
u8 ppd_feci2c; /* 0x2F */
- u8 res7; /* 0x30 */
+ u8 res30; /* 0x30 */
u8 ppd_uart; /* 0x31 */
u8 ppd_qspi; /* 0x32 */
u8 ppd_timer; /* 0x33 */
- u8 res8; /* 0x34 */
+#ifdef CONFIG_M5329
+ u8 res34; /* 0x34 */
u8 ppd_lcddatah; /* 0x35 */
u8 ppd_lcddatam; /* 0x36 */
u8 ppd_lcddatal; /* 0x37 */
u8 ppd_lcdctlh; /* 0x38 */
u8 ppd_lcdctll; /* 0x39 */
- u16 res9; /* 0x3A - 0x3B */
+ u16 res3A; /* 0x3A - 0x3B */
+#else
+ u16 res34; /* 0x34 - 0x35 */
+ u8 ppd_fech; /* 0x36 */
+ u8 ppd_fecl; /* 0x37 */
+ u16 res38[3]; /* 0x38 - 0x3D */
+#endif
/* Port Clear Output Data Registers */
- u8 pclrr_fech; /* 0x3C */
- u8 pclrr_fecl; /* 0x3D */
+#ifdef CONFIG_M5329
+ u8 res3C; /* 0x3C */
+ u8 pclrr_fech; /* 0x3D */
+ u8 pclrr_fecl; /* 0x3E */
+#else
u8 pclrr_ssi; /* 0x3E */
+#endif
u8 pclrr_busctl; /* 0x3F */
u8 pclrr_be; /* 0x40 */
u8 pclrr_cs; /* 0x41 */
u8 pclrr_pwm; /* 0x42 */
u8 pclrr_feci2c; /* 0x43 */
- u8 res10; /* 0x44 */
+ u8 res44; /* 0x44 */
u8 pclrr_uart; /* 0x45 */
u8 pclrr_qspi; /* 0x46 */
u8 pclrr_timer; /* 0x47 */
- u8 res11; /* 0x48 */
- u8 pclrr_lcddatah; /* 0x49 */
- u8 pclrr_lcddatam; /* 0x4A */
- u8 pclrr_lcddatal; /* 0x4B */
+#ifdef CONFIG_M5329
+ u8 pclrr_lcddatah; /* 0x48 */
+ u8 pclrr_lcddatam; /* 0x49 */
+ u8 pclrr_lcddatal; /* 0x4A */
+ u8 pclrr_ssi; /* 0x4B */
u8 pclrr_lcdctlh; /* 0x4C */
u8 pclrr_lcdctll; /* 0x4D */
- u16 res12; /* 0x4E - 0x4F */
+ u16 res4E; /* 0x4E - 0x4F */
+#else
+ u16 res48; /* 0x48 - 0x49 */
+ u8 pclrr_fech; /* 0x4A */
+ u8 pclrr_fecl; /* 0x4B */
+ u8 res4C[5]; /* 0x4C - 0x50 */
+#endif
/* Pin Assignment Registers */
+#ifdef CONFIG_M5329
u8 par_fec; /* 0x50 */
+#endif
u8 par_pwm; /* 0x51 */
u8 par_busctl; /* 0x52 */
u8 par_feci2c; /* 0x53 */
@@ -472,15 +514,20 @@
u16 par_uart; /* 0x58 */
u16 par_qspi; /* 0x5A */
u8 par_timer; /* 0x5C */
+#ifdef CONFIG_M5329
u8 par_lcddata; /* 0x5D */
u16 par_lcdctl; /* 0x5E */
+#else
+ u8 par_fec; /* 0x5D */
+ u16 res5E; /* 0x5E - 0x5F */
+#endif
u16 par_irq; /* 0x60 */
- u16 res16; /* 0x62 - 0x63 */
+ u16 res62; /* 0x62 - 0x63 */
/* Mode Select Control Registers */
u8 mscr_flexbus; /* 0x64 */
u8 mscr_sdram; /* 0x65 */
- u16 res17; /* 0x66 - 0x67 */
+ u16 res66; /* 0x66 - 0x67 */
/* Drive Strength Control Registers */
u8 dscr_i2c; /* 0x68 */
@@ -490,7 +537,11 @@
u8 dscr_qspi; /* 0x6C */
u8 dscr_timer; /* 0x6D */
u8 dscr_ssi; /* 0x6E */
+#ifdef CONFIG_M5329
u8 dscr_lcd; /* 0x6F */
+#else
+ u8 res6F; /* 0x6F */
+#endif
u8 dscr_debug; /* 0x70 */
u8 dscr_clkrst; /* 0x71 */
u8 dscr_irq; /* 0x72 */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index 8316fcf..c1669dc 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -1118,6 +1118,7 @@
#define GPIO_PCLRR_LCDCTLL7 (0x80)
/* Bit definitions and macros for GPIO_PAR_FEC */
+#ifdef CONFIG_M5329
#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
#define GPIO_PAR_FEC_7W_GPIO (0x00)
@@ -1126,6 +1127,10 @@
#define GPIO_PAR_FEC_MII_GPIO (0x00)
#define GPIO_PAR_FEC_MII_UART (0x01)
#define GPIO_PAR_FEC_MII_FEC (0x03)
+#else
+#define GPIO_PAR_FEC_7W_FEC (0x08)
+#define GPIO_PAR_FEC_MII_FEC (0x02)
+#endif
/* Bit definitions and macros for GPIO_PAR_PWM */
#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
new file mode 100644
index 0000000..6bfffa1
--- /dev/null
+++ b/include/configs/M5373EVB.h
@@ -0,0 +1,267 @@
+/*
+ * Configuation settings for the Freescale MCF5373 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5373EVB_H
+#define _M5373EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x /* define processor family */
+#define CONFIG_M5373 /* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef NANDFLASH_SIZE
+# define CONFIG_CMD_NAND
+#endif
+
+#define CFG_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x58000
+#define CFG_IMMR CFG_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5373EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 2ffff;" \
+ "era 0 2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x40010000
+
+#define CFG_HZ 1000
+#define CFG_CLK 80000000
+#define CFG_CPU_CLK CFG_CLK * 3
+
+#define CFG_MBAR 0xFC000000
+
+#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x80000000
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x221
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x40000000
+#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SDRAM_CFG1 0x53722730
+#define CFG_SDRAM_CFG2 0x56670000
+#define CFG_SDRAM_CTRL 0xE1092000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x018D0000
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef NANDFLASH_SIZE
+# define CFG_MAX_NAND_DEVICE 1
+# define CFG_NAND_BASE CFG_CS2_BASE
+# define CFG_NAND_SIZE 1
+# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+# define NAND_MAX_CHIPS 1
+# define NAND_ALLOW_ERASE_ALL 1
+# define CONFIG_JFFS2_NAND 1
+# define CONFIG_JFFS2_DEV "nand0"
+# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
+# define CONFIG_JFFS2_PART_OFFSET 0x00000000
+#endif
+
+#define CFG_FLASH_BASE CFG_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x007f0001
+#define CFG_CS0_CTRL 0x00001fa0
+
+#define CFG_CS1_BASE 0x10000000
+#define CFG_CS1_MASK 0x001f0001
+#define CFG_CS1_CTRL 0x002A3780
+
+#ifdef NANDFLASH_SIZE
+#define CFG_CS2_BASE 0x20000000
+#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
+#define CFG_CS2_CTRL 0x00001f60
+#endif
+
+#endif /* _M5373EVB_H */