commit 6f7b5a2b0342a84cbf0855c08f66db565a12a26a
author Anup Patel <Anup.Patel@wdc.com> Tue Jun 25 06:31:08 2019 +0000
committer Andes <uboot@andestech.com> Fri Jul 19 14:24:51 2019 +0800
tree 756f5befa0841e33c43e8c3ffb3cacf66a0c831a
parent 00a156d5862e6a6bf681f46c1c4d97ec6d102e31

clk: sifive: Sync-up WRPLL library with upstream Linux

Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

drivers/clk/sifive/fu540-prci.c

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 56084db..cdbf35e 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -174,7 +174,7 @@
  * bypass mux is not glitchless.
  */
 struct __prci_wrpll_data {
-	struct analogbits_wrpll_cfg c;
+	struct wrpll_cfg c;
 	void (*bypass)(struct __prci_data *pd);
 	void (*no_bypass)(struct __prci_data *pd);
 	u8 cfg0_offs;
@@ -244,7 +244,7 @@
 
 /**
  * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
- * @c: ptr to a struct analogbits_wrpll_cfg record to write config into
+ * @c: ptr to a struct wrpll_cfg record to write config into
  * @r: value read from the PRCI PLL configuration register
  *
  * Given a value @r read from an FU540 PRCI PLL configuration register,
@@ -256,7 +256,7 @@
  *
  * Context: Any context.
  */
-static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
+static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
 {
 	u32 v;
 
@@ -287,7 +287,7 @@
 
 /**
  * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
- * @c: pointer to a struct analogbits_wrpll_cfg record containing the PLL's cfg
+ * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
  *
  * Using a set of WRPLL configuration values pointed to by @c,
  * assemble a PRCI PLL configuration register value, and return it to
@@ -300,7 +300,7 @@
  * Returns: a value suitable for writing into a PRCI PLL configuration
  *          register
  */
-static u32 __prci_wrpll_pack(struct analogbits_wrpll_cfg *c)
+static u32 __prci_wrpll_pack(struct wrpll_cfg *c)
 {
 	u32 r = 0;
 
@@ -348,11 +348,11 @@
  */
 static void __prci_wrpll_write_cfg(struct __prci_data *pd,
 				   struct __prci_wrpll_data *pwd,
-				   struct analogbits_wrpll_cfg *c)
+				   struct wrpll_cfg *c)
 {
 	__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
 
-	memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));
+	memcpy(&pwd->c, c, sizeof(struct wrpll_cfg));
 }
 
 /* Core clock mux control */
@@ -403,7 +403,7 @@
 {
 	struct __prci_wrpll_data *pwd = pc->pwd;
 
-	return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);
+	return wrpll_calc_output_rate(&pwd->c, parent_rate);
 }
 
 static unsigned long sifive_fu540_prci_wrpll_round_rate(
@@ -412,13 +412,13 @@
 						unsigned long *parent_rate)
 {
 	struct __prci_wrpll_data *pwd = pc->pwd;
-	struct analogbits_wrpll_cfg c;
+	struct wrpll_cfg c;
 
 	memcpy(&c, &pwd->c, sizeof(c));
 
-	analogbits_wrpll_configure_for_rate(&c, rate, *parent_rate);
+	wrpll_configure_for_rate(&c, rate, *parent_rate);
 
-	return analogbits_wrpll_calc_output_rate(&c, *parent_rate);
+	return wrpll_calc_output_rate(&c, *parent_rate);
 }
 
 static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
@@ -429,7 +429,7 @@
 	struct __prci_data *pd = pc->pd;
 	int r;
 
-	r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
+	r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
 	if (r)
 		return -ERANGE;
 
@@ -438,7 +438,7 @@
 
 	__prci_wrpll_write_cfg(pd, pwd, &pwd->c);
 
-	udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));
+	udelay(wrpll_calc_max_lock_us(&pwd->c));
 
 	if (pwd->no_bypass)
 		pwd->no_bypass(pd);