tree c59b4a9b12fe44520f497cfc919b35c7db4481e0
parent 1f20fc8e504f8bcc3a6120d32fde83ebbfeee96d
author Suman Anna <s-anna@ti.com> 1565994616 -0500
committer Tom Rini <trini@konsulko.com> 1566315998 -0400

ARM: DRA7: Fixup DPLL clock rate fixup logic for newer kernels

The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") updates the kernel device-tree blob to adjust
the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected
in U-Boot. All these DPLL clocks are children of the cm_core_aon clocks
DT node.

The hierarchy of this clocks DT node has changed in newer Linux kernels
starting from v5.0, and this results in a failure in ft_fixup_clocks()
function to update the clock rates on these newer kernels. Fix this by
updating the lookup logic to look through both the newer and older
DT hierarchy paths for the cm_core_aon clocks node.

Signed-off-by: Suman Anna <s-anna@ti.com>