commit 6e5ce31b2883ef783bde9cd81897960d53bbd5a1
author Marek Vasut <marex@denx.de> Thu Mar 15 18:33:23 2012 +0000
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Thu Mar 29 07:57:08 2012 +0200
tree 5b94e43db46a0f6baf1329f4b81843bebb9423d5
parent 6e48cf3ed0bf4d55f80364a8801be055d6b1cd28

i.MX28: Enable caches by default

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

arch/arm/cpu/arm926ejs/mx28/mx28.c

diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index 9bfd83b..cf6d4e9 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -63,6 +63,16 @@
 		;
 }
 
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
 int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {